Typed states for the displayed outbound observations.
Source: paper_references, paper_reference_links, observed 2026-05-10T09:32:19.100780Z
Paper Citation Record · LEDGER
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
As of 4 August 2026, this Paper Citation Record lists 23 of 23 outbound references and 1 inbound Pith citation observation for arXiv:2604.14550.
A citation records a reference. It does not transfer a finding from one paper to another.
Coverage vector
One-hop event checks from named stored sources.
Source: scholarly_work_events, retraction_status_cache, observed 2026-08-04T06:34:03.388597+00:00
Pith citing papers itemized under the disclosed page cap.
Source: paper_references, paper_reference_links, observed 2026-08-01T15:14:08.339342Z
A source-named dated measurement, never combined with another source.
Source: cited_works
Reference resolution
23 of 23 outbound references displayed
- verified exact6
- verified fuzzy15
- unresolved0
- parse uncertain0
- malformed identifier1
- metadata mismatch1
External citation measurements
No source-named external measurement is stored.
Outbound references
Observation 053d8230-1adf-4e5b-a991-b9883a1004a6 · outbound
This paper cites Large Language Models for Software Engineering: A Systematic Literature Review.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Large Language Models for Software Engineering: A Systematic Literature Review
Reference 1
- Resolution
- metadata mismatch
- arxiv_id, observed 2026-05-10T09:33:41.306803Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 433abeaf-255d-4ac8-8bf4-f97ecf89607e · outbound
This paper cites Beyond Synthetic Benchmarks.arXiv:2510.26130, October.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Beyond Synthetic Benchmarks.arXiv:2510.26130, October
Reference 2
- Resolution
- verified exact
- arxiv_id, observed 2026-05-10T09:33:41.316354Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 9579d414-a7ba-452b-bc0e-58dd1d86f06f · outbound
This paper cites Hivegen–hierarchical llm-based verilog generation for scalable chip design.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Hivegen–hierarchical llm-based verilog generation for scalable chip design
Reference 3
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.293660Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 76ed8ee6-deb8-453a-895c-6bdaf176022d · outbound
This paper cites Large language model for verilog code generation: Literature review and the road ahead.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Large language model for verilog code generation: Literature review and the road ahead
Reference 4
- Resolution
- verified exact
- arxiv_id, observed 2026-05-10T09:33:41.313179Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation d62c3dcf-8bf7-48a5-abbe-b3a005c1da50 · outbound
This paper cites Spec2rtl- agent: Automated hardware code generation from complex specifications using llm agent systems.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Spec2rtl- agent: Automated hardware code generation from complex specifications using llm agent systems
Reference 5
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.309144Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation eb8f51e0-7103-4d9a-a89f-4c4fb9f19439 · outbound
This paper cites Rome was not built in a single step: Hierarchical prompting for llm-based chip design.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Rome was not built in a single step: Hierarchical prompting for llm-based chip design
Reference 6
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.301948Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation e636aed3-715c-41d7-98a9-cf76bee472a4 · outbound
This paper cites Assertionforge: Enhancing formal verification assertion generation with structured representation of specifications and rtl.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Assertionforge: Enhancing formal verification assertion generation with structured representation of specifications and rtl
Reference 7
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.297775Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 515b2053-3628-4b53-ae6e-3b84e749ba9a · outbound
This paper cites Automating hardware design and verification from architec- tural papers via a neural-symbolic graph framework.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Automating hardware design and verification from architec- tural papers via a neural-symbolic graph framework
Reference 8
- Resolution
- verified exact
- arxiv_id, observed 2026-05-10T09:33:41.310040Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 49979ff1-4a71-43bb-8367-5a715d47c22f · outbound
This paper cites Verirag: A knowledge graph-augmented rag for verilog and assertion generation.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Verirag: A knowledge graph-augmented rag for verilog and assertion generation
Reference 9
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.299780Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 4fcc3604-1ece-4095-b1d1-e97d92a42ab1 · outbound
This paper cites NotebookLM.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs NotebookLM
Reference 10
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.295650Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 08c788a2-f8a8-4e84-9fea-825debb30519 · outbound
This paper cites Chatcpu: An agile cpu design and verification platform with llm.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Chatcpu: An agile cpu design and verification platform with llm
Reference 11
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.306522Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 14bdc74a-da8f-481d-8584-ec583f92abb7 · outbound
This paper cites Available: https://doi.org/10.1145/3649329.3658493.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Available: https://doi.org/10.1145/3649329.3658493
Reference 12
- Resolution
- verified exact
- arxiv_id, observed 2026-05-10T09:33:40.766208Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation a281d0bd-8fdf-45cf-a344-2d4ce2a88783 · outbound
This paper cites Openroad project: Toward autonomous ic design.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Openroad project: Toward autonomous ic design
Reference 13
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.291553Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 451d543f-8478-4898-b6a8-38818cb1d1a5 · outbound
This paper cites Icarus verilog.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Icarus verilog
Reference 14
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.304250Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 42c3fb8e-c534-44c4-b421-3595914817f2 · outbound
This paper cites Claude Sonnet 4.6.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Claude Sonnet 4.6
Reference 15
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.283081Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 81fcec29-adc6-4784-af01-1232b722b6df · outbound
This paper cites Yosys open synthesis suite.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Yosys open synthesis suite
Reference 16
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.287541Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 426fa53d-7697-40d7-a423-8c804975d8d8 · outbound
This paper cites Openlane 2: Making the most popular open source asic implementation flow.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Openlane 2: Making the most popular open source asic implementation flow
Reference 17
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.281357Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 202f488a-01bd-46cc-b982-bdf8782f4231 · outbound
This paper cites The risc-v instruction set manual, volume i: User-level isa, version 2.1.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs The risc-v instruction set manual, volume i: User-level isa, version 2.1
Reference 18
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.289746Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation d3ff1257-26fe-4d7b-9a7d-6fe037180bea · outbound
This paper cites Autogen: Enabling next-gen llm applications via multi-agent conversations.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Autogen: Enabling next-gen llm applications via multi-agent conversations
Reference 19
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.285296Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 07a15a0b-2ecc-4db1-890b-af08e5d41bc5 · outbound
This paper cites Gpt-4o mini: advancing cost-efficient intelligence.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Gpt-4o mini: advancing cost-efficient intelligence
Reference 20
- Resolution
- verified fuzzy
- raw_fallback, observed 2026-05-20T17:03:42.279191Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 540426a7-8354-4644-8a06-8ae6a06855b0 · outbound
This paper cites NIST Special Publication 800-230 (Initial Public Draft), National Insti- tute of Standards and Technology (Apr 2026).https://doi.org/10.6028/NIST.
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs NIST Special Publication 800-230 (Initial Public Draft), National Insti- tute of Standards and Technology (Apr 2026).https://doi.org/10.6028/NIST
Reference 21
- Resolution
- malformed identifier
- doi_truncated, observed 2026-05-10T09:33:40.762166Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 2cac03e0-6c1b-48d5-88a1-accc46fc959a · outbound
This paper cites Digital signature standard (dss).
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs Digital signature standard (dss)
Reference 22
- Resolution
- verified exact
- doi, observed 2026-05-10T09:33:40.759339Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Observation 579b74aa-0419-421b-bbe9-79b2a5ac86f1 · outbound
This paper cites The Keyed -Hash Message Authentication Code (HMAC).
VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs The Keyed -Hash Message Authentication Code (HMAC)
Reference 23
- Resolution
- verified exact
- doi, observed 2026-05-10T09:33:40.756531Z
Source-reported events for the cited work
No event found in the named queried sources as of 2026-08-04T06:34:03.388597+00:00.
Pith citing papers
Observation dc824629-bea8-437c-9813-9a024cd2f868 · inbound
A Progressive Approach to Synthesizable RTL Design Generation Using LLMs cites this paper.
A Progressive Approach to Synthesizable RTL Design Generation Using LLMs VeriGraphi: A Multi-Agent Framework of Hierarchical RTL Generation for Large Hardware Designs
Reference 8
- Resolution
- unresolved
- no resolver link, observed 2026-08-01T15:14:08.339342Z
Source-reported events for the cited work
Unavailable: canonical work link unavailable.