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arxiv: 2605.27601 · v1 · pith:ZPW62TZ2new · submitted 2026-05-26 · 💻 cs.DC · cs.LG· cs.PF

A Methodology to Assess Power Modeling in Energy-Aware Federated Learning on Heterogeneous Mobile Devices

Chaimae Jallouli , Karim Boubouh , Robert Basmadjian This is my paper

Pith reviewed 2026-06-29 15:22 UTC · model grok-4.3

classification 💻 cs.DC cs.LGcs.PF
keywords CPU power estimationfederated learningenergy efficiencymobile devicesARM SoCspower modelingheterogeneous computing
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The pith

An analytical CMOS-based CPU power model achieves under 10% error on Android devices and enables 1.4 times lower energy use in federated learning than approximate models.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces a software-only methodology to estimate CPU power on heterogeneous multi-cluster ARM SoCs by mapping voltage rails to clusters. This allows use of an analytical CMOS-based model instead of the simplified approximations common in energy-aware federated learning. On two commodity Android devices the analytical model stays within 10% error while approximations reach errors as high as 959%. When plugged into the AnycostFL framework the accurate model delivers the target 80% accuracy at 1.4 times lower energy consumption.

Core claim

A reproducible CPU power estimation methodology that combines a rail-to-cluster mapping technique with the analytical CMOS-based model predicts CPU power with errors below 10% on heterogeneous Android devices, enabling the same 80% model accuracy in AnycostFL while consuming 1.4 times less energy than when the approximate model is used.

What carries the argument

Rail-to-cluster mapping technique that retrieves cluster-level supply voltage from software-accessible information on multi-cluster ARM SoCs.

If this is right

  • Energy-aware federated learning frameworks can select computation schedules that actually minimize energy rather than misestimate it.
  • Approximate power models risk leading to decisions that waste energy while still reaching the target accuracy.
  • The methodology removes the need for external measurement hardware when applying analytical models to commodity mobile devices.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same mapping approach could be tested on non-Android ARM platforms or other energy-aware distributed training systems.
  • Extending the model to include GPU or memory power on the same devices would give a fuller picture of total energy.
  • If the mapping holds across more SoC vendors, it would allow broader adoption of analytical models in mobile machine learning without custom hardware.

Load-bearing premise

The rail-to-cluster mapping can reliably retrieve cluster-level supply voltages on heterogeneous ARM SoCs using only software-accessible information without external hardware or extra device calibration.

What would settle it

Direct power measurements on additional Android devices with different multi-cluster SoC designs, comparing the analytical model's predictions against measured values across varied workloads.

Figures

Figures reproduced from arXiv: 2605.27601 by Chaimae Jallouli, Karim Boubouh, Robert Basmadjian.

Figure 1
Figure 1. Figure 1: Main pipeline for computing CPU dynamic power on heterogeneous ARM-based mobile [PITH_FULL_IMAGE:figures/full_fig_p004_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Dynamic power prediction comparison across analytical and approximate models on [PITH_FULL_IMAGE:figures/full_fig_p010_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Cumulative computation energy vs. Accuracy of AnycostFL on (a) Fashion-MNIST and [PITH_FULL_IMAGE:figures/full_fig_p011_3.png] view at source ↗
read the original abstract

Estimating CPU power on heterogeneous ARM-based commodity devices is challenging due to limited access to CPU's voltage domains. As a result, state-of-the-art energy-aware Federated Learning (FL) frameworks typically rely on simplified approximate power models to estimate computation energy, rather than the more accurate analytical CMOS-based model. To bridge this gap, we propose a reproducible CPU power estimation methodology combined with a rail-to-cluster mapping technique to retrieve cluster-level supply voltage. We evaluate our approach on two commodity Android devices and show that the analytical model predicts CPU power with errors below 10%, whereas the approximate model incurs errors of up to 959%. Using AnycostFL, a state-of-the-art energy-aware FL framework, we show that the analytical model achieves the same 80% model accuracy while consuming 1.4x less energy than the approximate model. These results highlight that approximate models can severely misestimate computation energy and lead to suboptimal decisions. This work facilitates the use of analytical CPU power models on heterogeneous multi-cluster ARM-based mobile SoCs without additional hardware support or external power measurement tools.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 0 minor

Summary. The paper proposes a reproducible methodology for CPU power estimation on heterogeneous multi-cluster ARM SoCs that combines an analytical CMOS-based power model with a rail-to-cluster mapping technique to recover per-cluster supply voltage from software-accessible registers. Evaluated on two Android devices, the analytical model achieves <10% prediction error while an approximate model reaches 959% error; when plugged into AnycostFL, the analytical model yields the same 80% target accuracy at 1.4x lower energy.

Significance. If the rail-to-cluster mapping proves robust, the work would enable more accurate energy-aware device selection and scheduling in federated learning on commodity mobile hardware without external measurement equipment, directly addressing a practical barrier that currently forces frameworks to rely on crude approximations.

major comments (2)
  1. [Methodology] Methodology (rail-to-cluster mapping): the central claim that the analytical model yields <10% error depends on accurate cluster-level voltage as input to the CMOS power equation; the manuscript validates the mapping only on the two tested devices and provides no independent cross-device verification or parameter-free derivation that would establish correctness on unseen heterogeneous ARM SoCs.
  2. [Evaluation] Evaluation section: the reported 1.4x energy reduction in AnycostFL is obtained by substituting the two power models into the same FL workload; without evidence that the mapping was derived without external hardware measurements during development, the error bounds and energy savings cannot be assumed to transfer beyond the two evaluated devices.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the detailed and constructive review. We address the two major comments point-by-point below, providing clarifications on the methodology and evaluation while proposing targeted revisions to improve the manuscript.

read point-by-point responses

  1. Referee: [Methodology] Methodology (rail-to-cluster mapping): the central claim that the analytical model yields <10% error depends on accurate cluster-level voltage as input to the CMOS power equation; the manuscript validates the mapping only on the two tested devices and provides no independent cross-device verification or parameter-free derivation that would establish correctness on unseen heterogeneous ARM SoCs.

    Authors: The rail-to-cluster mapping is constructed exclusively from standard, software-accessible Linux kernel interfaces (CPUFreq sysfs entries and device-tree voltage domain descriptions) that are present on heterogeneous ARM SoCs; no device-specific parameters or external calibration are required. We will revise the methodology section to include the complete derivation steps, pseudocode, and explicit statement that the procedure is parameter-free once the kernel-exposed rails are read. While we acknowledge that additional devices would further strengthen generalizability claims, the two evaluated SoCs already differ in cluster count, voltage domain organization, and kernel version, providing initial evidence of transferability. The source code for the mapping will remain publicly available to enable independent verification. revision: partial

  2. Referee: [Evaluation] Evaluation section: the reported 1.4x energy reduction in AnycostFL is obtained by substituting the two power models into the same FL workload; without evidence that the mapping was derived without external hardware measurements during development, the error bounds and energy savings cannot be assumed to transfer beyond the two evaluated devices.

    Authors: No external hardware measurements were used at any stage, including during development of the mapping. All voltage values were obtained directly from the same software registers later used at runtime; the <10% error figures were computed against on-device power readings collected via identical software interfaces. We will add an explicit paragraph in the evaluation section documenting this process and reiterating that the methodology requires no external equipment. Consequently, the 1.4x energy saving is a direct consequence of substituting the more accurate analytical model (whose error was measured on-device) into AnycostFL, and the same substitution can be performed on any other device exposing the same kernel interfaces. revision: yes

Circularity Check

0 steps flagged

No circularity: empirical methodology validated by direct device measurements

full rationale

The paper describes a reproducible measurement methodology for retrieving cluster-level voltage on heterogeneous ARM SoCs and compares an analytical CMOS power model against an approximate model through experiments on two Android devices. Error bounds (<10% vs. up to 959%) and the 1.4x energy savings in AnycostFL are obtained by executing the identical FL workload under each model and recording actual outcomes; these results do not reduce to fitted parameters or self-citations by construction. The central claims rest on external hardware-independent measurements rather than any derivation that is definitionally equivalent to its inputs.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

The central claim rests on the assumption that the rail-to-cluster mapping can be performed from software-accessible registers alone and that the two tested devices are representative of heterogeneous ARM mobile SoCs. No free parameters are explicitly fitted in the abstract; the analytical CMOS model itself is treated as standard physics.

axioms (1)
  • domain assumption The analytical CMOS power equation remains valid for modern mobile ARM clusters when supplied with accurate per-cluster voltage.
    Invoked when claiming <10% prediction error; the abstract treats the CMOS model as the ground truth against which approximations are judged.

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