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REVIEW 2 major objections 2 minor 202 references

ScaleDisturb exploits temporal asymmetry by extending aggressor row open times differently to induce DRAM bitflips after fewer activations than prior patterns.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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T0 review · grok-4.3

2026-06-27 21:39 UTC pith:JK34M356

load-bearing objection ScaleDisturb uses asymmetric aggressor-row open times to cut activations needed for bitflips, with data from 196 DDR4 chips plus a PoC, though software timing control is the part that still needs scrutiny. the 2 major comments →

arxiv 2606.07761 v1 pith:JK34M356 submitted 2026-06-05 cs.CR cs.AR

ScaleDisturb: Exploiting Temporal Asymmetry to Amplify Read Disturbance in Modern DRAM Chips

Jikun Wang , Haocong Luo , Ataberk Olgun , \.Ismail Emir Y\"uksel , A. Giray Ya\u{g}l{\i}k\c{c}{\i} , Yu Liang , F. Nisa Bostanc{\i} , Mohammad Sadrosadati
show 1 more author
Onur Mutlu
This is my paper
classification cs.CR cs.AR
keywords DRAMread disturbanceRowHammerRowPressbitflipsaccess patternsmemory securitytemporal asymmetry
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents ScaleDisturb, a DRAM access pattern that amplifies read disturbance by asymmetrically extending the open time of two aggressor rows. Experiments across 199 chips show this causes bitflips at significantly fewer row activations than state-of-the-art patterns such as RowHammer and RowPress. The pattern makes attacks easier on every tested chip and shows that vulnerability grows as manufacturing nodes shrink. A user-level proof-of-concept attack on a real system produces more bitflips than existing methods, and four mitigation approaches are evaluated.

Core claim

ScaleDisturb is a new DRAM access pattern that amplifies read disturbance by asymmetrically extending the open time of two aggressor rows. Rigorous characterization of 196 DDR4 and 3 HBM2 chips shows that it leads to bitflips at significantly fewer row activations than state-of-the-art memory access patterns, makes read disturbance attacks easier across all tested DRAM chips, and increases DRAM vulnerability to read disturbance as manufacturing technology scales down to smaller node sizes. A proof-of-concept attack on a real system where a user-level program leverages ScaleDisturb induces more bitflips than state-of-the-art RowHammer and RowPress patterns.

What carries the argument

ScaleDisturb access pattern that asymmetrically extends the open time of two aggressor rows to amplify disturbance effects.

Load-bearing premise

The new access pattern can be implemented from the software stack on real systems and the 199 tested chips are representative of production DRAM behavior under asymmetric timing.

What would settle it

Observation on additional DRAM chips that ScaleDisturb requires the same or greater number of row activations to induce bitflips compared to standard patterns.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • Bitflips occur after significantly fewer row activations than RowHammer or RowPress patterns.
  • Read disturbance attacks become easier to mount from the software stack on all tested chips.
  • DRAM vulnerability to read disturbance grows as manufacturing node sizes decrease.
  • User-level programs can induce more bitflips in real systems using the pattern.
  • Four mitigation strategies are proposed and evaluated to address the amplified disturbance.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Future DRAM controllers may need explicit safeguards against timing asymmetry in row access.
  • Detection software could flag memory access sequences with varying aggressor open durations.
  • The underlying physics of read disturbance might be clarified by targeted study of asymmetric cases.
  • Similar amplification effects could appear in other dense memory technologies under asymmetric control.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 2 minor

Summary. The manuscript introduces ScaleDisturb, a DRAM access pattern that exploits temporal asymmetry by extending the open intervals of two aggressor rows differently to amplify read disturbance effects (RowHammer/RowPress). Characterization on 196 DDR4 and 3 HBM2 chips shows bitflips occurring at significantly fewer activations than prior patterns, with the effect holding across all tested chips and worsening at smaller technology nodes; a user-level PoC attack is demonstrated on real hardware, and four mitigations are evaluated.

Significance. If the central empirical claims hold, the work would be significant for DRAM security, as it identifies a previously unexplored access pattern dimension that lowers the bar for practical attacks and ties vulnerability growth to continued density scaling. The scale of the chip characterization (199 devices) and the inclusion of a real-system PoC are strengths that would make the findings directly relevant to both attack and defense research.

major comments (2)
  1. [§6 (Proof-of-Concept Attack)] §6 (Proof-of-Concept Attack): the description of the user-level PoC does not include timing histograms, open-time delta measurements, or other verification that the intended asymmetric aggressor-row open intervals are actually achieved and sustained under OS scheduling, memory-controller reordering, and cache effects on the tested systems. This verification is load-bearing for the claim that ScaleDisturb is realizable from software and produces the reported reduction in activation count.
  2. [§5 (Experimental Characterization)] §5 (Experimental Characterization): while results are aggregated across 199 chips, the section provides insufficient detail on controls for memory-controller timing behavior or confirmation that observed open-time asymmetry matches the target values on each device; without these, it is unclear whether the reported amplification is attributable to ScaleDisturb rather than test-harness artifacts.
minor comments (2)
  1. [Abstract] The abstract states results for '196 DDR4 and 3 HBM2' chips but does not break down the distribution across technology nodes or manufacturers, which would help assess the scaling claim.
  2. [§3 (ScaleDisturb Pattern)] Notation for the two aggressor rows and their open-time parameters is introduced without an accompanying diagram or equation that explicitly defines the asymmetry ratio used in the experiments.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive comments, which highlight areas where additional verification and detail will strengthen the manuscript. We address each major comment below and will revise accordingly.

read point-by-point responses

  1. Referee: [§6 (Proof-of-Concept Attack)] the description of the user-level PoC does not include timing histograms, open-time delta measurements, or other verification that the intended asymmetric aggressor-row open intervals are actually achieved and sustained under OS scheduling, memory-controller reordering, and cache effects on the tested systems. This verification is load-bearing for the claim that ScaleDisturb is realizable from software and produces the reported reduction in activation count.

    Authors: We agree that explicit verification of the achieved open-time asymmetry under real-system conditions is necessary to support the PoC claims. In the revised manuscript, we will augment §6 with timing histograms, measured open-time deltas, and additional controls demonstrating that the target asymmetry is sustained despite OS scheduling, memory-controller reordering, and cache effects on the evaluated systems. These additions will directly address the concern and confirm the reported activation-count reductions are attributable to ScaleDisturb. revision: yes

  2. Referee: [§5 (Experimental Characterization)] while results are aggregated across 199 chips, the section provides insufficient detail on controls for memory-controller timing behavior or confirmation that observed open-time asymmetry matches the target values on each device; without these, it is unclear whether the reported amplification is attributable to ScaleDisturb rather than test-harness artifacts.

    Authors: We concur that expanded methodological detail is required to rule out test-harness artifacts. The revised §5 will include (i) a description of the memory-controller timing controls employed, (ii) per-device verification that the programmed open-time asymmetry matches the intended targets, and (iii) additional discussion of how the experimental setup isolates ScaleDisturb effects from controller behavior. These clarifications will be added without altering the reported results. revision: yes

Circularity Check

0 steps flagged

No circularity: purely empirical characterization on physical hardware

full rationale

The paper reports direct experimental measurements of bitflip rates under a new access pattern (ScaleDisturb) across 199 real DRAM chips. No equations, fitted parameters, uniqueness theorems, or self-citations are used to derive the central claims; the reported reductions in activation count and scaling trends are observed outcomes rather than quantities constructed from the inputs by definition. The analysis is therefore self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

This is an empirical experimental study; the central claim rests on physical chip measurements rather than mathematical axioms, free parameters, or new postulated entities.

pith-pipeline@v0.9.1-grok · 5836 in / 1055 out tokens · 31536 ms · 2026-06-27T21:39:38.816139+00:00 · methodology

0 comments
read the original abstract

DRAM suffers from read disturbance phenomena (e.g., RowHammer and RowPress), where repeatedly accessing or continuously keeping open a DRAM row (aggressor row) induces bitflips in other physically nearby unaccessed rows (victim rows). The disturbance mechanism is practically exploitable from the software stack and worsens across generations with continued density scaling. DRAM read disturbance is highly sensitive to memory access patterns, yet prior work explores read disturbance under only a limited set of access patterns. We present ScaleDisturb, a new DRAM access pattern that can amplify DRAM read disturbance by asymmetrically extending the open time of two aggressor rows. Our rigorous experimental characterization of 196 DDR4 and 3 HBM2 DRAM chips shows that ScaleDisturb (1) leads to bitflips at significantly fewer row activations, compared to state-of-the-art memory access patterns, (2) makes read disturbance attacks easier across all tested DRAM chips, (3) increases DRAM vulnerability to read disturbance as DRAM manufacturing technology scales down to smaller node sizes. We showcase a proof-of-concept attack on a real system where a user-level program leveraging ScaleDisturb induces more bitflips than state-of-the-art RowHammer and RowPress memory access patterns. We describe and evaluate four solutions for mitigating read disturbance bitflips in the presence of ScaleDisturb and call for more research on the topic.

Figures

Figures reproduced from arXiv: 2606.07761 by A. Giray Ya\u{g}l{\i}k\c{c}{\i}, Ataberk Olgun, F. Nisa Bostanc{\i}, Haocong Luo, \.Ismail Emir Y\"uksel, Jikun Wang, Mohammad Sadrosadati, Onur Mutlu, Yu Liang.

Figure 1
Figure 1. Figure 1: Hierarchical organization of modern DRAM. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FPGA-based DRAM and memory controller testing setup (left) and laboratory (right). Real DDR4 and HBM2 DRAM Chips Tested [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: ScaleDisturb Design Space Metrics. To quantify how ScaleDisturb amplifies DRAM’s vul￾nerability to read disturbance, we examine how ACmin changes as tAggON1 increases under a fixed OTB. A lower ACmin indi￾cates that a victim row exhibits greater vulnerability. For each OTB, we sweep tAggON1 from tRAS to tRAS + OTB in steps of 5% of the OTB, and report the minimum observed ACmin as the final ACmin. For each… view at source ↗
Figure 3
Figure 3. Figure 3: Three DRAM access patterns: (a) double-sided RowHammer, (b) double-sided RowPress, and (c) ScaleDisturb. Open Time Budget. To clarify the row open time distribution in ScaleDisturb access pattern, we define Open Time Budget (OTB) as: OTB =tAggON1 +tAggON2 −2 ·tRAS s.t. tAggON ≥ tRAS (1) By design, both tAggON1 and tAggON2 are greater than or equal to tRAS, ensuring that OTB accounts for the additional open… view at source ↗
Figure 6
Figure 6. Figure 6: shows the normalized ACmin (y-axis) distribution across chips from Samsung, SK Hynix, and Micron. Each violin plot represents the distribution of ACmin at a given OTB (x-axis): whiskers indicate the minimum and maximum values, the dashed line inside denotes the median, and the width at each point reflects the distribution density. We highlight the minimum normalized ACmin for each manufacturer in red text.… view at source ↗
Figure 5
Figure 5. Figure 5: Normalized ACmin distribution across all victim rows, sorted by reduction percentile, for six OTB values (left) and ACmin distribution under RowPress and ScaleDisturb (right) Observation 1. ScaleDisturb reduces ACmin by 9.6% on av￾erage (up to 63%) across all tested rows compared to double￾sided RowPress. Across all tested rows under six OTB values, the normalized ACmin decreases from 1.0 at P0, to 0.904 a… view at source ↗
Figure 7
Figure 7. Figure 7: ACmin distributions across different density-revision chips Observation 4. Newer chips tend to be more vulnerable to ScaleDisturb bitflips. We observe that in the same die density for each tested man￾ufacturer, more advanced technology nodes3 experience higher ScaleDisturb vulnerability. The average ACmin under ScaleDis￾turb decreases by 9.8%, 18.4%, and 62.0% for Samsung (16Gb, A to B), SK Hynix (8Gb, C t… view at source ↗
Figure 8
Figure 8. Figure 8: Three observed ACmin reduction patterns: L-type, R￾type and Flat-type, when sweeping tAggON1. Observation 5. DRAM rows under ScaleDisturb exhibit three major ACmin reduction patterns: L-, R- and Flat-type. We find that as tAggON1 increases, the minimum ACmin of a row may occur at either lower (e.g., 120 ns) or higher (e.g., 480 ns) tAggON1 values, while some rows exhibit little change in ACmin. We hypothes… view at source ↗
Figure 10
Figure 10. Figure 10: shows the ACmin distribution (y-axis) across 300 tests (each box plot) at varying tAggON1 (x-axis), with OTB fixed at 600 ns, for a representative victim row exhibiting R-Type pattern. The top and bottom whiskers denote the maximum and minimum ACmin. We alternate the background color for tAggON1 values. We make two key observations: 0 60 120 180 240 300 360 420 480 540 600 tAggON1 - tRAS (ns) 16K 18K 20K … view at source ↗
Figure 12
Figure 12. Figure 12: ACmin distribution under different access patterns. Observation 12. Victim rows are asymmetrically vulnerable to upper and lower aggressors under single-sided patterns. For all tested OTBs, we observe average ACmin variations of 14.0%, 11.2% and 3.0% between applying single-sided patterns to the upper and lower aggressor rows, for modules S1, H1, and M1, respectively. This indicates that the effects of tw… view at source ↗
Figure 11
Figure 11. Figure 11: Overlap of first-bitflip locations. Observation 10. ScaleDisturb flips a distinct set of cells compared to double-sided RowPress. The first flipped cell within a row differs significantly be￾tween ScaleDisturb and double-sided RowPress across a large fraction of rows. For example, the overlap ratio of 16Gb B-Die chips from Micron decreases to 0.52 at 7.8 µs, indicating that 48% of rows flip at entirely di… view at source ↗
Figure 13
Figure 13. Figure 13: Normalized ACmin and ACmin distribution of HBM2 chips (51%), 16% (49%), 22% (58%), 32% (60%), 40% (63%) than double-sided RowPress across the six evaluated OTBs. We ex￾pect our other observations for DDR4 chips (§4.1 and §4.2) will hold for HBM2 chips as well because both DDR4 and HBM2 DRAM use the same underlying DRAM cell array structure. Takeaway 6. ScaleDisturb widely affects DRAM chips: not only DDR4… view at source ↗
Figure 15
Figure 15. Figure 15: Effect of temperature (50 ◦C and 80 ◦C) on ACmin of ScaleDisturb under Rowstripe0 (top) and Rowstripe1 (bottom). Observation 16. Under Rowstripe0, ScaleDisturb shows limited temperature sensitivity at all OTB values. Under Rowstripe0, a higher temperature of 80 ◦C only slightly changes ACmin compared to 50 ◦C. On average, at 80 ◦C, ACmin changes by +5.1%, +0.6%, and -11.2% for Sam￾sung, SK Hynix, and Micr… view at source ↗
Figure 16
Figure 16. Figure 16: Bitflip counts across rows under different [PITH_FULL_IMAGE:figures/full_fig_p010_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: shows the bitflips distribution across NUM_AGGR_ACTS (shown as ACT on the y-axis labels) and TOTAL_READ. Each subplot shows the number of bitflips (y-axis) versus NUM_READ1 (x-axis), with blue and red bars for ScaleDisturb and double￾sided RowPress, respectively, and RowHammer with yellow backgrounds. We make the following observation: 0 200 ACT = 4 #bitflips RH BF=2 0 4 8 12 16 TOTAL_READ = 16 0 8 16 24 … view at source ↗
Figure 18
Figure 18. Figure 18: Distribution of 64-bit words by bitflip count across [PITH_FULL_IMAGE:figures/full_fig_p010_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: Performance (normalized IPC) of five read disturbance [PITH_FULL_IMAGE:figures/full_fig_p011_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: Energy impact of evaluated read disturbance mitiga [PITH_FULL_IMAGE:figures/full_fig_p011_20.png] view at source ↗
Figure 21
Figure 21. Figure 21: (right) shows an example how TeACUp slows the counter increment of the faster row using DSR. Symmetric Rows Asymmetric Faster Row Asymmetric Slower Row TeACUp (w/ DSR) Threshold Aggressor Row Counter Row Accesses & Time Premature Refresh Delayed Refresh 1:1 tAggON Ratio 1:3 w/o TeACUp 1:3 w/ TeACUp Counter Increment [PITH_FULL_IMAGE:figures/full_fig_p012_21.png] view at source ↗
Figure 22
Figure 22. Figure 22: Performance evaluation: TeACUp normalized to Im￾Press counter update latencies. This design can be adopted in TeACUp to minimize the latency overhead of DSR calculation, enabling concurrent multiple counter queries during bank precharge op￾erations, thereby effectively hiding the associated latency. 8. Related Work To our knowledge, this is the first work to introduce a new read disturbance access pattern… view at source ↗

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Reference graph

Works this paper leans on

202 extracted references · 10 canonical work pages

  1. [1]

    Robert H. Dennard. Field-Effect Transistor Memory, 1968. U.S. Patent 3,387,286

    1968

  2. [2]

    Memory Scaling: A Systems Architecture Perspective

    Onur Mutlu. Memory Scaling: A Systems Architecture Perspective. InIMW, 2013

    2013

  3. [3]

    Memory-Centric Computing: Solving Computing’s Memory Problem

    Onur Mutlu, Ataberk Olgun, and Ismail Emir Yuksel. Memory-Centric Computing: Solving Computing’s Memory Problem. InIMW, 2025

    2025

  4. [4]

    Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors

    Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, and Onur Mutlu. Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors. InISCA, 2014

    2014

  5. [5]

    The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser

    Onur Mutlu. The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser. InDATE, 2017

    2017

  6. [6]

    RowHammer: A Retrospective.TCAD, 2019

    Onur Mutlu and Jeremie S Kim. RowHammer: A Retrospective.TCAD, 2019

    2019

  7. [7]

    Kim, Minesh Patel, Abdullah Giray Ya˘glıkçı, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu

    Jeremie S. Kim, Minesh Patel, Abdullah Giray Ya˘glıkçı, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu. Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques. InISCA, 2020

    2020

  8. [8]

    TRRespass: Exploiting the Many Sides of Target Row Refresh

    Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi. TRRespass: Exploiting the Many Sides of Target Row Refresh. InS&P, 2020

    2020

  9. [9]

    Kim, and Onur Mutlu

    Lois Orosa, A Giray Ya˘glıkçı, Haocong Luo, Ataberk Olgun, Jisung Park, Hasan Hassan, Minesh Patel, Jeremie S. Kim, and Onur Mutlu. A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses. InMICRO, 2021

    2021

  10. [10]

    Kim, Victor van der Veen, Kaveh Razavi, and Onur Mutlu

    Hasan Hassan, Yahya Can Tugrul, Jeremie S. Kim, Victor van der Veen, Kaveh Razavi, and Onur Mutlu. Uncovering in-DRAM RowHammer Protection Mecha- nisms: A New Methodology, Custom RowHammer Patterns, and Implications. In MICRO, 2021

    2021

  11. [11]

    Half-Double: Hammering From the Next Row Over

    Andreas Kogler, Jonas Juffinger, Salman Qazi, Yoongu Kim, Moritz Lipp, Nicolas Boichat, Eric Shiu, Mattias Nissler, and Daniel Gruss. Half-Double: Hammering From the Next Row Over. InUSENIX Security, 2022

    2022

  12. [12]

    RowPress: Amplifying Read Disturbance in Modern DRAM Chips

    Haocong Luo, Ataberk Olgun, Abdullah Giray Ya˘glıkçı, Yahya Can Tu˘grul, Steve Rhyner, Meryem Banu Cavlak, Joël Lindegger, Mohammad Sadrosadati, and Onur Mutlu. RowPress: Amplifying Read Disturbance in Modern DRAM Chips. InISCA, 2023

    2023

  13. [13]

    RowPress Vulnerability in Modern DRAM Chips.IEEE Micro, 2024

    Haocong Luo, Ataberk Olgun, Abdullah Giray Ya˘glikçi, Yahya Can Tu˘grul, Steve Rhyner, Meryem Banu Cavlak, Joël Lindegger, Mohammad Sadrosadati, and Onur Mutlu. RowPress Vulnerability in Modern DRAM Chips.IEEE Micro, 2024

    2024

  14. [14]

    Giray Yaglikci

    Onur Mutlu, Ataberk Olgun, and A. Giray Yaglikci. Fundamentally Understanding and Solving RowHammer. InASP-DAC, 2023

    2023

  15. [15]

    An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips

    Haocong Luo, Ismail Emir Yüksel, Ataberk Olgun, A Giray Ya˘glıkçı, Mohammad Sadrosadati, and Onur Mutlu. An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips. InDSN Disrupt, 2024

    2024

  16. [16]

    Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies

    Haocong Luo, ˙Ismail Emir Yüksel, Ataberk Olgun, A Giray Ya ˘glıkçı, and Onur Mutlu. Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies. InVTS, 2025

    2025

  17. [17]

    Nisa Bostanci, Ismail Emir Yuksel, Oguzhan Canpolat, Haocong Luo, Geraldo F

    Ataberk Olgun, F. Nisa Bostanci, Ismail Emir Yuksel, Oguzhan Canpolat, Haocong Luo, Geraldo F. Oliveira, A. Giray Yaglikci, Minesh Patel, and Onur Mutlu. Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance. InHPCA, 2025

    2025

  18. [18]

    Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions

    Abdullah Giray Ya ˘glıkçı, Yahya Can Tu˘grul, Geraldo F Oliveira, ˙Ismail Emir Yüksel, Ataberk Olgun, Haocong Luo, and Onur Mutlu. Spatial Variation-Aware Read Disturbance Defenses: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions. InHPCA, 2024

    2024

  19. [19]

    Giray Ya ˘glıkçı, Yahya Can Tu˘grul, Haocong Luo, Steve Rhyner, Behzad Salami, Juan Gomez Luna, and Onur Mutlu

    Ataberk Olgun, Majd Osseiran, A. Giray Ya ˘glıkçı, Yahya Can Tu˘grul, Haocong Luo, Steve Rhyner, Behzad Salami, Juan Gomez Luna, and Onur Mutlu. Read Disturbance in High Bandwidth Memory: A Detailed Experimental Study on HBM2 DRAM Chips. InDSN, 2024

    2024

  20. [20]

    Blaster: Characterizing the blast radius of rowhammer

    Zhenrong Lang, Patrick Jattke, Michele Marazzi, and Kaveh Razavi. Blaster: Characterizing the blast radius of rowhammer. InDRAMSec, 2023

    2023

  21. [21]

    An Experimental Analysis of RowHammer in HBM2 DRAM Chips

    Ataberk Olgun, Majd Osseiran, Abdullah Giray Yaglikci, Yahya Can Tugrul, Hao- cong Luo, Steve Rhyner, Behzad Salami, Juan Gomez Luna, and Onur Mutlu. An Experimental Analysis of RowHammer in HBM2 DRAM Chips. InDSN Disrupt, 2023. 13

    2023

  22. [22]

    A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM

    Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, Onur Mutlu, Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, and Onur Mutlu. A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM. InISCA, 2012

    2012

  23. [23]

    Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture

    Donghyuk Lee et al. Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture. InHPCA, 2013

    2013

  24. [24]

    RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization

    Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarung- nirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Phillip B Gibbons, Michael A Kozuch, and Todd Mowry. RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization. InMICRO, 2013

    2013

  25. [25]

    Improving DRAM Performance by Parallelizing Refreshes with Accesses

    Kevin K Chang, Donghyuk Lee, Zeshan Chishti, Alaa R Alameldeen, Chris Wilker- son, Yoongu Kim, and Onur Mutlu. Improving DRAM Performance by Parallelizing Refreshes with Accesses. InHPCA, 2014

    2014

  26. [26]

    PARBOR: An Efficient System- Level Technique to Detect Data-Dependent Failures in DRAM

    Samira Khan, Donghyuk Lee, and Onur Mutlu. PARBOR: An Efficient System- Level Technique to Detect Data-Dependent Failures in DRAM. InDSN, 2016

    2016

  27. [27]

    RAIDR: Retention-Aware Intelligent DRAM Refresh

    Jamie Liu, Ben Jaiyen, Richard Veras, and Onur Mutlu. RAIDR: Retention-Aware Intelligent DRAM Refresh. InISCA, 2012

    2012

  28. [28]

    An Exper- imental Study of Data Retention Behavior in Modern DRAM Devices

    Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, and Onur Mutlu. An Exper- imental Study of Data Retention Behavior in Modern DRAM Devices. InISCA, 2013

    2013

  29. [29]

    The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study

    Samira Khan, Donghyuk Lee, Yoongu Kim, Alaa R Alameldeen, Chris Wilkerson, and Onur Mutlu. The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study. InSIGMETRICS, 2014

    2014

  30. [30]

    Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

    Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Khan, Vivek Seshadri, Kevin Chang, and Onur Mutlu. Adaptive-latency DRAM: Optimizing DRAM timing for the common-case. InHPCA, 2015

    2015

  31. [31]

    JEDEC.JESD79-3: DDR3 SDRAM Standard, 2012

    2012

  32. [32]

    JEDEC.JESD79-4C: DDR4 SDRAM Standard, 2020

    2020

  33. [33]

    JESD79-5C: DDR5 SDRAM Standard, 2024

    JEDEC. JESD79-5C: DDR5 SDRAM Standard, 2024

    2024

  34. [34]

    About the Security Content of Mac EFI Security Update 2015-001

    Apple Inc. About the Security Content of Mac EFI Security Update 2015-001. https://support.apple.com/en-us/HT204934, 2015. June 2015

    2015

  35. [35]

    HP Moonshot Component Pack Version 2015.05.0

    Hewlett-Packard Enterprise. HP Moonshot Component Pack Version 2015.05.0. http://h17007.www1.hp.com/us/en/enterprise/servers/products/moons hot/component-pack/index.aspx, 2015

    2015

  36. [36]

    Row Hammer Privilege Escalation

    Lenovo. Row Hammer Privilege Escalation. https://support.lenovo.com/us/ en/product_security/row_hammer, 2015

    2015

  37. [39]

    Architectural Support for Mitigating Row Hammering in DRAM Memories.CAL, 2014

    Dae-Hyun Kim, Prashant J Nair, and Moinuddin K Qureshi. Architectural Support for Mitigating Row Hammering in DRAM Memories.CAL, 2014

    2014

  38. [40]

    Bains and J.B

    K.S. Bains and J.B. Halbert. Distributed Row Hammer Tracking. US Patent App. 13/631,781, April 3 2014

    2014

  39. [41]

    Bains et al

    K.S. Bains et al. Method, Apparatus and System for Providing a Memory Refresh. US Patent: 9,030,903, 2015

    2015

  40. [42]

    Bains et al

    K.S. Bains et al. Row Hammer Refresh Command. US Patent App. 13/539,415, 2014

    2014

  41. [43]

    Bains et al

    K. Bains et al. Row Hammer Refresh Command. US Patent App. 14/068,677, 2014

    2014

  42. [44]

    ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks

    Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Rui Qiao, Reetuparna Das, Matthew Hicks, Yossi Oren, and Todd Austin. ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks. InASPLOS, 2016

    2016

  43. [45]

    Row Hammer Refresh Command, 2015

    Kuljit Bains, John Halbert, Christopher Mozak, Theodore Schoenborn, and Zvika Greenfield. Row Hammer Refresh Command, 2015. U.S. Patent 9,117,544

    2015

  44. [46]

    Row Hammer Monitoring Based on Stored Row Hammer Threshold Value

    Kuljit S Bains and John B Halbert. Row Hammer Monitoring Based on Stored Row Hammer Threshold Value. US Patent: 10,083,737, 2016. U.S. Patent 9,384,821

    2016

  45. [47]

    Counter-based Tree Structure for Row Hammering Mitigation in DRAM.IEEE CAL, 2017

    Seyed Mohammad Seyedzadeh, Alex K Jones, and Rami Melhem. Counter-based Tree Structure for Row Hammering Mitigation in DRAM.IEEE CAL, 2017

    2017

  46. [48]

    Distributed Row Hammer Tracking, 2016

    Kuljit S Bains and John B Halbert. Distributed Row Hammer Tracking, 2016. U.S. Patent 9,299,400

    2016

  47. [49]

    Throttling Support for Row-Hammer Counters,

    Zvika Greenfield and Tomer Levy. Throttling Support for Row-Hammer Counters,

  48. [50]

    Patent 9,251,885

    U.S. Patent 9,251,885

  49. [51]

    Making DRAM Stronger Against Row Hammering

    Mungyu Son, Hyunsun Park, Junwhan Ahn, and Sungjoo Yoo. Making DRAM Stronger Against Row Hammering. InDAC, 2017

    2017

  50. [52]

    S. M. Seyedzadeh, A. K. Jones, and R. Melhem. Mitigating Wordline Crosstalk Using Adaptive Trees of Counters. InISCA, 2018

    2018

  51. [53]

    MASCAT: Stopping Microar- chitectural Attacks Before Execution.IACR Cryptology, 2016

    Gorka Irazoqui, Thomas Eisenbarth, and Berk Sunar. MASCAT: Stopping Microar- chitectural Attacks Before Execution.IACR Cryptology, 2016

    2016

  52. [54]

    MRLoc: Mitigating Row-Hammering Based on Memory Locality

    Jung Min You and Joon-Sung Yang. MRLoc: Mitigating Row-Hammering Based on Memory Locality. InDAC, 2019

    2019

  53. [55]

    TWiCe: Preventing Row-Hammering by Exploiting Time Window Counters

    Eojin Lee, Ingab Kang, Sukhan Lee, G Edward Suh, and Jung Ho Ahn. TWiCe: Preventing Row-Hammering by Exploiting Time Window Counters. InISCA, 2019

    2019

  54. [56]

    Yeonhong Park, Woosuk Kwon, Eojin Lee, Tae Jun Ham, Jung Ho Ahn, and Jae W. Lee. Graphene: Strong yet Lightweight Row Hammer Protection. InMICRO, 2020

    2020

  55. [57]

    Security Analysis of the Silver Bullet Technique for RowHammer Prevention,

    A. Giray Ya˘glıkçı, Jeremie S. Kim, Fabrice Devaux, and Onur Mutlu. Security Anal- ysis of the Silver Bullet Technique for RowHammer Prevention. arXiv:2106.07084, 2021

    work page arXiv 2021

  56. [58]

    Giray Ya˘glikçi, Minesh Patel, Jeremie S

    A. Giray Ya˘glikçi, Minesh Patel, Jeremie S. Kim, Roknoddin Azizi, Ataberk Ol- gun, Lois Orosa, Hasan Hassan, Jisung Park, Konstantinos Kanellopoulos, Taha Shahroodi, Saugata Ghose, and Onur Mutlu. BlockHammer: Preventing RowHam- mer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows. InHPCA, 2021

    2021

  57. [59]

    CAT-TWO: Counter-Based Adaptive Tree, Time Window Optimized for DRAM Row-Hammer Prevention.IEEE Access, 2020

    Ingab Kang, Eojin Lee, and Jung Ho Ahn. CAT-TWO: Counter-Based Adaptive Tree, Time Window Optimized for DRAM Row-Hammer Prevention.IEEE Access, 2020

    2020

  58. [60]

    Hydra: Enabling Low-Overhead Mitigation of Row-Hammer at Ultra-Low Thresholds via Hybrid Tracking

    Moinuddin Qureshi, Aditya Rohan, Gururaj Saileshwar, and Prashant J Nair. Hydra: Enabling Low-Overhead Mitigation of Row-Hammer at Ultra-Low Thresholds via Hybrid Tracking. InISCA, 2022

    2022

  59. [61]

    Random- ized Row-Swap: Mitigating Row Hammer by Breaking Spatial Correlation Between Aggressor and Victim Rows

    Gururaj Saileshwar, Bolin Wang, Moinuddin Qureshi, and Prashant J Nair. Random- ized Row-Swap: Mitigating Row Hammer by Breaking Spatial Correlation Between Aggressor and Victim Rows. InASPLOS, 2022

    2022

  60. [62]

    Can’t Touch This: Software-Only Mitigation Against Rowhammer Attacks Targeting Kernel Memory

    Ferdinand Brasser, Lucas Davi, David Gens, Christopher Liebchen, and Ahmad- Reza Sadeghi. Can’t Touch This: Software-Only Mitigation Against Rowhammer Attacks Targeting Kernel Memory. InUSENIX Security, 2017

    2017

  61. [63]

    ZebRAM: Comprehensive and Compatible Software Protection Against Rowhammer Attacks

    Radhesh Krishnan Konoth, Marco Oliverio, Andrei Tatar, Dennis Andriesse, Her- bert Bos, Cristiano Giuffrida, and Kaveh Razavi. ZebRAM: Comprehensive and Compatible Software Protection Against Rowhammer Attacks. InOSDI, 2018

    2018

  62. [64]

    GuardION: Practical Mitigation of DMA-Based Rowhammer Attacks on ARM

    Victor van der Veen, Martina Lindorfer, Yanick Fratantonio, Harikrishnan Padman- abha Pillai, Giovanni Vigna, Christopher Kruegel, Herbert Bos, and Kaveh Razavi. GuardION: Practical Mitigation of DMA-Based Rowhammer Attacks on ARM. In DIMVA, 2018

    2018

  63. [65]

    Rapid Detection of Rowhammer Attacks Using Dynamic Skewed Hash Tree

    Saru Vig, Sarani Bhattacharya, Debdeep Mukhopadhyay, and Siew-Kei Lam. Rapid Detection of Rowhammer Attacks Using Dynamic Skewed Hash Tree. InHASP, 2018

    2018

  64. [66]

    Lee, and Jung Ho Ahn

    Michael Jaemin Kim, Jaehyun Park, Yeonhong Park, Wanju Doh, Namhoon Kim, Tae Jun Ham, Jae W. Lee, and Jung Ho Ahn. Mithril: Cooperative Row Hammer Protection on Commodity DRAM Leveraging Managed Refresh. InHPCA, 2022

    2022

  65. [67]

    CryoGuard: A Near Refresh-Free Robust DRAM Design for Cryogenic Computing

    Gyu-Hyeon Lee, Seongmin Na, Ilkwon Byun, Dongmoon Min, and Jangwoo Kim. CryoGuard: A Near Refresh-Free Robust DRAM Design for Cryogenic Computing. InISCA, 2021

    2021

  66. [68]

    ProTRR: Princi- pled yet Optimal In-DRAM Target Row Refresh

    Michele Marazzi, Patrick Jattke, Flavien Solt, and Kaveh Razavi. ProTRR: Princi- pled yet Optimal In-DRAM Target Row Refresh. InS&P, 2022

    2022

  67. [69]

    SoftTRR: Protect Page Tables against Rowhammer Attacks using Software-only Target Row Refresh

    Zhi Zhang, Yueqiang Cheng, Minghua Wang, Wei He, Wenhao Wang, Surya Nepal, Yansong Gao, Kang Li, Zhe Wang, and Chenggang Wu. SoftTRR: Protect Page Tables against Rowhammer Attacks using Software-only Target Row Refresh. In USENIX ATC, 2022

    2022

  68. [70]

    Learning to Mitigate RowHammer Attacks

    Biresh Kumar Joardar, Tyler K Bletsch, and Krishnendu Chakrabarty. Learning to Mitigate RowHammer Attacks. InDATE, 2022

    2022

  69. [71]

    CSI: Rowhammer–Cryptographic Security and Integrity against Rowhammer

    Jonas Juffinger, Lukas Lamster, Andreas Kogler, Maria Eichlseder, Moritz Lipp, and Daniel Gruss. CSI: Rowhammer–Cryptographic Security and Integrity against Rowhammer. InS&P, 2023

    2023

  70. [72]

    HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips

    A Giray Ya˘glikci, Ataberk Olgun, Minesh Patel, Haocong Luo, Hasan Hassan, Lois Orosa, O˘guz Ergin, and Onur Mutlu. HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips. InMICRO, 2022

    2022

  71. [73]

    Nair, and Moinuddin Qureshi

    Anish Saxena, Gururaj Saileshwar, Prashant J. Nair, and Moinuddin Qureshi. AQUA: Scalable Rowhammer Mitigation by Quarantining Aggressor Rows at Runtime. In MICRO, 2022

    2022

  72. [74]

    Efficient Protection Mecha- nism for CPU Cache Flush Instruction Based Attacks.IEICE TIS, 2022

    Shuhei Enomoto, Hiroki Kuzuno, and Hiroshi Yamada. Efficient Protection Mecha- nism for CPU Cache Flush Instruction Based Attacks.IEICE TIS, 2022

    2022

  73. [75]

    Revisiting Residue Codes for Modern Memories

    Evgeny Manzhosov, Adam Hastings, Meghna Pancholi, Ryan Piersma, Mohamed Tarek Ibn Ziad, and Simha Sethumadhavan. Revisiting Residue Codes for Modern Memories. InMICRO, 2022

    2022

  74. [76]

    EV AX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security

    Samira Mirbagher Ajorpaz, Daniel Moghimi, Jeffrey Neal Collins, Gilles Pokam, Nael Abu-Ghazaleh, and Dean Tullsen. EV AX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security. InMICRO, 2022

    2022

  75. [77]

    ALARM: Active LeArning of Rowhammer Mitigations

    Amir Naseredini, Martin Berger, Matteo Sammartino, and Shale Xiong. ALARM: Active LeArning of Rowhammer Mitigations. https://users.sussex.ac.uk/~m fb21/rh-draft.pdf, 2022

    2022

  76. [78]

    Bletsch, and Krishnendu Chakrabarty

    Biresh Kumar Joardar, Tyler K. Bletsch, and Krishnendu Chakrabarty. Machine Learning-based Rowhammer Mitigation.TCAD, 2022

    2022

  77. [79]

    Extracting the Secrets of OpenSSL with RAMBleed

    Chihiro Tomita, Makoto Takita, Kazuhide Fukushima, Yuto Nakano, Yoshiaki Shiraishi, and Masakatu Morii. Extracting the Secrets of OpenSSL with RAMBleed. Sensors, 2022

    2022

  78. [80]

    Leveraging EM Side-Channel Information to Detect Rowham- mer Attacks

    Zhenkai Zhang, Zihao Zhan, Daniel Balasubramanian, Bo Li, Peter V olgyesi, and Xenofon Koutsoukos. Leveraging EM Side-Channel Information to Detect Rowham- mer Attacks. InS&P, 2020

    2020

  79. [81]

    Stop! Hammer Time: Rethinking Our Approach to Rowhammer Mitigations

    Kevin Loughlin, Stefan Saroiu, Alec Wolman, and Baris Kasikci. Stop! Hammer Time: Rethinking Our Approach to Rowhammer Mitigations. InHotOS, 2021

    2021

  80. [82]

    Method and Circuit for Protecting a DRAM Memory Device from the Row Hammer Effect

    Fabrice Devaux and Renaud Ayrignac. Method and Circuit for Protecting a DRAM Memory Device from the Row Hammer Effect. US Patent: 10,885,966, 2021. 10,885,966

    2021

Showing first 80 references.