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REVIEW 2 major objections 2 minor 17 references

A hierarchical logical processor concatenates a high-rate code with the rotated surface code and uses shuttle buses to reach three to four times higher qubit efficiency at physical error rate 10^{-3}.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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T0 review · grok-4.3

2026-06-26 10:03 UTC pith:MRLRORHC

load-bearing objection The HLP construction with shuttle buses gives a workable way to layer high-rate codes on surface codes and cut non-local gate frequency, but the claimed efficiency gains rest on standard noise simulations that may miss real hardware errors. the 2 major comments →

arxiv 2606.22594 v1 pith:MRLRORHC submitted 2026-06-21 quant-ph

Hierarchical Logical Processor on the Rotated Surface Code with Shuttle Buses

Zi-Han Chen , Ming-Cheng Chen , Chao-Yang Lu , Jian-Wei Pan This is my paper
classification quant-ph
keywords hierarchical logical processorrotated surface codeshuttle busesfault-tolerant quantum computationquantum error correctiontransversal gateshigh-rate CSS codes
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper proposes the hierarchical logical processor by stacking a high-rate CSS code atop rotated surface code patches connected by shuttle buses. This arrangement requires long-range couplings only once every Theta of the base distance rounds of level-zero correction. Circuit-level simulations at physical error rate 10^{-3} show the construction reaches three to four times the qubit efficiency of a plain rotated surface code. It also trims space per logical qubit by one hundred to two hundred physical qubits and shortens the full correction cycle by a factor of twenty to thirty compared with the yoked surface code.

Core claim

The hierarchical logical processor concatenates a high-rate quantum CSS code with the rotated surface code and introduces elongated shuttle bus patches. These buses enable simultaneous coupling to multiple patches through transversal hybrid-unit CNOT gates, allowing level-1 syndrome extraction with reduced error correlations and parallel logical measurements while limiting non-local operations to infrequent intervals.

What carries the argument

The shuttle bus, an elongated rotated surface code patch that couples simultaneously to multiple standard patches via transversal hybrid-unit CNOT gates.

Load-bearing premise

The circuit-level noise model and error correlations assumed for shuttle bus operations and transversal hybrid-unit CNOT gates match real hardware behavior.

What would settle it

Running the HLP circuits on hardware with beyond-planar connectivity and checking whether measured logical error rates and overhead reductions match the simulated values without extra unmodeled errors.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

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If this is right

  • At physical error rate 10^{-3} an HLP based on the [[256,194,4]] code reaches 3-4 times higher qubit efficiency than the standard rotated surface code.
  • Space overhead per logical qubit falls by 100-200 physical qubits relative to the yoked surface code on the same level-1 code.
  • The logical error-correction cycle shortens by a factor of 20-30.
  • Level-1 syndrome extraction occurs with suppressed error correlations and supports highly parallel logical Pauli measurements.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The reduced frequency of long-range operations could make fault tolerance feasible on hardware where such couplings remain expensive or noisy.
  • The same layering pattern might improve encoding efficiency for other high-rate codes placed atop different base patches.
  • Shorter cycles could accelerate algorithms that interleave many logical measurements with computation.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 2 minor

Summary. The paper proposes the Hierarchical Logical Processor (HLP), which concatenates a high-rate quantum CSS code with the rotated surface code (RSC) via elongated 'shuttle bus' patches and transversal hybrid-unit CNOT gates. This construction requires long-range couplings only every Θ(d₀) rounds. Circuit-level Monte Carlo simulations are presented for several HLP instances; the headline result is that at physical error rate p=10^{-3} the [[256,194,4]] HLP yields 3-4× higher qubit efficiency than plain RSC, 100-200 fewer physical qubits per logical qubit than the yoked surface code, and a 20-30× shorter logical cycle time.

Significance. If the reported simulation advantages survive more realistic noise models, the HLP offers a concrete route to higher-rate logical qubits while keeping non-local interactions infrequent. The approach is a hybrid between surface-code locality and qLDPC efficiency and supplies concrete numerical benchmarks for both memory and Pauli-measurement performance.

major comments (2)
  1. [simulation-results section / abstract] Abstract and simulation-results section: the quantitative claims (3-4× efficiency, 100-200 qubit saving, 20-30× cycle-time reduction) rest entirely on circuit-level Monte Carlo data for shuttle-bus and hybrid-unit CNOT operations. The manuscript states a standard depolarizing model but does not specify the precise correlation assumptions, shuttle-induced decoherence channels, or crosstalk terms; any additional long-range error source omitted from the model would directly raise the level-1 logical error rate and erase the reported advantage over both RSC and yoked surface code.
  2. [construction / level-1 syndrome extraction] Construction section: the claim that long-range couplings occur only every Θ(d₀) rounds is load-bearing for the connectivity advantage. The paper must show explicitly how the level-1 syndrome-extraction circuit is scheduled so that shuttle-bus usage remains at this reduced frequency while still suppressing level-1 error correlations; without the explicit circuit diagram or round count, the Θ(d₀) statement cannot be verified.
minor comments (2)
  1. Notation: the symbols d₀ and [[n,k,d]] are used before being defined; a short definitions paragraph at the start of the methods would improve readability.
  2. Figure captions: several simulation plots lack error-bar descriptions or the exact number of Monte Carlo shots used to obtain the reported logical error rates.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive and detailed feedback. We address the two major comments point by point below and will revise the manuscript to improve clarity on the noise model and circuit scheduling.

read point-by-point responses

  1. Referee: [simulation-results section / abstract] Abstract and simulation-results section: the quantitative claims (3-4× efficiency, 100-200 qubit saving, 20-30× cycle-time reduction) rest entirely on circuit-level Monte Carlo data for shuttle-bus and hybrid-unit CNOT operations. The manuscript states a standard depolarizing model but does not specify the precise correlation assumptions, shuttle-induced decoherence channels, or crosstalk terms; any additional long-range error source omitted from the model would directly raise the level-1 logical error rate and erase the reported advantage over both RSC and yoked surface code.

    Authors: We agree that the noise model requires more explicit documentation. The simulations use a standard circuit-level depolarizing model in which every two-qubit gate, measurement, and reset is followed by an independent depolarizing channel of strength p (with single-qubit operations at p/10), and no additional correlations or crosstalk are introduced beyond those generated by the circuit itself. Shuttle-bus and hybrid-unit CNOT operations are subject to the same per-operation error rates. The reported advantages are therefore conditional on this model; unmodeled long-range errors would indeed affect the results. In revision we will add a dedicated paragraph in the simulation section that states the exact channel definitions, correlation assumptions, and any shuttle-specific decoherence terms. revision: yes

  2. Referee: [construction / level-1 syndrome extraction] Construction section: the claim that long-range couplings occur only every Θ(d₀) rounds is load-bearing for the connectivity advantage. The paper must show explicitly how the level-1 syndrome-extraction circuit is scheduled so that shuttle-bus usage remains at this reduced frequency while still suppressing level-1 error correlations; without the explicit circuit diagram or round count, the Θ(d₀) statement cannot be verified.

    Authors: The construction relies on running d₀ rounds of level-0 error correction on each base RSC patch before invoking the shuttle bus for a level-1 syndrome extraction; the high-rate outer code distance permits this reduced frequency while the base-code distance suppresses intra-block correlations. We acknowledge that an explicit schedule would make the claim easier to verify. In the revised manuscript we will insert a timing diagram (or table) in the construction section that lists the number of rounds between shuttle-bus activations and confirms the Θ(d₀) interval. revision: yes

Circularity Check

0 steps flagged

No significant circularity; claims rest on independent circuit-level simulations

full rationale

The paper's central performance claims (3-4× qubit efficiency, reduced space overhead, and shortened cycle times for the [[256,194,4]] HLP at p=10^{-3}) are obtained directly from explicit circuit-level Monte Carlo simulations of shuttle-bus operations and transversal hybrid-unit CNOT gates under a depolarizing noise model. These numerical benchmarks constitute external evidence relative to the construction; no step reduces by definition, by fitted-parameter renaming, or by self-citation chain to the reported metrics themselves. The derivation chain is therefore self-contained against the simulation results.

Axiom & Free-Parameter Ledger

1 free parameters · 2 axioms · 2 invented entities

The proposal rests on standard quantum error correction assumptions and introduces new architectural components whose performance is asserted via simulation.

free parameters (1)
  • [[256,194,4]] code
    Specific high-rate CSS code selected for the concrete HLP example; parameters are given but selection criteria not detailed in abstract.
axioms (2)
  • domain assumption Circuit-level depolarizing noise model applies to all operations including shuttle bus couplings
    Underlying assumption for all reported simulation results.
  • domain assumption Transversal hybrid-unit CNOT gates can be implemented without introducing additional error correlations beyond the model
    Required for the level-1 syndrome extraction claims.
invented entities (2)
  • Shuttle bus no independent evidence
    purpose: Elongated RSC patch enabling simultaneous coupling to multiple standard patches via transversal gates
    New structural element introduced to support the hierarchical architecture.
  • Hierarchical Logical Processor (HLP) no independent evidence
    purpose: Concatenated code structure reducing frequency of non-local couplings
    Core proposed processor design.

pith-pipeline@v0.9.1-grok · 5833 in / 1354 out tokens · 26212 ms · 2026-06-26T10:03:35.631433+00:00 · methodology

0 comments
Cite this review

Pith. "Pith review of Hierarchical Logical Processor on the Rotated Surface Code with Shuttle Buses." pith.science (2026). https://pith.science/paper/MRLRORHC

@misc{pith2026260622594,
  author       = {Pith},
  title        = {Pith review of: Hierarchical Logical Processor on the Rotated Surface Code with Shuttle Buses},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/MRLRORHC}},
  note         = {Machine review of arXiv:2606.22594}
}
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read the original abstract

Quantum platforms with beyond-planar connectivity provide new opportunities for fault-tolerant quantum computation (FTQC). While quantum low-density parity-check (qLDPC) codes offer high encoding efficiency, their direct implementation requires non-local couplings in every round of syndrome extraction, incurring additional physical error and implementation complexity. To reduce the frequency of such couplings, we propose the Hierarchical Logical Processor (HLP), which concatenates a high-rate quantum CSS code with the rotated surface code (RSC). HLPs can achieve beyond-RSC encoding efficiency while requiring long-range connectivity only once every $\Theta(d_0)$ rounds of level-0 error correction, where $d_0$ denotes the base-code distance, substantially reducing the frequency of non-local couplings relative to direct implementations of qLDPC codes. HLPs introduce elongated RSC patches called shuttle buses. Using transversal hybrid-unit CNOT gates, a single shuttle bus can simultaneously couple to multiple standard RSC patches. This capability enables efficient level-1 syndrome extraction with suppressed level-1 error correlations and supports highly parallel logical Pauli measurements. We perform circuit-level simulations of several concrete HLP constructions and benchmark both logical memory and logical Pauli measurement performance. At a physical error rate of $10^{-3}$, an HLP based on the [[256,194,4]] code achieves 3-4 times higher qubit efficiency than the standard RSC. Compared with the yoked surface code on the same level-1 code, this HLP reduces the space overhead per logical qubit by 100-200 physical qubits and shortens the logical error-correction cycle time by a factor of 20-30.

Figures

Figures reproduced from arXiv: 2606.22594 by Chao-Yang Lu, Jian-Wei Pan, Ming-Cheng Chen, Zi-Han Chen.

Figure 1
Figure 1. Figure 1: FIG. 1. Architecture of a hierarchical logical processor. ( [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. Benchmarking the memory performance of various [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Logical Pauli measurements on a hierarchical logical [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Cores and shuttle buses. ( [PITH_FULL_IMAGE:figures/full_fig_p009_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. Level-1 [PITH_FULL_IMAGE:figures/full_fig_p013_5.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7 [PITH_FULL_IMAGE:figures/full_fig_p014_7.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. Postdecoding weight for an edge [PITH_FULL_IMAGE:figures/full_fig_p014_6.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. Space-time stabilizers and a CNOT membrane. ( [PITH_FULL_IMAGE:figures/full_fig_p016_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9. Two examples of lightning cycles and their canonical [PITH_FULL_IMAGE:figures/full_fig_p017_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10. Cleaning a cross-membrane walk [PITH_FULL_IMAGE:figures/full_fig_p018_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: FIG. 11. Bus-core CNOT gates during an [PITH_FULL_IMAGE:figures/full_fig_p027_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: FIG. 12. Mid-cycle transversal [PITH_FULL_IMAGE:figures/full_fig_p028_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: FIG. 13. Scheduling of a hybrid architecture consisting of hi [PITH_FULL_IMAGE:figures/full_fig_p032_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: FIG. 14. Level-1 SE circuit for the [PITH_FULL_IMAGE:figures/full_fig_p033_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: FIG. 15. Scheduling of three [PITH_FULL_IMAGE:figures/full_fig_p033_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: FIG. 16. Soft-output reference and its validation. ( [PITH_FULL_IMAGE:figures/full_fig_p034_16.png] view at source ↗
Figure 18
Figure 18. Figure 18: FIG. 18. Correlation between [PITH_FULL_IMAGE:figures/full_fig_p035_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: FIG. 19. Calibration of soft-output simulation. See also [PITH_FULL_IMAGE:figures/full_fig_p035_19.png] view at source ↗
Figure 20
Figure 20. Figure 20: FIG. 20. Extrapolation of logical error rates per level-0 SE round for the rotated surface code (RSC) and hierarchical logical [PITH_FULL_IMAGE:figures/full_fig_p036_20.png] view at source ↗

discussion (0)

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Reference graph

Works this paper leans on

17 extracted references

  1. [1]

    For each subconfigurationg⊂f X ∪f Z,S f(g) =S e∈g Sf(e)with eachea primitive level-0 error in g

  2. [2]

    Similarly, for each primitive errore Z ∈f Z, PZ ◦S f(eZ) =e Z

    For each primitive erroreX ∈f X,P X ◦S f(eX) = eX. Similarly, for each primitive errore Z ∈f Z, PZ ◦S f(eZ) =e Z

  3. [3]

    For everygX ⊂ fX,κ,S f(gX)⊂f κ

    For everygX ⊂f X,ϵ,S f(gX)⊂f ϵ. For everygX ⊂ fX,κ,S f(gX)⊂f κ

  4. [4]

    For everyg Z ⊂ fZ,κ,S f(gZ)⊂f κ

    For everygZ ⊂f Z,ϵ,S f(gZ)⊂f ϵ. For everyg Z ⊂ fZ,κ,S f(gZ)⊂f κ. By construction, we know that given a subconfiguration g⊂f X ∪f Z,|S f(g)∩ϵ| ≥max(|g X ∩ϵ X |,|g Z ∩ϵ Z|). Additionally, ifgforms a connected cluster on the level- 0 adjacency graph, thenS f(g)also forms a connected cluster. Building on Lemma 12, we can bound a general level-0 residual error...

  5. [5]

    For each general residual level-0 error configuration f(composed of two components, physical errorsfϵ and decoded errorsfκ, respectively) that induces a level-1 error configuration containingg, there exists 24 µ∈ F g withµ⊂fsuch that the weight of the intersectionofµandthephysicalerrorsinfislower bounded by bothd0|g|/2and|µ|/C 1, whereC1 >1 is a constant ...

  6. [6]

    Every error configuration inF g has a weight at leastd0|g|/2

    The number of error configurations inFg with a weightwis upper bounded byC 2 ·C w 3 , where both C2 >0andC 3 >1are constants. Every error configuration inF g has a weight at leastd0|g|/2. Moreover, suppose physical level-0 errors are local stochastic, such that the event of physical errors con- taining a general level-0 error configurationϵmay oc- cur wit...

  7. [7]

    Then, we can simply upper bound the size of any receptive zone byzmax

    Thesizeofthereceptive zone of a primitive level-1 bus error is upper bounded by 4τbd2 0d1 +τ bd2 0 ≤8τ bd2 0d1. Then, we can simply upper bound the size of any receptive zone byzmax. Denote the number of weight-wconfigurations inF g asC g(w). Ac- cording to Lemma 15,C g(w)≤(z max/r)|g|(re)w. Com- bining this bound with Lemma 13, we can see thatFg is a key...

  8. [8]

    Initialize the level-1 ancilla in theZbasis

  9. [9]

    Every level-1 layer has at mostd1 control qubits

    Perform a sequence of CNOT gates between level-1 data qubits (controls) and the level-1 ancilla qubit (target), such that for every level-1 data qubiti withz i = 1, exactly one CNOT gate is applied between that qubit and the ancilla. Every level-1 layer has at mostd1 control qubits

  10. [10]

    Perform a level-1Hgate on the ancilla

  11. [11]

    Every level-1 layer has at mostd 1 target qubits

    Perform a sequence of CNOT gates between the level-1ancilla(control)andlevel-1dataqubits(tar- gets), such that for every level-1 data qubitiwith xi = 1, exactly one CNOT gate is applied between that qubit and the ancilla. Every level-1 layer has at mostd 1 target qubits

  12. [12]

    We now describe the level-0 implementation of anH- transformed readout gadget

    Measure the level-1 ancilla in theXbasis. We now describe the level-0 implementation of anH- transformed readout gadget. The level-1 ancilla of the gadget is implemented by a shuttle bus, referred to as anHbus. In the first step, theHbus is transversally initialized in theZbasis as aZbus. Then, the sequence of level-1 CNOT gates between level-1 data qubit...

  13. [13]

    Perform a level-1Sgate on the ancilla

  14. [14]

    The level-0 implementation of anHS-transformed read- out gadget mostly follows from that of anH-transformed readout gadget

    Measure the ancilla inXbasis. The level-0 implementation of anHS-transformed read- out gadget mostly follows from that of anH-transformed readout gadget. The only new step for the former is to perform a logicalSgate on theHbus. Following the approach in Ref. [41], we can perform a mid-cycle fold-transversalSgate by leveraging the dynamics of the level-0 S...

  15. [15]

    whereaandbare non-negative fitting parameters

    Additionally, we simulate the HLP based on the[[4,2,2]] Iceberg code at the circuit level withαb = 0.5. whereaandbare non-negative fitting parameters. We find thata= 0.65andb= 1provides a close fit for both logicalXandZerrorrates(Fig.17(a)). Wecomparethis fitted ansatz with data pairs consisting ofX-basis soft outputs and logicalZerror rates on a core for...

  16. [16]

    The HLP is run as a memory for ten level-1 SE rounds

    An HLP with the[[4,2,2]]Iceberg code as the level- 1 code. The HLP is run as a memory for ten level-1 SE rounds

  17. [17]

    We simulate only five level-1 SE rounds on the HLP, since circuit-level simulation is costly at this scale

    An HLP with the[[64,34,4]]Square Berg code as the level-1 code. We simulate only five level-1 SE rounds on the HLP, since circuit-level simulation is costly at this scale. As shown in Fig. 19, the soft-output simulations using the fitted level-1 error rate ansatzLER 0.65,1 produce results close to those obtained from circuit-level simu- lations. However, ...