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arxiv: 2606.28585 · v1 · pith:RG7LVLLGnew · submitted 2026-06-26 · ❄️ cond-mat.mes-hall

Voltage-tunable Josephson Junctions on Germanium Quantum Wells with in-situ Aluminum Contacts

Joshua P. Thompson , Jason T. Dong , Bernardo Langa Jr , Chomani K. Gaspe , Riss Card , Brycelynn Bailey , Shiva Davari , Bethany E. Matthews
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Matthew J. Olszta Silas Hoffman Thomas M. Hazard Kyle Serniak Hugh O.H. Churchill Kasra Sardashti Christopher J.K. Richardson
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Pith reviewed 2026-06-30 01:07 UTC · model grok-4.3

classification ❄️ cond-mat.mes-hall
keywords voltage-tunable Josephson junctionsgermanium quantum wellsin-situ aluminum contactsdeep mesa etchgate-tunable supercurrentssuperconducting quantum electronicsmolecular beam epitaxyoxide-free interfaces
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The pith

Voltage-tunable Josephson junctions on germanium quantum wells with in-situ aluminum contacts achieve gate-tunable supercurrents above 100 nA.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper establishes a fabrication route for voltage-tunable Josephson junctions using molecular beam epitaxy grown germanium quantum wells and in-situ aluminum contacts that form oxide-free interfaces. A deep mesa etch removes surrounding epitaxial material so that the junctions sit on a float-zone silicon substrate while allowing metal lines to run up tapered sidewalls for gates and interconnects. Devices fabricated this way exhibit gate control of supercurrent with a peak critical current exceeding 100 nA and an IcRn product of 8.63 microvolts. The approach is presented as compatible with wafer-scale processing and as a way to place these tunable elements alongside other superconducting circuit components on low-loss substrates. A reader would care because the work directly addresses the microwave-loss barrier that has limited integration of semiconductor-based tunable junctions into quantum circuits.

Core claim

The fabricated Josephson junctions demonstrate gate-tunable supercurrents with a maximum critical current over 100 nA and critical-current normal-resistance product of 8.63 μV. These results demonstrate a pathway toward improved integration of voltage-tunable superconducting circuit elements with quantum electronic building blocks such as couplers and qubits.

What carries the argument

The deep mesa etch process that produces a sidewall taper sufficient for continuous metal deposition from the substrate to the top of the mesa, enabling electrostatic gate electrodes and interconnects while leaving the VT-JJ device on the low-loss substrate.

If this is right

  • VT-JJs can be placed directly on a low-loss silicon substrate rather than on lossy epitaxial material.
  • The same wafer-scale process supports placement of couplers and qubits alongside the tunable junctions.
  • Oxide-free superconductor-semiconductor interfaces formed by in-situ aluminum allow supercurrent flow that remains gate-tunable.
  • The approach remains compatible with conventional semiconductor processing steps.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same mesa-and-taper technique could be applied to other semiconductor platforms that currently suffer from substrate loss when hosting tunable junctions.
  • Direct measurement of resonator quality factors in circuits that include these VT-JJs would quantify the actual microwave-loss reduction.
  • Voltage control of junction critical current could be used to implement tunable couplers without additional flux lines.

Load-bearing premise

The deep mesa etch produces a sidewall taper sufficient for continuous metal deposition from the substrate to the top of the mesa without introducing defects that degrade device performance or add microwave loss.

What would settle it

Fabrication of an integrated circuit containing both a VT-JJ and a low-loss superconducting element on the same substrate followed by measurement of microwave loss or loss of gate tunability would falsify the integration pathway.

Figures

Figures reproduced from arXiv: 2606.28585 by Bernardo Langa Jr, Bethany E. Matthews, Brycelynn Bailey, Chomani K. Gaspe, Christopher J.K. Richardson, Hugh O.H. Churchill, Jason T. Dong, Joshua P. Thompson, Kasra Sardashti, Kyle Serniak, Matthew J. Olszta, Riss Card, Shiva Davari, Silas Hoffman, Thomas M. Hazard.

Figure 1
Figure 1. Figure 1: FIG. 1. a) Al/Ge QW heterostructure schematic. b) Magnetotransport for a Hall bar with hole density, [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. a) Representative false colored SEM micrograph of a JJ, the gate electrode can be observed climbing the mesa to [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. a) Current-voltage curves measured at 10 mK from a Josephson junction demonstrating gate-tunable superconductivity. [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
read the original abstract

Voltage-tunable Josephson junctions (VT-JJs) are an emerging element in superconducting quantum electronics with potential to expand the functionality of conventional designs. While VT-JJs are largely compatible with wafer-scale semiconductor processing, their integration into quantum circuits remains a challenge due to unmitigated semiconductor microwave loss. Here, a deep mesa etch process, wherein the epitaxial material is removed except the VT-JJ device, will facilitate the integration of VT-JJs with low-microwave-loss circuit elements by allowing these circuit elements to be placed directly on a low-loss substrate. A Germanium quantum well is grown by Molecular Beam Epitaxy (MBE) on a float zone silicon substrate with in-situ deposited aluminum contacts. This combination allows the formation of an oxide-free superconductor-semiconductor interface. The deep mesa etch process is optimized to produce a sidewall taper sufficient for continuous metal deposition from the substrate to the top of the mesa for electrostatic gate electrodes and interconnects. The fabricated Josephson junctions demonstrate gate-tunable supercurrents with a maximum critical current over 100 nA and critical-current normal-resistance product of $8.63~\mu V$. These results demonstrate a pathway toward improved integration of voltage-tunable superconducting circuit elements with quantum electronic building blocks such as couplers and qubits.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

3 major / 1 minor

Summary. The manuscript describes the fabrication of voltage-tunable Josephson junctions on a Ge quantum well grown by MBE on float-zone Si, using in-situ Al contacts to form an oxide-free interface. A deep mesa etch isolates the devices and is optimized to produce a sidewall taper enabling continuous metal deposition for gates and interconnects directly on the low-loss substrate. Fabricated devices show gate-tunable supercurrents with maximum Ic exceeding 100 nA and IcRn product of 8.63 μV, presented as a pathway toward integration of VT-JJs with couplers and qubits.

Significance. If the reported Ic and IcRn values prove reproducible with proper statistics and the mesa etch is shown to support continuous interconnects without added defects or microwave loss, the work would offer a concrete route for hybrid integration of tunable semiconductor JJs with low-loss superconducting circuits on a common platform. The in-situ Al/Ge interface approach addresses a common source of interface disorder in such systems.

major comments (3)
  1. [Abstract] Abstract: the performance metrics (maximum Ic > 100 nA and IcRn = 8.63 μV) are presented without any measurement protocol, number of devices, statistics, or error analysis, so the central device-performance claim cannot be evaluated.
  2. [Abstract] Abstract / deep-mesa-etch description: the claim that the optimized sidewall taper enables continuous metal deposition from substrate to mesa top without introducing defects or microwave loss is load-bearing for the integration-pathway conclusion, yet no cross-sectional imaging, interconnect resistance data, or microwave characterization of co-fabricated elements is referenced.
  3. [Abstract] Integration-pathway statement: the assertion that the etch facilitates placement of low-microwave-loss circuit elements directly on the substrate rests on an unverified assumption; without supporting data the pathway claim does not follow from the reported JJ metrics alone.
minor comments (1)
  1. [Abstract] The numerical value 8.63 μV should be accompanied by the gate-voltage condition or a note on whether it represents a maximum.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for their careful reading and constructive comments on the manuscript. We address each major comment point by point below and agree that revisions to the abstract are warranted to strengthen the presentation of the results.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the performance metrics (maximum Ic > 100 nA and IcRn = 8.63 μV) are presented without any measurement protocol, number of devices, statistics, or error analysis, so the central device-performance claim cannot be evaluated.

    Authors: We agree that the abstract, as a concise summary, omits key details on the measurement protocol and device statistics that are provided in the main text and figures. The reported Ic and IcRn values represent the highest observed across the fabricated devices, with supporting data from multiple junctions shown in the results section. We will revise the abstract to include a brief statement on the number of devices measured and the range of observed values. revision: yes

  2. Referee: [Abstract] Abstract / deep-mesa-etch description: the claim that the optimized sidewall taper enables continuous metal deposition from substrate to mesa top without introducing defects or microwave loss is load-bearing for the integration-pathway conclusion, yet no cross-sectional imaging, interconnect resistance data, or microwave characterization of co-fabricated elements is referenced.

    Authors: The main manuscript includes SEM imaging of the optimized sidewall taper and electrical characterization confirming continuous interconnects. We will revise the abstract to explicitly reference these supporting results from the body of the paper, making clear that the taper enables continuous deposition as verified by imaging and transport measurements. revision: yes

  3. Referee: [Abstract] Integration-pathway statement: the assertion that the etch facilitates placement of low-microwave-loss circuit elements directly on the substrate rests on an unverified assumption; without supporting data the pathway claim does not follow from the reported JJ metrics alone.

    Authors: The integration pathway is presented as a prospective route enabled by the demonstrated deep mesa etch and JJ performance, rather than a fully characterized integration. The etch process is shown to allow direct substrate placement, which is the key enabling step. We will revise the abstract wording to clarify that this constitutes a proposed pathway supported by the etch optimization and JJ results, without overstating the current demonstration. revision: yes

Circularity Check

0 steps flagged

No circularity: experimental fabrication report with direct device metrics

full rationale

The paper is a purely experimental fabrication and characterization report. It presents measured Ic > 100 nA and IcRn = 8.63 μV from fabricated Ge quantum-well Josephson junctions, plus an optimized deep mesa etch process. No derivations, equations, fitted parameters renamed as predictions, or self-citation chains appear in the provided text. The integration-pathway statement is a forward-looking claim resting on the reported device performance and etch optimization, not on any reduction to prior inputs by construction. This matches the default expectation of a self-contained experimental paper (score 0-2).

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Relies on standard domain assumptions from MBE epitaxy and semiconductor processing; no free parameters, invented entities, or ad-hoc axioms beyond the reported experimental outcomes.

axioms (1)
  • domain assumption In-situ aluminum deposition on the germanium quantum well produces an oxide-free superconductor-semiconductor interface suitable for Josephson junction formation.
    Invoked directly in the abstract description of the material stack.

pith-pipeline@v0.9.1-grok · 5829 in / 1209 out tokens · 52729 ms · 2026-06-30T01:07:05.489361+00:00 · methodology

discussion (0)

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