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REVIEW 3 major objections 4 minor 67 references

A simple binomial fault model estimates logical error rates across quantum codes and hardware and finds when distributing error correction pays off.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

T0 review · grok-4.5

2026-07-11 21:48 UTC pith:PNTDUUYZ

load-bearing objection A clean, usable binomial-tail screen for modern QEC codes and distributed sweet spots; absolute numbers rest on an unvalidated malignancy fraction, but the qualitative tool is solid and worth engaging. the 3 major comments →

arxiv 2607.04082 v1 pith:PNTDUUYZ submitted 2026-07-05 quant-ph cs.ET

A Cross-Platform Analysis of High-Performance Quantum Error Correction Codes

classification quant-ph cs.ET
keywords quantum error correctionlogical error ratebinomial fault modeldistributed quantum computingsurface codeqLDPC codesbiased noisecircuit volume
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Physical qubits remain too few and too noisy for large-scale quantum computers, so error-correcting codes must be chosen carefully for each hardware platform and for multi-chip systems. This paper claims that the two dominant drivers of logical failure are the code’s fault threshold and the effective number of two-qubit operations per correction cycle, and that a binomial-tail probability on those quantities already gives useful leading-order estimates. The same model is extended to split local versus interconnect operations and to biased noise, allowing rapid comparison of topological, subsystem, concatenated, qLDPC and Floquet codes on trapped-ion, superconducting and neutral-atom machines. Qualitative orderings seen in expensive full-stack simulations reappear analytically, and the framework locates concrete “sweet-spot” regions—numbers of chips and code distances—where distribution improves logical error despite noisier links. Designers therefore gain a fast way to decide which codes are practical and when multi-chip architectures become advantageous without running full simulations for every candidate.

Core claim

Logical error rate is bounded, to leading order, by the probability that the total number of independent physical faults in one correction cycle exceeds the code’s correctable threshold κ = t + 1. Once circuit volume (native two-qubit gates plus routing, measurement and interconnect overhead) and per-location error rates are known, this single binomial (or multi-class Poisson-binomial) tail reproduces the main performance trends of advanced QEC codes across platforms and identifies the QPU-count and distance at which distributed surface-code or bivariate-bicycle constructions become worthwhile.

What carries the argument

The binomial-tail bound p_L ≤ P[X ≥ κ], where X is the sum of independent fault indicators (or separate binomials for intra- and inter-QPU classes) and κ is the minimum number of faults that can produce a logical error. Circuit volume N_loc and physical error rates enter only through the parameters of X; everything else is abstracted away.

Load-bearing premise

Every set of at least κ independent physical faults is treated as a logical failure, so the model ignores decoder success, error degeneracy, ancilla-only faults and correlated noise.

What would settle it

Run full-stack syndrome-extraction simulations (or real-device experiments) for the same code instances and physical error rates used in the paper’s tables; if the measured logical error rates reverse the predicted ordering of codes or show no sweet-spot improvement near the claimed q ≈ 9, d = 29 surface-code point, the leading-order claim fails.

Watch this falsifier — get emailed when new claim-graph text bears on it.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper introduces a lightweight binomial-tail framework for estimating logical error rates of advanced QEC codes (topological, subsystem, concatenated, qLDPC, Floquet) across trapped-ion, superconducting and neutral-atom platforms as well as distributed multi-QPU systems. Logical failure is bounded by p_L ≤ P[X ≥ κ] where X is the number of independent physical faults per cycle and κ = t + 1; N_loc is taken primarily from two-qubit gate counts (with extensions for routing, inter-QPU links and biased noise). Code parameters are drawn from the ECCentric study; the model is used to rank codes, reproduce qualitative simulation trends, and locate distributed “sweet spots” (e.g., q ≈ 9, d = 29 for a surface-code-like scaling at interconnect ratio r = 10).

Significance. If the leading-order picture is reliable, the framework supplies a transparent, computationally cheap screening tool that can identify which code–hardware combinations are even plausible before expensive full-stack simulation, and that can map the design region in which distributing a code across multiple QPUs improves rather than degrades logical performance. The explicit separation of intra- versus inter-QPU faults, the inclusion of bias-tailored distances, and the concrete numerical sweet-spot tables are useful contributions for architecture-level exploration. The authors correctly flag the model’s dual optimism/pessimism and do not claim quantitative decoder-level accuracy.

major comments (3)
  1. [III.A, Eq. (1)–(2); IV.B, Tables IV–V] Section III.A Eq. (1) and the distributed extension Eq. (2) treat every configuration of ≥κ independent faults as a logical failure. The authors themselves note (after Table III) that many such sets are non-malignant (ancilla-only, correctly decoded, degenerate or non-logical). All numerical results—Table III, Fig. 2, Tables IV–VIII and the reported sweet spots (q = 9, d = 29, p_L ≈ 6.94 × 10^{-10})—are generated from the raw binomial tail with no malignancy fraction or decoder model. Because the absolute p_L values and the precise (q, d) coordinates of the optima rest on the untested assumption that this fraction is roughly constant across N_inter and code family, a sensitivity study (or an explicit statement that only qualitative ordering is claimed) is required for the central distributed-QEC claim to be load-bearing.
  2. [IV.B.1–2, Tables V, VII–VIII] The distributed surface-code and BB scaling studies introduce free parameters α = 4 (boundary overhead), λ = 0.25 (BB embedding factor), and the prefactors N_2Q(d) ≈ 11 d^{2} / 18 d^{2}. Tables V, VII and VIII show that the location of the sweet spot moves dramatically with r and λ. Without a systematic sweep or justification that these particular values are representative rather than illustrative, the concrete “sweet-spot design region” advertised in the abstract and Section V cannot be regarded as robust.
  3. [IV.A, after Table III] The only quantitative comparison with ECCentric is an average p_L at a single physical error rate p = 0.004 (text after Table III). Per-code ordering, distance dependence and the effect of routing overhead are not checked. Because the paper’s claim is that the analytic model “reproduces qualitative trends observed in larger-scale simulations,” a more granular side-by-side comparison (or an explicit list of which trends are reproduced) is needed to substantiate that assertion.
minor comments (4)
  1. [Table II] Table II lists “Gauge Color (2D) ≈ 11”; the approximate distance should be stated precisely or the source of the approximation clarified.
  2. [Fig. 1] Figure 1 caption and axis labels do not indicate whether the curves are the exact binomial tail or a Poisson approximation; a one-line clarification would help reproducibility.
  3. [II.B, III] The notation N_loc is used both for the ideal two-qubit count and for the inflated count that includes SWAPs/measurements; a consistent subscript convention (e.g., N_loc^(eff)) would reduce ambiguity in Sections II–III.
  4. [IV, Table II] Reference [7] (ECCentric) is cited as the source of all circuit volumes; a short appendix table reproducing the exact N_2Q and n_phys numbers extracted from that work would make the present manuscript self-contained.

Circularity Check

0 steps flagged

No circularity: binomial-tail estimates and distributed sweet spots are direct numerical consequences of independently sourced code parameters, hardware rates, and stated scalings, not fits or self-definitional reductions.

full rationale

The central construction (Section III.A Eq. (1), distributed extension Eq. (2), biased-noise Eq. (4)) is the elementary binomial (or Poisson-binomial) tail p_L ≤ P[X ≥ κ] with X the count of independent faults. Code instances (Table II: N_2Q, d, κ) are taken verbatim from the external ECCentric simulation study [7]; physical rates p_2Q are taken from published hardware numbers (Apollo, Willow, Flamingo, Infleqtion). Distributed scalings (n_phys(d)≈2d^{2}, N_2Q(d)≈11d^{2}, N_inter=αd(q-1) with α=4; analogous BB forms with free embedding factor λ) are stated as modeling assumptions, not fitted to any target p_L. The resulting Table III values, Fig. 2/3 curves, and sweet-spot coordinates (e.g., q=9, d=29 at r=10) are therefore ordinary numerical evaluations of those inputs; they do not re-state a fitted quantity as a prediction, nor do they rest on a self-citation uniqueness claim or an ansatz smuggled from the authors’ prior work. Self-citations [1],[2] appear only for background on DQC and are not load-bearing for the error-rate formulas. The acknowledged pessimism of the raw tail (non-malignant faults) is a modeling limitation, not a circular reduction. Hence the derivation chain is self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

4 free parameters · 4 axioms · 0 invented entities

The central numerical claims rest on a short list of modeling choices and externally supplied numbers rather than on new physical postulates. The free parameters are the hand-chosen scaling coefficients and noise ratios used in the distributed sweeps; the axioms are the standard independent-fault and threshold-failure assumptions of the binomial model; no new entities are invented.

free parameters (4)
  • α (inter-QPU boundary overhead) = 4
    Set by hand to α=4 in the surface-code distributed model; controls how fast N_inter grows with q and d and therefore moves the sweet-spot location.
  • λ (BB embedding factor) = 0.25 (default)
    Fraction of two-qubit gates that become inter-QPU under partitioning; swept over {0.05,0.10,0.25,0.50,1.00} and strongly affects whether distribution helps BB codes.
  • r = p_inter / p_intra = 10 (main case)
    Interconnect noise ratio; representative values 1,3,10,30 are chosen by hand to map the design space.
  • N_2Q(d) scaling prefactors = 11 and 18
    Surface N_2Q≈11d² and BB N_2Q≈18d² are normalized to the single benchmark instances of Table II rather than derived from first principles.
axioms (4)
  • domain assumption Faults at distinct circuit locations are independent Bernoulli trials, so the total fault count is binomial (or Poisson-binomial).
    Stated in Section III.A and used for every p_L bound; standard but known to be violated by crosstalk and leakage.
  • ad hoc to paper Logical failure occurs whenever the number of faults reaches or exceeds κ = t+1, independent of decoder, syndrome structure or degeneracy.
    Eq. (1) and the distributed extensions; the paper itself notes this is a pessimistic upper bound.
  • domain assumption Two-qubit gate count (plus simple routing/interconnect additives) is a sufficient leading-order proxy for total fault locations.
    Section III opening paragraphs; measurement, idle and SPAM errors are declared negligible.
  • domain assumption Code parameters (d, N_2Q) taken from the ECCentric simulation study are representative of the code families.
    Table II and surrounding text; the paper does not re-derive or re-compile the circuits.

pith-pipeline@v1.1.0-grok45 · 24170 in / 3028 out tokens · 30704 ms · 2026-07-11T21:48:31.831876+00:00 · methodology

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read the original abstract

The theory of quantum error correction was established decades ago. Yet the limitation of the quantum computing platforms in terms of noise level and available physical qubit count persists, which greatly hinders the development of scalable quantum computing systems. In this paper, we present analytical estimates of logical error rates of advanced QEC codes across leading hardware platforms and distributed quantum computing systems using a simple but unified framework. The analysis captures two dominant contributors to logical error: code structure and two-qubit gate overhead. The framework provides a fast estimate of logical error rates and identification of dominating factors in different hardware platforms, such as circuit volume, routing overhead, inter-QPU operations, or asymmetric noise protection. We show that several qualitative trends observed in larger-scale simulations can be reproduced and interpreted analytically within this framework. We further demonstrate that the framework can be used to find the sweet spot design region of distributed QEC, which is critical for the design of distributed quantum computing systems.

Figures

Figures reproduced from arXiv: 2607.04082 by Bryan Pan, Yufeng Xin.

Figure 1
Figure 1. Figure 1: Logical error estimates per round vs. two-qubit error rate for different QEC codes optimize code distance under a fixed physical-qubit budget, rather it compares fixed benchmark instances. By contrast, the distributed-QPU sweeps in Section IV-B include a simplified capacity constraint, so any improvement from distribution should be interpreted as capacity-enabled distance growth rather than an intrinsic ad… view at source ↗
Figure 2
Figure 2. Figure 2: Distributed-QPU logical error estimate as a function of QPU count. Each QPU assumed to support 200 physical qubits, nphys ≈ 2d 2 , N2Q ≈ 11d 2 , and Ninter = 4d(q − 1). where Xintra ∼ Binomial(Nintra, pintra) Xinter ∼ Binomial(Ninter, pinter) [PITH_FULL_IMAGE:figures/full_fig_p008_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: shows the resulting logical error estimates as a function of QPU count for several interconnect noise ratios using pintra = 10−4 and λ = 0.25. When r = 1, inter-QPU operations are as reliable as local gates, so increasing the number of QPUs improves performance by allowing a larger￾distance BB code. When r = 3, there is still a distribution benefit, but the sweet spot occurs at a smaller QPU count. When r … view at source ↗
Figure 4
Figure 4. Figure 4: Sensitivity of the distributed BB analytical model to the nonlocal embedding factor λ for fixed pintra = 10−4 and r = 10. contrast, BB codes require either highly reliable interconnects or a highly modular layout to benefit from distribution. To test the importance of the embedding assumption, Fig￾ure 4 fixes r = 10. and varies λ. Smaller values of λ correspond to better partitioning, fewer cross-QPU check… view at source ↗
Figure 5
Figure 5. Figure 5: Logical error estimates per round pL vs bias η for a fixed two-qubit error rate of ploc = 10−4 . and bias-tailored topological codes (XZZX). This set lets us isolate how noise bias favors codes with enhanced Z distance relative to standard symmetric ones. It is clear that within this model, codes tailored to more Z errors by having a higher Z distance vastly outperform traditional codes at high levels of η… view at source ↗

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