Paper Citation Record · LEDGER

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration

As of 13 August 2026, this Paper Citation Record lists 38 of 38 outbound references and 0 inbound Pith citation observations for arXiv:2607.04475.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2607.04475 v1

Coverage vector

measured 38 of 38 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-07-11T18:52:57.727698Z

measured 38 of 38 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-13T06:32:02.005865+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

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measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

38 of 38 outbound references displayed

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Outbound references

Observation 2184abda-196a-4c15-a3c7-87c4b0d56ca1 · outbound

This paper cites A multi-mode 8k-mac hw-utilization-aware neural processing unit with a unified multi-precision datapath in 4nm flagship mobile soc,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration A multi-mode 8k-mac hw-utilization-aware neural processing unit with a unified multi-precision datapath in 4nm flagship mobile soc,

Reference 1

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation 924cccc1-25c1-4bc7-bf8a-261a40599570 · outbound

This paper cites A 12.1 tops/w quantized network acceleration processor with effective-weight- based convolution and error-compensation-based prediction,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration A 12.1 tops/w quantized network acceleration processor with effective-weight- based convolution and error-compensation-based prediction,

Reference 2

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation 6f91d019-5d07-4ac3-a9a1-9b5fc41bc18b · outbound

This paper cites A 28nm 0.22uj/token memory-compute- intensity-aware cnn-transformer accelerator with hybrid-attention-based layer-fusion and cascaded pruning for semantic-segmentation,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration A 28nm 0.22uj/token memory-compute- intensity-aware cnn-transformer accelerator with hybrid-attention-based layer-fusion and cascaded pruning for semantic-segmentation,

Reference 3

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation d362f3cf-2610-4c22-aa75-b01313115e73 · outbound

This paper cites Mega.mini: An energy-efficient npu leveraging a novel big/little core with hybrid input activation for generative ai acceleration,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Mega.mini: An energy-efficient npu leveraging a novel big/little core with hybrid input activation for generative ai acceleration,

Reference 4

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation badd646d-dde0-43e4-b59f-9d1b1f3146a7 · outbound

This paper cites T-rex: A 68-to-567us/token 0.41-to-3.95uj/token transformer accelerator with reduced external memory access and enhanced hardware utilization in 16nm finfet,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration T-rex: A 68-to-567us/token 0.41-to-3.95uj/token transformer accelerator with reduced external memory access and enhanced hardware utilization in 16nm finfet,

Reference 5

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation e40d42e4-161b-452d-9d9d-b23a379ed693 · outbound

This paper cites A 28nm 11.2tops/w hardware-utilization- aware neural-network accelerator with dynamic dataflow,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration A 28nm 11.2tops/w hardware-utilization- aware neural-network accelerator with dynamic dataflow,

Reference 6

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation 36361d1c-93a4-4165-b632-849ec6b3c8b8 · outbound

This paper cites How to keep pushing ml accelerator performance? know your rooflines!.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration How to keep pushing ml accelerator performance? know your rooflines!

Reference 7

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation c45916f3-7c52-4ade-be97-cb7e26f7aaeb · outbound

This paper cites Datamaestro: A versatile and efficient data streaming engine bringing decoupled memory access to dataflow accelerators,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Datamaestro: A versatile and efficient data streaming engine bringing decoupled memory access to dataflow accelerators,

Reference 8

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation cabe10f1-0543-4f1b-bf9f-a9e4e20d9867 · outbound

This paper cites Xpulpnn: Enabling energy efficient and flexible inference of quantized neural networks on risc-v based iot end nodes,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Xpulpnn: Enabling energy efficient and flexible inference of quantized neural networks on risc-v based iot end nodes,

Reference 9

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Observation df45acd6-c6de-4388-8987-91d3fb5154eb · outbound

This paper cites Vega: A ten-core soc for iot endnodes with dnn acceleration and cognitive wake-up from mram-based state-retentive sleep mode,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Vega: A ten-core soc for iot endnodes with dnn acceleration and cognitive wake-up from mram-based state-retentive sleep mode,

Reference 10

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation 7e5db5b5-a3cd-49c8-bdde-1b9acedf2b66 · outbound

This paper cites 22.1 A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V , 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration 22.1 A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V , 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing,

Reference 11

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Observation 38e9010c-36dd-48ee-bcf8-31b4714184cc · outbound

This paper cites Mx: Enhancing risc-v’s vector isa for ultra-low overhead, energy-efficient matrix multiplication,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Mx: Enhancing risc-v’s vector isa for ultra-low overhead, energy-efficient matrix multiplication,

Reference 12

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation 46e62a8f-7d3a-426c-a915-8a6bdddaa18a · outbound

This paper cites A 3 tops/w risc-v parallel cluster for inference of fine-grain mixed-precision quantized neural networks,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration A 3 tops/w risc-v parallel cluster for inference of fine-grain mixed-precision quantized neural networks,

Reference 13

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation b7a791eb-27a9-4a82-b3b6-5a9df514ad1e · outbound

This paper cites Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency

Reference 14

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation fb38f0e8-cc55-4d68-a724-e458fd2b5b18 · outbound

This paper cites Quadrilatero: A risc-v programmable matrix coprocessor for low-power edge applications,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Quadrilatero: A risc-v programmable matrix coprocessor for low-power edge applications,

Reference 15

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Observation 8118faea-8b31-46c5-bd0a-e3e16a13cc7d · outbound

This paper cites A survey and comparative analysis of number systems for deep neural networks,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration A survey and comparative analysis of number systems for deep neural networks,

Reference 16

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Observation ffe20df0-061c-4bd3-a019-6ade0df87cf8 · outbound

This paper cites A 22-nm 4.92 tops/w end-to-end rns dnn accelerator for edge-ai devices,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration A 22-nm 4.92 tops/w end-to-end rns dnn accelerator for edge-ai devices,

Reference 17

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

Source-reported events for the cited work

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Observation 46a488d0-9231-411c-9daa-7152b9b043da · outbound

This paper cites Online normalizer calculation for softmax.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Online normalizer calculation for softmax

Reference 18

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Observation 91d79acb-2dc5-4961-8948-d203bb1dd20f · outbound

This paper cites MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration MobileNets: Efficient Convolutional Neural Networks for Mobile Vision Applications

Reference 19

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation 62c0674f-7081-4e6c-a8e7-954641ebdad9 · outbound

This paper cites A 22-nm 4.92 TOPS/W end-to-end RNS DNN Accelerator for Edge-AI Devices,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration A 22-nm 4.92 TOPS/W end-to-end RNS DNN Accelerator for Edge-AI Devices,

Reference 20

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation 5b0d9c53-1322-4e25-a71f-f3d233369ddf · outbound

This paper cites Res-DNN: A Residue Number System-Based DNN Accelerator Unit,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Res-DNN: A Residue Number System-Based DNN Accelerator Unit,

Reference 21

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation 57db284f-d5a5-457c-8f69-0f93de413d11 · outbound

This paper cites A deep convolutional neural network based on nested residue number system,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration A deep convolutional neural network based on nested residue number system,

Reference 22

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation 5a3f8cbe-2268-4897-b809-5379d2c4212f · outbound

This paper cites Application of the residue number system to reduce hardware costs of the convolutional neural network implementation,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Application of the residue number system to reduce hardware costs of the convolutional neural network implementation,

Reference 23

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Observation 6ecd3774-e06e-4ae5-8ccb-270a18411214 · outbound

This paper cites RNSiM: Efficient Deep Neural Network Accelerator Using Residue Number Systems,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration RNSiM: Efficient Deep Neural Network Accelerator Using Residue Number Systems,

Reference 24

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Observation f1b51ce0-4796-45ef-9702-af080f65cd1d · outbound

This paper cites RNSnet: In-Memory Neural Network Acceleration Using Residue Number System,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration RNSnet: In-Memory Neural Network Acceleration Using Residue Number System,

Reference 25

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation d9c352cc-2a22-4d4a-ae0d-f791342dfe21 · outbound

This paper cites A multiplier-Free RNS-Based CNN accelerator exploiting bit-Level sparsity,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration A multiplier-Free RNS-Based CNN accelerator exploiting bit-Level sparsity,

Reference 26

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation eac912b1-6100-4747-b4b8-0ba827e38a63 · outbound

This paper cites A mixed-precision rns dnn accelerator,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration A mixed-precision rns dnn accelerator,

Reference 27

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation c3281081-9623-4741-9114-6ee054625317 · outbound

This paper cites Improving Post Training Neural Quantization: Layer-wise Calibration and Integer Programming.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Improving Post Training Neural Quantization: Layer-wise Calibration and Integer Programming

Reference 28

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Observation d274bf54-fd42-4b65-b22c-535f19ed0901 · outbound

This paper cites Optimal brain compression: A framework for accurate post-training quantization and pruning,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Optimal brain compression: A framework for accurate post-training quantization and pruning,

Reference 29

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation a8f01a8a-069a-4fe5-9b18-2c132f686c82 · outbound

This paper cites Effi- cient Diminished1 Modulo2 n + 1Multipliers,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Effi- cient Diminished1 Modulo2 n + 1Multipliers,

Reference 30

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Observation 84ace0f4-f6b5-4e0b-9f7b-455b0325c492 · outbound

This paper cites Deep Residual Learning for Image Recognition,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Deep Residual Learning for Image Recognition,

Reference 31

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Observation aeaabb7b-7ada-4a4b-9257-e716873bc74e · outbound

This paper cites An Image is Worth 16x16 Words: Transformers for Image Recognition at Scale.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration An Image is Worth 16x16 Words: Transformers for Image Recognition at Scale

Reference 32

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation 278a2294-1f5a-4991-8bd4-b310da961006 · outbound

This paper cites YOLOv3: An Incremental Improvement.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration YOLOv3: An Incremental Improvement

Reference 33

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation e1449024-8328-40b0-97a0-8921bd113d7b · outbound

This paper cites BERT: Pre-training of Deep Bidirectional Transformers for Language Understanding,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration BERT: Pre-training of Deep Bidirectional Transformers for Language Understanding,

Reference 34

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation 8b37ad91-c590-4e9d-a788-406532550c67 · outbound

This paper cites Bit- Blade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Bit- Blade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks,

Reference 35

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation a2053e18-ecd5-435c-83a0-dcdf3565d797 · outbound

This paper cites DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC,

Reference 36

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Observation 41a5135a-9384-4e08-8a18-6c3e7137296a · outbound

This paper cites Bit Fusion: Bit-Level Dynamically Composable Ar- chitecture for Accelerating Deep Neural Network,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Bit Fusion: Bit-Level Dynamically Composable Ar- chitecture for Accelerating Deep Neural Network,

Reference 37

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Unavailable: canonical work link unavailable.

Observation 5816f742-7980-4cfa-88e8-a79f30bb5038 · outbound

This paper cites Toward attention-based tinyml: A heteroge- neous accelerated architecture and automated deployment flow,.

A Reconfigurable and Representation-Adaptive ISA-Based Architecture for Efficient DNN Acceleration Toward attention-based tinyml: A heteroge- neous accelerated architecture and automated deployment flow,

Reference 38

Resolution: unresolved; no resolver link, observed 2026-07-11T18:52:57.727698Z

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Pith citing papers

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