Quantum Software Engineering in Practice: FPGA and AI Integration for Quantum Certification

Adri\'an Pousa; Alejandro Fern\'andez; Jos\'e Manuel Su\'arez; Luis Mariano Bibb\'o; Marcos Guillermo Lammers

REVIEW 3 major objections 8 minor 26 references

Quantum Software Engineering in Practice: FPGA and AI Integration for Quantum Certification

T0 review · 3 major / 8 minor · reviewed 2026-07-09 · glm-5.2

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Pith's one-line read FPGA + LLM hybrid reaches 99.94% of CHSH quantum limit

desk verdict A modular QSE framework for CHSH certification that ships working code but tests its LLM optimizer only in the trivial regime where it isn't needed. read the letter →

arxiv 2607.07597 v1 pith:DRQVTRNG submitted 2026-07-08 quant-ph cs.SEcs.SYeess.SY

Marcos Guillermo Lammers , José Manuel Suárez , Adrián Pousa , Luis Mariano Bibbó , Alejandro Fernández This is my paper · ORCID

classification quant-phcs.SEcs.SYeess.SY

keywords QuantumSoftwareEngineeringCHSHinequalitycertificationFPGAaccelerationLLMoptimizationNISQdevicesentanglementhybridquantum-classicalsystems

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper presents QAccCert, a software framework that combines FPGA hardware acceleration with large language model (LLM) optimization to certify quantum entanglement via the CHSH inequality. The central claim is that integrating these heterogeneous technologies under disciplined software engineering principles transforms quantum certification from a theoretical exercise into a practical, scalable process. The framework uses an LLM (DistilGPT2) to suggest measurement angles based on iteration history, achieving S=2.8267, or 99.94% of the theoretical maximum of 2*sqrt(2), in ideal quantum simulations. An FPGA computes the quantum correlations in parallel, with projected speedups reaching 9.4x over a CPU for the CHSH use case and scaling to thousands of parallel correlations. The paper positions these results as proof that the synergy of modular architecture, hardware acceleration, and adaptive AI is the necessary response to the noise and imperfections of real quantum devices.

What carries the argument

QAccCert (Quantum Accelerated Certification Framework), CHSH inequality, FPGA-accelerated correlation computation, LLM-guided angle optimization (DistilGPT2, Mistral-7B)

What would settle it

Run the QAccCert framework on a real NISQ device with noise. If the LLM-guided optimization does not achieve CHSH violations closer to the device-specific experimental optimum than a simple local search or random search, the claim that LLMs provide adaptive value for imperfect hardware would be undermined.

Watch

Extended reading notes

Core claim

The paper's central discovery is that an LLM can serve as a memory-driven optimizer for quantum measurement parameters, using the history of prior iterations to guide the search toward high-quality solutions. In the experiments, the DistilGPT2 model achieved 99.94% of the theoretical CHSH maximum, outperforming random search (97.3%) and a local perturbation fallback (97.9%) in solution quality. The paper also demonstrates that FPGA parallel computation of quantum correlations provides a constant-time hardware advantage that scales with system size, projecting a 9.4x speedup over CPU for the CHSH protocol and over 2,400x for systems with 1024 correlations.

Load-bearing premise

The paper assumes that using an LLM to suggest measurement angles provides a meaningful advantage for quantum certification, but its own results show a simple local perturbation heuristic achieves 97.9% of the maximum in fewer iterations (35 vs 41), making the LLM's benefit marginal in precision and worse in speed for this specific parameter space.

Editorial extensions

If this is right

If the framework transfers to noisy hardware, the LLM's ability to learn device-specific imperfections could reduce the number of costly quantum measurements needed for certification on real NISQ devices.
The modular architecture means the LLM or FPGA can be swapped independently, allowing the framework to adapt as quantum hardware and AI models evolve without full system redesigns.
Extending the approach to multipartite systems like GHZ states would test whether the LLM-guided optimization scales to higher-dimensional parameter spaces where brute-force search is infeasible.
Projected FPGA speedups suggest that for large-scale quantum benchmarking involving thousands of correlations, dedicated hardware could become a bottleneck-removing necessity rather than an optional accelerator.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The paper's own data shows that a simple local perturbation heuristic converges in 35 iterations versus the LLM's 41, reaching 97.9% of the maximum. This suggests the LLM's advantage is in precision of the final result, not in convergence speed, and it remains unclear whether the marginal precision gain (99.94% vs 97.9%) justifies the computational overhead of running a language model.
Because all experiments use an ideal simulator without a noise model, the claim that LLMs can adapt to hardware imperfections is untested. The framework's value on real NISQ devices depends on whether the LLM can distinguish noise-induced patterns from signal in the iteration history, which is a different and harder problem than exploring a smooth ideal parameter space.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Desk Editor's Note

read the letter

Short version: the paper builds a real, modular software system (QAccCert) that integrates an FPGA, two LLMs, and Qiskit for CHSH entanglement certification, with a public GitHub repo. The engineering is genuine and the architecture is clean. But the central empirical claim — that LLM-guided optimization is useful for certification — is tested only in ideal, noise-free simulation where the optimum is analytically known, which is exactly the regime where the LLM is least necessary. The stress-test concern lands squarely on the paper's own logic: §IV.D.2 justifies LLMs by arguing that on real NISQ hardware the theoretical angles won't be optimal due to noise, yet all experiments use AerSimulator with no noise model. In that regime, the CHSH optimum is a 4-parameter search with a known closed-form solution. The paper's own data confirms the problem: the local perturbation fallback reaches 97.9% of the maximum in 35 iterations, while the best LLM (DistilGPT2) reaches 99.94% but needs 41 iterations. That's a marginal precision gain at higher iteration cost. Mistral-7B, the more capable model, does worse than both at 95.1% in 46 iterations — which is hard to reconcile with the claim that LLM reasoning quality drives the optimization. The FPGA story is also incomplete. The measured speedup is negative: the current UART prototype runs at 554 ms/iteration versus 0.002 ms on CPU. The 9.4× speedup is projected for a USB 3.0 interface that was not tested. The projection is plausible but it's not evidence. What the paper does well: the modular architecture is well-motivated, the separation of concerns is real, the code is public, and the QSE framing is applied thoughtfully rather than as decoration. The Verilog implementation and the open-hardware FPGA choice (iCE40) are concrete and reproducible. The paper is honest about its limitations — it explicitly states these are ideal-simulation results and frames them as an upper bound. That said, the honesty about limitations doesn't resolve the core issue: the paper's own justification for using LLMs points to a regime (noisy hardware) that it never tests. The ideal-simulation results don't tell us whether LLMs would actually help where the paper says they would. This is a legitimate QSE case study with a working prototype, but the empirical contribution is thin. It's for readers interested in quantum software architecture and hybrid system design, not for anyone looking for evidence that LLMs improve quantum certification. It deserves a serious referee who can push the authors to run at least one experiment with a noise model — that single addition would make or break the paper's central claim.

Referee Report

3 major / 8 minor

Summary. The paper presents QAccCert, a hybrid framework for quantum entanglement certification via CHSH inequality violation, integrating FPGA-based correlation computation with LLM-guided optimization of measurement angles. The framework is evaluated in ideal Qiskit AerSimulator simulations (no noise model), comparing random search, local perturbation fallback, and two LLMs (DistilGPT2, Mistral-7B) for parameter optimization. The authors report that DistilGPT2 achieves S=2.8267 (99.94% of the theoretical maximum), outperforming the fallback heuristic (S=2.7686, 97.9%) and random search (S=2.7520, 97.3%). FPGA acceleration is characterized at three levels: current UART prototype (554.4 ms/iteration), projected USB 3.0 (0.00084 ms/iteration), and PC-only baseline (0.00197 ms/correlation). The paper frames the work as a Quantum Software Engineering case study demonstrating modular architecture, hardware abstraction, and adaptive optimization.

Significance. The paper provides a concrete software architecture with modular separation of concerns (quantum execution, FPGA acceleration, AI optimization, orchestration), accompanied by working code (GitHub repository linked in Figure 1). The FPGA Verilog implementation and Icestudio-based design represent a reproducible hardware contribution. However, the significance of the central claim—that LLM-guided optimization provides a meaningful advantage for quantum certification—is substantially undermined by the experimental design. The experiments are conducted entirely in ideal simulation where the CHSH optimum is analytically known, which is precisely the regime where the paper's own justification (§IV.D.2) states LLMs are unnecessary. The reported advantage of the best LLM over local perturbation is marginal in precision (1.9 percentage points) and worse in convergence speed (41 vs. 35 iterations). The FPGA speedup is projected rather than measured: the 9.4x figure relies on a hypothetical USB 3.0 interface, while the actual prototype introduces 550 ms of intentional delays. The paper does not provide falsifiable predictions for the noisy regime where LLMs would theoretically be advantageous

major comments (3)

§IV.D.2 and §V: The central justification for using LLMs (adaptation to hardware imperfections where theoretical optima fail) is never tested. All experiments use ideal AerSimulator without a noise model—exactly the regime where θ=[0, π/4, π/8, 3π/8] are analytically optimal. The paper's own data confirms this: the fallback local perturbation achieves 97.9% in 35 iterations, while the best LLM (DistilGPT2) achieves 99.94% in 41 iterations—a marginal precision gain at higher iteration cost. Meanwhile, Mistral-7B (the more capable model) performs worse at 95.1% in 46 iterations, which is inconsistent with the claim that LLM reasoning quality drives optimization. The paper thus demonstrates LLM performance only in a trivial regime and provides no evidence about the noisy regime where the paper's own argument says LLMs would be needed. This is load-bearing because the abstract and conclusion
Table II: The claim that LLM optimization demonstrates 'more efficient parameter space exploration' is not supported by the data. DistilGPT2 requires 41 iterations vs. 35 for the fallback, while achieving only 2.1% higher S. The paper itself acknowledges this trade-off in §V.B.2 ('the LLM's advantage is qualitative, not quantitative'), but the abstract and conclusion still frame LLM optimization as 'efficient.' The inconsistency between the claimed efficiency and the reported iteration counts needs to be reconciled, or the claims should be scaled back to match what the data actually shows.
Table I and §V.B.1: The 9.4x FPGA speedup is projected, not measured. The actual prototype achieves 554.4 ms/iteration (slower than the PC baseline of ~0.08 ms for 4 correlations), with 99.9% of the time consumed by intentional communication delays. The projected USB 3.0 performance (0.00084 ms/iteration) is a calculation based on interface bandwidth, not an empirical measurement. The paper should clearly distinguish between measured and projected performance throughout, and the abstract/conclusion should not present the 9.4x figure as an achieved result. The claim that FPGA acceleration 'significantly reduces classical post-processing times' (§II, contribution 2) is not demonstrated empirically.

minor comments (8)

Abstract: The phrase 'achieving 99.94% of the theoretical limit' could mislead readers into thinking this was achieved on real hardware. The abstract should clarify that all results are from ideal simulation.
§III.B, Eq. (1): The CHSH inequality is presented without defining the correlation function E(α,β) in terms of measurement probabilities. A brief definition would help readers unfamiliar with the protocol.
Algorithm 1, line 13: The condition 'iter mod 2 = 0' for LLM queries is not motivated. Why every other iteration? This design choice should be explained or its sensitivity analyzed.
Table II note: The efficiency percentages are computed as S/(2√2)×100, but 2√2≈2.828 is an approximation. Using 2.828427... would change the reported percentages slightly.
§V.B.1: The phrase 'intentional delays' for the UART prototype is explained only in a note. This should be stated more prominently in the main text, as the 554.4 ms figure is otherwise misleading without these delays.
Figure 3 caption references '41 iterations' but does not explain why this specific iteration count was chosen.
References [14] and [15] are self-citations by the authors. This is acceptable but should be noted for transparency in the related work section.
§VII.B: The future work on initializing with theoretical angles is promising but contradicts the current approach of starting from random angles. This tension should be acknowledged.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for a careful and substantive reading of our manuscript. The report correctly identifies that the central claims about LLM advantage and FPGA speedup are not fully supported by the current experimental evidence in the form they are presently stated. We agree with the referee on two of three major comments and will revise the manuscript accordingly. On the first comment, we partially agree: the referee is right that the ideal-simulation regime does not test the core motivation for using LLMs, and we will scale back claims accordingly. However, we also clarify that the paper's primary contribution is the QSE architecture itself, not a demonstration that LLMs outperform classical optimizers in the ideal regime.

read point-by-point responses

Referee: §IV.D.2 and §V: The central justification for using LLMs (adaptation to hardware imperfections where theoretical optima fail) is never tested. All experiments use ideal AerSimulator without a noise model—exactly the regime where θ=[0, π/4, π/8, 3π/8] are analytically optimal. The paper's own data confirms this: the fallback local perturbation achieves 97.9% in 35 iterations, while the best LLM (DistilGPT2) achieves 99.94% in 41 iterations—a marginal precision gain at higher iteration cost. Meanwhile, Mistral-7B (the more capable model) performs worse at 95.1% in 46 iterations, which is inconsistent with the claim that LLM reasoning quality drives optimization. The paper thus demonstrates LLM performance only in a trivial regime and provides no evidence about the noisy regime where the paper's own argument says LLMs would be needed. This is load-bearing because the abstract and conclusion

Authors: The referee is correct that the ideal-simulation regime does not test the central motivation for LLM-based optimization, and we will revise the abstract, §IV.D.2, and §V to make this limitation explicit. We will remove or qualify language suggesting that the current results demonstrate LLM advantage in the noisy regime. We will also add an honest discussion of the Mistral-7B underperformance, noting that model size does not guarantee better optimization in this task and that the result may reflect sensitivity to prompt design and temperature settings rather than reasoning capability per se. That said, we wish to clarify the paper's intended contribution. The manuscript's primary claim is architectural: QAccCert demonstrates that FPGAs, LLMs, and quantum backends can be integrated within a modular QSE framework with well-defined interfaces. The numerical results serve as a proof of concept that the integration is functional, not as evidence that LLMs outperform classical optimizers. We will make this framing explicit in the revision. We acknowledge that without noisy-regime experiments, we cannot substantiate the claim that LLMs provide meaningful advantage where theoretical optima fail. We will add this as a stated limitation and outline it as immediate future work rather than leaving it implicit. revision: partial
Referee: Table II: The claim that LLM optimization demonstrates 'more efficient parameter space exploration' is not supported by the data. DistilGPT2 requires 41 iterations vs. 35 for the fallback, while achieving only 2.1% higher S. The paper itself acknowledges this trade-off in §V.B.2 ('the LLM's advantage is qualitative, not quantitative'), but the abstract and conclusion still frame LLM optimization as 'efficient.' The inconsistency between the claimed efficiency and the reported iteration counts needs to be reconciled, or the claims should be scaled back to match what the data actually shows.

Authors: The referee is correct. The data shows that DistilGPT2 achieves higher solution quality (99.94% vs. 97.9%) but requires more iterations (41 vs. 35). The word 'efficient' in the abstract and conclusion is misleading because it conflates solution quality with convergence speed. We will revise the abstract to replace 'more efficient parameter space exploration' with language that accurately describes the result: the LLM achieves higher solution quality (higher S value) at the cost of additional iterations. The conclusion will be revised similarly. We will also ensure that §V.B.2's acknowledgment of the qualitative-not-quantitative advantage is consistent with the claims made in the abstract and conclusion. revision: yes
Referee: Table I and §V.B.1: The 9.4x FPGA speedup is projected, not measured. The actual prototype achieves 554.4 ms/iteration (slower than the PC baseline of ~0.08 ms for 4 correlations), with 99.9% of the time consumed by intentional communication delays. The projected USB 3.0 performance (0.00084 ms/iteration) is a calculation based on interface bandwidth, not an empirical measurement. The paper should clearly distinguish between measured and projected performance throughout, and the abstract/conclusion should not present the 9.4x figure as an achieved result. The claim that FPGA acceleration 'significantly reduces classical post-processing times' (§II, contribution 2) is not demonstrated empirically.

Authors: The referee is correct. The 9.4x speedup is a projection based on USB 3.0 bandwidth calculations, not an empirical measurement. The actual prototype with UART is slower than the PC baseline due to intentional communication delays. We will revise the manuscript as follows: (1) The abstract and conclusion will not present the 9.4x figure as an achieved result. (2) Throughout the paper, we will clearly label projected performance as projected and measured performance as measured. (3) Contribution 2 in §II will be reworded from 'FPGA acceleration significantly reduces classical post-processing times' to language that accurately reflects what was demonstrated: the FPGA prototype implements correlation computation in hardware, and projected performance under a high-speed interface suggests potential speedup, but this has not been empirically validated. (4) Table I and Table III will be annotated to make the projected vs. measured distinction unambiguous. revision: yes

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity: the central claim is tested against an external benchmark (CHSH), and self-citations are contextual, not load-bearing.

full rationale

The paper's central claim — that LLM-guided optimization achieves 99.94% of the CHSH theoretical maximum — is evaluated against an external, well-known benchmark (the CHSH inequality, ref [5], external). The optimization result is not forced by construction: the algorithm initializes at the known theoretical angles, but the outcome depends on the LLM's suggestions, and indeed different LLMs produce different results (DistilGPT2 at 99.94%, Mistral-7B at 95.1%), showing the result is not tautologically determined by the setup. Self-citations [14] and [15] (by Lammers and Fernández) appear in related work for quantum resource management context but do not serve as load-bearing premises for the CHSH optimization claim — the architecture and experiments are described self-containedly. The paper's real weaknesses (testing only in noiseless simulation where the optimum is analytically known, marginal LLM advantage over simple local perturbation) are correctness and experimental-validity concerns, not circularity. No step in the derivation chain reduces to its own inputs by definition or by self-citation.

Assumptions & free parameters 3 free parameters · 3 assumptions · 1 invented entities

The framework relies on standard quantum protocols (CHSH) but introduces ad hoc parameters for LLM configuration and FPGA communication delays. The assumption that LLMs are effective optimizers for this problem is a domain assumption weakly supported by the paper's own marginal results. The projected performance relies on an ad hoc calculation for USB 3.0.

free parameters (3)

LLM temperature = 0.5
Set ad hoc for both LLMs to balance exploration and determinism in angle suggestions.
Algorithm iteration count (N_max) = Not specified, but results show 35-46 iterations
The stopping condition depends on reaching a practical optimum (|S-2.828| < epsilon), but the total iteration budget is a free parameter of the experiment.
FPGA communication delays = 20ms initial, 4x10ms pauses, 500ms response
Intentionally introduced software delays in the UART prototype to ensure communication integrity, directly affecting the measured 554.4ms iteration time.

assumptions (3)

standard math CHSH inequality violation is a valid metric for entanglement certification.
Invoked in Section III.B as the foundational protocol for the certification framework.
domain assumption LLMs can identify patterns in optimization history to suggest promising parameters.
Stated in Section IV.D.2 as justification for using LLMs as optimizers. The paper's own data shows this is only marginally better than local search.
ad hoc to paper Projected USB 3.0 performance accurately reflects future FPGA capability.
Used in Table I and III to claim 9.4x speedup and 0.00084ms iteration time, based on calculation rather than measurement.

invented entities (1)

QAccCert Framework independent evidence
purpose: Hybrid certification framework integrating FPGA and AI for quantum processing.
The framework is implemented and tested in simulation, with code provided in a GitHub repository, serving as a concrete case study.

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Cite this review

Pith. "Pith review of Quantum Software Engineering in Practice: FPGA and AI Integration for Quantum Certification." pith.science (2026). https://pith.science/paper/DRQVTRNG

@misc{pith2026260707597,
  author       = {Pith},
  title        = {Pith review of: Quantum Software Engineering in Practice: FPGA and AI Integration for Quantum Certification},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/DRQVTRNG}},
  note         = {Machine review of arXiv:2607.07597}
}

abstract

The emergence of Quantum Software Engineering (QSE) responds to the need for systematic, disciplined, and quantifiable approaches to the development, operation, and maintenance of quantum software. Within this context, quantum computer certification represents a significant challenge: verifying that quantum devices produce valid entangled states despite hardware imperfections, noise, and decoherence. This paper presents QAccCert, a hybrid certification framework developed following QSE principles, demonstrating how heterogeneous technologies like FPGAs and Artificial Intelligence can be integrated for quantum processing. The framework implements entanglement certification through CHSH inequality violation in ideal quantum simulations using Qiskit AerSimulator. Through LLM-guided optimization, the system achieves 99.94% of the theoretical maximum of $2\sqrt{2}$, evidencing more efficient parameter space exploration than random search. These simulated results illustrate how QSE methodologies, combined with strategic technology interconnection, can be applied for practical and scalable quantum certification on real NISQ hardware in future work. This study provides a concrete case study of systematic quantum software development.

Figures

Figures reproduced from arXiv: 2607.07597 by the authors.

**Figure 2.** Quantum circuit for measuring non-locality in entangled states with [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** FPGA acceleration scalability. Top: Total execution time for [PITH_FULL_IMAGE:figures/full_fig_p007_3.png] view at source ↗

Figures from the paper (1 more)

**Figure 4.** Figure 4: Verilog code snippet for correlation computation on the FPGA. [PITH_FULL_IMAGE:figures/full_fig_p008_4.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

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Pith tools

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