Pith. sign in

REVIEW 3 major objections 5 minor 62 references

ScratNet segments thin, irregular semiconductor scratches more accurately by pairing a stem-modified Swin encoder with multi-scale dilated aggregation and anisotropic boundary refinement.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

T0 review · grok-4.5

2026-07-14 13:26 UTC pith:I25NJIXY

load-bearing objection Solid applied decoder engineering for thin semiconductor scratches; gains are real on their data, transfer is the open question. the 3 major comments →

arxiv 2607.10214 v1 pith:I25NJIXY submitted 2026-07-11 cs.CV

ScratNet: A Swin-Based Multi-Scale Dilated Network with Precision Refinement for Semiconductor Scratch Segmentation

Sachin Ranjan , Hoon Kim This is my paper
classification cs.CV
keywords scratch segmentationsilicon wafervision transformersemiconductorSwin Transformermulti-scale dilated aggregationprecision refinementdefect detection
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Surface scratches on silicon wafers and IC dies are thin, low-contrast, and morphologically irregular, so both classical inspection and many CNN segmenters lose edge detail. This paper claims that ScratNet—an end-to-end network that replaces ordinary patch embedding with a convolutional stem, then feeds a hierarchical Swin Transformer into a custom decoder—recovers those edges. The decoder first aggregates all four Swin stages with stage-specific dilated blocks, re-injects the high-resolution stem features, and finally sharpens boundaries with parallel anisotropic kernels. On two internal datasets the design raises scratch-region IoU and Dice while tightening boundary metrics relative to FCN, FPN and UPerNet attached to the same backbones. If the gains hold outside the authors’ lab, automated optical inspection can deliver pixel-precise defect maps that better support yield control and process feedback in high-volume semiconductor manufacturing.

Core claim

When a stem-modified Swin-Base encoder is paired with the proposed Multi-Scale Dilated Aggregation, Stem Integration and Precision Refinement modules, scratch-region IoU/Dice and boundary fidelity consistently exceed those of FCN, FPN and UPerNet on identical backbones for both IC and wafer images.

What carries the argument

The MSP decoder (MDA + SIM + PR): MDA fuses hierarchical Swin stages top-down with paired dilated/non-dilated 3 imes3 blocks at rates (8,1)–(2,1); SIM re-injects early stem features; PR applies parallel 1 imes3/3 imes1/1 imes5/5 imes1 convolutions to restore thin-edge precision.

Load-bearing premise

The two private collections of IC and wafer images used for training and testing adequately represent the illumination, process noise and scratch morphologies found on real production lines.

What would settle it

Train and test the identical ScratNet configuration on an independently collected multi-fab or public semiconductor scratch dataset; if the IoU/Dice advantage over UPerNet and the Boundary-IoU/Hausdorff improvements vanish, the central claim is falsified.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • Inspection systems can replace or augment rule-based and plain-CNN pipelines with higher true-positive rates on thin scratches.
  • Improved Boundary-IoU and reduced Hausdorff distance enable more reliable pixel-level defect sizing for process control.
  • The same decoder modules can be attached to other hierarchical CNN or Transformer encoders without redesign.
  • Even after box-prompt fine-tuning, a general foundation model such as SAM remains inferior on this specialized micro-defect task.
  • Modest geometric augmentation (flips) further lifts scores, indicating the architecture benefits from simple data variation.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The anisotropic refinement branch may transfer to other elongated industrial defects (hairline cracks, filamentary fractures) where directional kernels help.
  • Because gains appear across both ResNet and Swin backbones, the decoder itself—not the encoder choice—is the primary source of improvement.
  • Production deployment still requires latency and power measurements on target factory hardware; the paper’s Titan Xp figures leave that open.
  • Public release of the two datasets would allow external verification of the reported margins and of the SAM comparison.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper proposes ScratNet, an encoder-decoder architecture for binary scratch segmentation on semiconductor IC and wafer images. It replaces the standard Swin patch embedding with a two-layer convolutional stem, then feeds hierarchical Swin features into a custom MSP decoder consisting of Multi-Scale Dilated Aggregation (MDA) that fuses all four stages with stage-specific dilation pairs (8,1)/(6,1)/(4,1)/(2,1), a Stem Integration Module (SIM) that re-injects the high-resolution stem features, and a Precision Refinement (PR) head that applies parallel anisotropic kernels (1×3, 3×1, 1×5, 5×1) before the final 1×1 classifier. Training uses a weighted BCE+Dice loss. On two private collections (749 IC images at 180×180 and 8200 wafer images at 224×224, 80/20 splits plus H/V flips), ScratNet with Swin-Base is reported to outperform FCN/FPN/UPerNet decoders on the same backbones (and UNet/HRNet/ResNet baselines) in scratch-region IoU/Dice, Boundary-IoU and Hausdorff distance, with additional ablations, a SAM zero-shot/fine-tune comparison, and an efficiency table.

Significance. If the reported gains hold under realistic production variation, ScratNet would be a useful, immediately deployable engineering contribution for high-precision semiconductor inspection: the combination of hierarchical Swin features with stage-adaptive dilated fusion and anisotropic boundary refinement is a sensible specialization for thin, low-contrast, elongated defects, and the multi-backbone tables plus component ablations (Tables IV–V) and boundary-aware metrics give a clearer picture than many industrial segmentation papers. The SAM comparison and efficiency numbers further strengthen the practical case. The main limitation on significance is that both datasets are private and the only augmentations are flips; without public release, cross-site tests or multi-seed statistics the claimed robustness for manufacturing remains lab-internal.

major comments (3)
  1. [Section IV-A / Tables I–II] Section IV-A states that k-fold cross-validation (k=5) “was also performed to provide a more reliable performance estimate,” yet Tables I–II and the entire results section report only single 80/20 point estimates with no fold-wise means, standard deviations or confidence intervals. The 2–4 point IoU lifts and Hausdorff reductions that constitute the central claim are therefore unaccompanied by any measure of variability; given the modest IC set size (149 test images) this omission is load-bearing for any claim of consistent superiority.
  2. [Section IV-A and Abstract] The two evaluation collections are private (749 IC + 8200 wafer images). The introduction repeatedly emphasizes “significant noise, variable illumination, and low contrast” as the industrial challenge, yet no cross-tool, cross-fab, or public-benchmark numbers are supplied, nor is any domain-shift protocol described. Consequently the transfer claim that ScratNet is “a scalable and robust solution for automated scratch inspection in high-precision manufacturing” rests on an untested representativeness assumption about the authors’ own acquisition conditions.
  3. [Section IV-E.1 / Table IV] In the ablation narrative (Section IV-E.1) the fully-equipped Swin-Base model is stated to reach 86.21 % IoU / 92.37 % Dice, while Table IV (and Table I) list 87.32 % / 93.48 %. The same discrepancy appears for intermediate configurations. Because the ablation tables are the primary evidence that each module (MDA, SIM, PR) contributes, numerical inconsistency between text and tables undermines confidence in the reported incremental gains.
minor comments (5)
  1. [Figure 1 / Section III-B] Figure 1 caption and the surrounding text refer to the decoder as both “MSP” and “MDA + SIM + PR”; a single consistent acronym would help.
  2. [Section III-C] The loss weights λ and μ in Eq. (14) are never given numerical values, nor is a sensitivity study provided; they should be stated for reproducibility.
  3. [Table II] In Table II the column header “Prec.” appears under both scratch-only and full-image blocks; the scratch-only Precision values are near 100 % for almost every model, which is expected under extreme class imbalance but should be briefly discussed so readers do not over-interpret them.
  4. [Figures 5–6] Several qualitative examples in Figures 5–6 show ScratNet IoU lower than a baseline on individual images; a short note on failure modes would balance the presentation.
  5. [Section III-B.1] The stem equations (3)–(4) use Pool(·) without specifying max- or average-pooling; the implementation detail matters for exact reproduction.

Circularity Check

0 steps flagged

No circularity: purely empirical supervised architecture with ablations and external baselines; no derivation reduces to its inputs by construction.

full rationale

ScratNet is an end-to-end encoder-decoder (modified Swin backbone + MDA/SIM/PR modules) whose claims are performance numbers on two private datasets (Tables I-II) plus ablations (Tables IV-V). There is no first-principles derivation, uniqueness theorem, or fitted constant that is later re-labeled a prediction. Hyper-parameters (dilation rates (2,1)/(4,1)/(6,1)/(8,1), anisotropic kernels, loss weights) are selected by explicit ablation, not hidden definitions. Self-citations ([47],[48],[51],[53]) are prior industrial applications by the same group and do not underwrite the central IoU/Dice/Boundary-IoU gains, which rest on direct comparison against FCN/FPN/UPerNet under identical training. The paper is therefore self-contained against its own experimental protocol; any transfer risk is a domain-shift concern, not circularity.

Axiom & Free-Parameter Ledger

4 free parameters · 3 axioms · 3 invented entities

The central performance claim rests on standard supervised-segmentation assumptions plus a handful of design choices (dilation schedule, anisotropic kernels, loss weights) that are selected by ablation rather than derived. No new physical entities are postulated; the invented modules are engineering constructs whose value is measured empirically on private data.

free parameters (4)
  • dilation rates (r_i)
    Chosen as (8,1),(6,1),(4,1),(2,1) by ablation (Table V); different schedules change IoU by several points.
  • PR kernel sizes
    1×3/3×1/1×5/5×1 selected after testing smaller alternatives; directly affects boundary metrics.
  • loss weights λ, μ
    Balance BCE vs Dice; values not reported, only that a composite is used.
  • learning rate / schedule / batch size
    1e-4, decay on plateau, batch 32; standard but still free choices that affect final numbers.
axioms (3)
  • domain assumption Hierarchical Swin features plus skip connections are sufficient multi-scale representations for thin defects
    Invoked throughout Section III-B; the entire decoder is built on this premise.
  • domain assumption BCE + Dice loss adequately handles extreme foreground/background imbalance
    Section III-C; no alternative losses are compared.
  • ad hoc to paper Private IC and wafer collections are representative of production variation
    Section IV-A; no public or multi-site validation is provided.
invented entities (3)
  • Multi-Scale Dilated Aggregation (MDA) module no independent evidence
    purpose: Stage-adaptive fusion of Swin features with paired dilated/non-dilated 3×3 convolutions
    Core decoder block; value shown only by ablation on the authors’ data.
  • Stem Integration Module (SIM) no independent evidence
    purpose: Re-inject high-resolution stem features into the decoder
    Engineering construct whose incremental gain is measured internally.
  • Precision Refinement (PR) branch no independent evidence
    purpose: Anisotropic convolutions to sharpen elongated scratch boundaries
    Final refinement stage; independent evidence limited to the same private test sets.

pith-pipeline@v1.1.0-grok45 · 25849 in / 2685 out tokens · 27427 ms · 2026-07-14T13:26:13.689186+00:00 · methodology

0 comments
read the original abstract

Surface scratch defects in semiconductor manufacturing pose significant challenges due to their irregular shapes, low contrast, and varying scales. Traditional inspection methods often struggle to detect such defects reliably, especially in complex imaging scenarios. While deep learning approaches based on Convolutional Neural Networks (CNNs) have improved accuracy, they often fail to capture fine-grained edge details. To address these limitations, we propose ScratNet, a novel end-to-end scratch segmentation framework that integrates a modified Swin Transformer backbone with a tailored decoder. The decoder incorporates a Multi-Scale Dilated Aggregation (MDA) module to capture both local and global context, a Stem Integration Module (SIM) to restore spatial detail, and a Precision Refinement (PR) branch that enhances boundary sharpness using anisotropic convolutions. Through this stage-adaptive feature aggregation and boundary-aware refinement, ScratNet achieves superior accuracy on thin and irregular defects. Extensive experiments demonstrate that ScratNet consistently outperforms existing methods, providing a scalable and robust solution for automated scratch inspection in high-precision manufacturing.

Figures

Figures reproduced from arXiv: 2607.10214 by Hoon Kim, Sachin Ranjan.

Figure 1
Figure 1. Figure 1: The proposed ScratNet architecture for scratch segmentation in semiconductor images. The input is first processed by a modified Swin Transformer [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: The proposed Multi-Scale Dilated Aggregation (MDA) with Stem Integration Module (SIM). MDA takes as input feature maps from all four stages [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: The proposed Precision Refinement (PR) block. It takes aggregated [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Qualitative comparison of scratch segmentation results on the IC dataset across different decoder modules. Each row shows an input IC image, its [PITH_FULL_IMAGE:figures/full_fig_p008_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Qualitative comparison of scratch segmentation results on the Wafer dataset across different decoder modules. Each row shows an input Wafer image, [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

62 extracted references · 4 linked inside Pith

  1. [1]

    STransFuse: Fusing swin transformer and convolutional neural network for remote sensing image semantic segmentation,

    L. Gao, H. Liu, M. Yang, L. Chen, Y . Wanet al., “STransFuse: Fusing swin transformer and convolutional neural network for remote sensing image semantic segmentation,”IEEE journal of selected topics in applied earth observations and remote sensing, vol. 14, pp. 10 990– 11 003, 2021

    2021

  2. [2]

    Predictive maintenance on the machining process and machine tool,

    A. Jimenez-Cortadi, I. Irigoien, F. Boto, B. Sierra, and G. Rodriguez, “Predictive maintenance on the machining process and machine tool,” Applied Sciences, vol. 10, no. 1, p. 224, 2019. 12

    2019

  3. [3]

    A review of recent advances in surface defect detection using texture analysis techniques,

    X. Xie, “A review of recent advances in surface defect detection using texture analysis techniques,”ELCVIA: electronic letters on computer vision and image analysis, pp. 1–22, 2008

    2008

  4. [4]

    Automated visual inspection in the semi- conductor industry: A survey,

    S.-H. Huang and Y .-C. Pan, “Automated visual inspection in the semi- conductor industry: A survey,”Computers in industry, vol. 66, pp. 1–10, 2015

    2015

  5. [5]

    Automated inspection of surface defects using machine vision,

    M. El-Agamy, M. Awad, and H. Sonbol, “Automated inspection of surface defects using machine vision,”The International Conference on Applied Mechanics and Mechanical Engineering, vol. 17, pp. 1–13, 04 2016

    2016

  6. [6]

    Review of wafer surface defect detection methods,

    J. Ma, T. Zhang, C. Yang, Y . Cao, L. Xie, H. Tian, and X. Li, “Review of wafer surface defect detection methods,”Electronics, vol. 12, no. 8, p. 1787, 2023

    2023

  7. [7]

    Testing open defects in memristor-based memories,

    S. Hamdioui, M. Taouil, and N. Z. Haron, “Testing open defects in memristor-based memories,”IEEE Transactions on Computers, vol. 64, no. 1, pp. 247–259, 2013

    2013

  8. [8]

    Warpage, stresses and koz of 3d tsv dram package during manufacturing processes,

    P. Huang, M. Tsai, C. Huang, P. Lin, L. Huanget al., “Warpage, stresses and koz of 3d tsv dram package during manufacturing processes,” in2012 14th International Conference on Electronic Materials and Packaging (EMAP). IEEE, 2012, pp. 1–5

    2012

  9. [9]

    Inspection and classification of semiconductor wafer surface defects using CNN deep learning networks,

    J.-C. Chien, M.-T. Wu, and J.-D. Lee, “Inspection and classification of semiconductor wafer surface defects using CNN deep learning networks,”Applied Sciences, vol. 10, no. 15, p. 5340, 2020

    2020

  10. [10]

    Tlu-net: a deep learning approach for automatic steel surface defect detection,

    P. Damacharla, A. Rao, J. Ringenberg, and A. Y . Javaid, “Tlu-net: a deep learning approach for automatic steel surface defect detection,” in2021 International Conference on Applied Artificial Intelligence (ICAPAI). IEEE, 2021, pp. 1–6

    2021

  11. [11]

    Artificial intelligence in semiconductor manufacturing,

    G. S. May, T. S. Kim, G. Triplett, and I. Yun, “Artificial intelligence in semiconductor manufacturing,”Wiley Encyclopedia of Electrical and Electronics Engineering, 2001

    2001

  12. [12]

    Integrated circuit packaging defect analysis and deep learning detection method,

    F. Liu, H. Wang, P. Feng, and L. Zeng, “Integrated circuit packaging defect analysis and deep learning detection method,”IEEE Transactions on Components, Packaging and Manufacturing Technology, 2024

    2024

  13. [13]

    Periodic surface defect detection in steel plates based on deep learning,

    Y . Liu, K. Xu, and J. Xu, “Periodic surface defect detection in steel plates based on deep learning,”Applied Sciences, vol. 9, no. 15, p. 3127, 2019

    2019

  14. [14]

    Deep learning for semiconductor defect classification,

    T. Sweeney, S. Coleman, and D. Kerr, “Deep learning for semiconductor defect classification,” in2022 IEEE 20th International Conference on Industrial Informatics (INDIN). IEEE, 2022, pp. 572–577

    2022

  15. [15]

    Deep neural network– based detection and verification of microelectronic images,

    M. A. Reza, Z. Chen, and D. J. Crandall, “Deep neural network– based detection and verification of microelectronic images,”Journal of Hardware and Systems Security, vol. 4, no. 1, pp. 44–54, 2020

    2020

  16. [16]

    Smd led chips defect detection using a yolov3-dense model,

    S.-H. Chen and C.-C. Tsai, “Smd led chips defect detection using a yolov3-dense model,”Advanced engineering informatics, vol. 47, p. 101255, 2021

    2021

  17. [17]

    An image is worth 16x16 words: Transformers for image recognition at scale,

    A. Dosovitskiy, L. Beyer, A. Kolesnikov, D. Weissenborn, X. Zhaiet al., “An image is worth 16x16 words: Transformers for image recognition at scale,”arXiv preprint arXiv:2010.11929, 2020

    Pith/arXiv arXiv 2010

  18. [18]

    Swin transformer: Hierarchical vision transformer using shifted windows,

    Z. Liu, Y . Lin, Y . Cao, H. Hu, Y . Weiet al., “Swin transformer: Hierarchical vision transformer using shifted windows,” inProceedings of the IEEE/CVF international conference on computer vision, 2021, pp. 10 012–10 022

    2021

  19. [19]

    Dilated neighborhood attention transformer,

    A. Hassani and H. Shi, “Dilated neighborhood attention transformer,” arXiv preprint arXiv:2209.15001, 2022

    Pith/arXiv arXiv 2022

  20. [20]

    Segformer: Simple and efficient design for semantic segmentation with transformers,

    E. Xie, W. Wang, Z. Yu, A. Anandkumar, J. M. Alvarez, and P. Luo, “Segformer: Simple and efficient design for semantic segmentation with transformers,”Advances in neural information processing systems, vol. 34, pp. 12 077–12 090, 2021

    2021

  21. [21]

    Cracks segmentation of engineering structures in complex backgrounds using a concatenation of transformer and cnn models driven by scene understanding information,

    C. Zhang, J. Yu, Y . Zhao, H. Wu, and G. Wu, “Cracks segmentation of engineering structures in complex backgrounds using a concatenation of transformer and cnn models driven by scene understanding information,” inStructures, vol. 65. Elsevier, 2024, p. 106685

    2024

  22. [22]

    Scsnet: a novel transformer-cnn fusion architecture for enhanced segmentation and classification on high- resolution semiconductor micro-scale defects,

    Y . Luo, Z. Mei, Y . Qiao, and Y . Chen, “Scsnet: a novel transformer-cnn fusion architecture for enhanced segmentation and classification on high- resolution semiconductor micro-scale defects,”Applied Intelligence, vol. 55, no. 6, p. 439, 2025

    2025

  23. [23]

    Generalized complete local binary pattern for robust scratch detection,

    H. Luo, J. Pan, and W. Zhang, “Generalized complete local binary pattern for robust scratch detection,”IEEE Transactions on Industrial Informatics, vol. 16, no. 7, pp. 4690–4701, 2020

    2020

  24. [24]

    Hypergraph video pedestrian re-identification based on posture structure relationship and action constraints,

    X. Hu, D. Wei, Z. Wang, J. Shen, and H. Ren, “Hypergraph video pedestrian re-identification based on posture structure relationship and action constraints,”Pattern recognition, vol. 111, p. 107688, 2021

    2021

  25. [25]

    Research on the optimizing process of the basic image processing algorithms,

    H. Zhang, “Research on the optimizing process of the basic image processing algorithms,” inCyber Security Intelligence and Analytics. Springer, 2020, pp. 212–217

    2020

  26. [26]

    Machine learning-based image processing for on-line defect recognition in addi- tive manufacturing,

    A. Caggiano, J. Zhang, V . Alfieri, F. Caiazzo, R. Gaoet al., “Machine learning-based image processing for on-line defect recognition in addi- tive manufacturing,”CIRP annals, vol. 68, no. 1, pp. 451–454, 2019

    2019

  27. [27]

    Advances in biomedical signal and im- age processing–a systematic review,

    J. Rajeswari and M. Jagannath, “Advances in biomedical signal and im- age processing–a systematic review,”Informatics in Medicine Unlocked, vol. 8, pp. 13–19, 2017

    2017

  28. [28]

    A wavelet-based approach in detecting visual defects on semiconductor wafer dies,

    C.-H. Yeh, F.-C. Wu, W.-L. Ji, and C.-Y . Huang, “A wavelet-based approach in detecting visual defects on semiconductor wafer dies,”IEEE Transactions on Semiconductor Manufacturing, vol. 23, no. 2, pp. 284– 292, 2010

    2010

  29. [29]

    Short-time discrete wavelet transform for wafer microc- rack detection,

    W.-R. Yang, “Short-time discrete wavelet transform for wafer microc- rack detection,” in2009 IEEE International Symposium on Industrial Electronics. IEEE, 2009, pp. 2069–2074

    2009

  30. [30]

    Polycrystalline silicon wafer defect segmentation based on deep convolutional neural networks,

    H. Han, C. Gao, Y . Zhao, S. Liao, L. Tang, and X. Li, “Polycrystalline silicon wafer defect segmentation based on deep convolutional neural networks,”Pattern Recognition Letters, vol. 130, pp. 234–241, 2020

    2020

  31. [31]

    Detection of spatial defect patterns generated in semiconductor fabrication processes,

    T. Yuan, W. Kuo, and S. J. Bae, “Detection of spatial defect patterns generated in semiconductor fabrication processes,”IEEE Transactions on Semiconductor Manufacturing, vol. 24, no. 3, pp. 392–403, 2011

    2011

  32. [32]

    Decision tree ensemble- based wafer map failure pattern recognition based on radon transform- based features,

    M. Piao, C. H. Jin, J. Y . Lee, and J.-Y . Byun, “Decision tree ensemble- based wafer map failure pattern recognition based on radon transform- based features,”IEEE Transactions on Semiconductor Manufacturing, vol. 31, no. 2, pp. 250–257, 2018

    2018

  33. [33]

    Non-destructive detection of sub-micron imperceptible scratches on laser chips based on consistent texture entropy recursive optimization semi-supervised network,

    P. Liu, “Non-destructive detection of sub-micron imperceptible scratches on laser chips based on consistent texture entropy recursive optimization semi-supervised network,”arXiv preprint arXiv:2503.13125, 2025

    Pith/arXiv arXiv 2025

  34. [34]

    Inspection and classification of semiconductor wafer surface defects using cnn deep learning networks,

    J.-C. Chien, M.-T. Wu, and J.-D. Lee, “Inspection and classification of semiconductor wafer surface defects using cnn deep learning networks,” Applied Sciences, vol. 10, no. 15, p. 5340, 2020

    2020

  35. [35]

    A novel method based on deep convolutional neural networks for wafer semiconductor surface defect inspection,

    G. Wen, Z. Gao, Q. Cai, Y . Wang, and S. Mei, “A novel method based on deep convolutional neural networks for wafer semiconductor surface defect inspection,”IEEE Transactions on Instrumentation and Measurement, vol. 69, no. 12, pp. 9668–9680, 2020

    2020

  36. [36]

    Deep learning-based detection, classification, and localization of defects in semiconductor processes,

    D. V . Patel, R. Bonam, and A. A. Oberai, “Deep learning-based detection, classification, and localization of defects in semiconductor processes,”Journal of Micro/nanolithography, MEMS, and MOEMS, vol. 19, no. 2, pp. 024 801–024 801, 2020

    2020

  37. [37]

    Machine learning-based detection method for wafer test induced defects,

    K. C.-C. Cheng, L. L.-Y . Chen, J.-W. Li, K. S.-M. Li, N. C.-Y . Tsai et al., “Machine learning-based detection method for wafer test induced defects,”IEEE Transactions on Semiconductor Manufacturing, vol. 34, no. 2, pp. 161–167, 2021

    2021

  38. [38]

    Deformable convolutional networks for efficient mixed-type wafer defect pattern recognition,

    J. Wang, C. Xu, Z. Yang, J. Zhang, and X. Li, “Deformable convolutional networks for efficient mixed-type wafer defect pattern recognition,” IEEE Transactions on Semiconductor Manufacturing, vol. 33, no. 4, pp. 587–596, 2020

    2020

  39. [39]

    Classification of mixed-type defect patterns in wafer bin maps using convolutional neural networks,

    K. Kyeong and H. Kim, “Classification of mixed-type defect patterns in wafer bin maps using convolutional neural networks,”IEEE Transactions on Semiconductor Manufacturing, vol. 31, no. 3, pp. 395–402, 2018

    2018

  40. [40]

    A wafer scratch detection method for correction and completing results of semantic segmentation,

    S. Xu, S. Hao, C. Song, and Z. Zeng, “A wafer scratch detection method for correction and completing results of semantic segmentation,” in2024 IEEE 2nd International Conference on Image Processing and Computer Applications (ICIPCA). IEEE, 2024, pp. 295–299

    2024

  41. [41]

    RA-UNet: A new deep learning segmentation method for semiconductor wafer defect analysis on fine-grained scanning electron microscope (sem) images,

    Y . Qiao, Y . Chen, F. Liu, Z. Mei, Y . Luoet al., “RA-UNet: A new deep learning segmentation method for semiconductor wafer defect analysis on fine-grained scanning electron microscope (sem) images,” IEEE Transactions on Semiconductor Manufacturing, 2025

    2025

  42. [42]

    Global context enhanced resolution networks for sapphire scratch detection and classi- fication,

    G. Zhao, Y . Lin, X. Zheng, B. Chen, S. Wang,et al., “Global context enhanced resolution networks for sapphire scratch detection and classi- fication,”Optics & Laser Technology, vol. 184, p. 112522, 2025

    2025

  43. [43]

    Deepsem-net: Enhancing sem defect analysis in semiconductor manufacturing with a dual-branch cnn- transformer architecture,

    Y . Qiao, Z. Mei, Y . Luo, and Y . Chen, “Deepsem-net: Enhancing sem defect analysis in semiconductor manufacturing with a dual-branch cnn- transformer architecture,”Computers & Industrial Engineering, vol. 193, p. 110301, 2024

    2024

  44. [44]

    Fully convolutional networks for semantic segmentation,

    J. Long, E. Shelhamer, and T. Darrell, “Fully convolutional networks for semantic segmentation,” inProceedings of the IEEE conference on computer vision and pattern recognition, 2015, pp. 3431–3440

    2015

  45. [45]

    U-net: Convolutional networks for biomedical image segmentation,

    O. Ronneberger, P. Fischer, and T. Brox, “U-net: Convolutional networks for biomedical image segmentation,” inMedical image computing and computer-assisted intervention–MICCAI 2015: 18th international con- ference, Munich, Germany, October 5-9, 2015, proceedings, part III 18. Springer, 2015, pp. 234–241

    2015

  46. [46]

    Unified perceptual parsing for scene understanding,

    T. Xiao, Y . Liu, B. Zhou, Y . Jiang, and J. Sun, “Unified perceptual parsing for scene understanding,” inProceedings of the European conference on computer vision (ECCV), 2018, pp. 418–434

    2018

  47. [47]

    Polycrystalline silicon wafer scratch segmentation based on deep convolutional autoencoder,

    N. Ranjan, S. Bhandari, Y .-C. Kim, and H. Kim, “Polycrystalline silicon wafer scratch segmentation based on deep convolutional autoencoder,” in2022 International Conference on Electronics, Information, and Communication (ICEIC). IEEE, 2022, pp. 1–4

    2022

  48. [48]

    Xcnet: Enhancing defect detection in sensor boards through data quality analysis and convolutional neural networks,

    S. Ranjan and H. Kim, “Xcnet: Enhancing defect detection in sensor boards through data quality analysis and convolutional neural networks,” 13 Journal of Semiconductor Technology and Science, vol. 25, no. 3, pp. 245–256, 2025

    2025

  49. [49]

    Feature pyramid networks for object detection,

    T.-Y . Lin, P. Doll ´ar, R. Girshick, K. He, B. Hariharanet al., “Feature pyramid networks for object detection,” inProceedings of the IEEE conference on computer vision and pattern recognition, 2017, pp. 2117– 2125

    2017

  50. [50]

    Rethinking atrous convolution for semantic image segmentation,

    L.-C. Chen, G. Papandreou, F. Schroff, and H. Adam, “Rethinking atrous convolution for semantic image segmentation,”arXiv preprint arXiv:1706.05587, 2017

    Pith/arXiv arXiv 2017

  51. [51]

    Wtpose: Waterfall transformer for multi-person pose estimation,

    N. Ranjan, B. Artacho, and A. Savakis, “Wtpose: Waterfall transformer for multi-person pose estimation,” inProceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision Workshops (WACVW), 2025

    2025

  52. [52]

    Deep high- resolution representation learning for visual recognition,

    J. Wang, K. Sun, T. Cheng, B. Jiang, C. Denget al., “Deep high- resolution representation learning for visual recognition,”IEEE trans- actions on pattern analysis and machine intelligence, vol. 43, no. 10, pp. 3349–3364, 2020

    2020

  53. [53]

    Large- scale road network traffic congestion prediction based on recurrent high- resolution network,

    S. Ranjan, Y .-C. Kim, N. Ranjan, S. Bhandari, and H. Kim, “Large- scale road network traffic congestion prediction based on recurrent high- resolution network,”Applied Sciences, vol. 13, no. 9, p. 5512, 2023

    2023

  54. [54]

    Yoloseg with applications to wafer die particle defect segmentation,

    Y .-T. Li, Y .-C. Chan, C.-C. Huang, Y .-C. Hsu, and S.-H. Chen, “Yoloseg with applications to wafer die particle defect segmentation,”Scientific Reports, vol. 15, no. 1, p. 2311, 2025

    2025

  55. [55]

    Deep residual learning for image recognition,

    K. He, X. Zhang, S. Ren, and J. Sun, “Deep residual learning for image recognition,” inProceedings of the IEEE conference on computer vision and pattern recognition, 2016, pp. 770–778

    2016

  56. [56]

    Surface defect detection in industrial appli- cations using reference-based deep learning,

    H. Chen and Z. Zhang, “Surface defect detection in industrial appli- cations using reference-based deep learning,”IEEE Transactions on Industrial Informatics, vol. 11, no. 6, pp. 1309–1318, 2015

    2015

  57. [57]

    Boundary iou: Improving object-centric image segmentation evaluation,

    B. Cheng, R. Girshick, P. Doll ´ar, A. C. Berg, and A. Kirillov, “Boundary iou: Improving object-centric image segmentation evaluation,” inPro- ceedings of the IEEE/CVF conference on computer vision and pattern recognition, 2021, pp. 15 334–15 342

    2021

  58. [58]

    A modified hausdorff distance for object matching,

    M.-P. Dubuisson and A. K. Jain, “A modified hausdorff distance for object matching,” inProceedings of 12th international conference on pattern recognition, vol. 1. IEEE, 1994, pp. 566–568

    1994

  59. [59]

    Segment anything,

    A. Kirillov, E. Mintun, N. Ravi, H. Mao, C. Rolland, L. Gustafson, T. Xiao, S. Whitehead, A. C. Berg, W.-Y . Loet al., “Segment anything,” inProceedings of the IEEE/CVF international conference on computer vision, 2023, pp. 4015–4026

    2023

  60. [60]

    Clipsam: Clip and sam collaboration for zero-shot anomaly segmentation,

    S. Li, J. Cao, P. Ye, Y . Ding, C. Tu, and T. Chen, “Clipsam: Clip and sam collaboration for zero-shot anomaly segmentation,”Neurocomputing, vol. 618, p. 129122, 2025

    2025

  61. [61]

    Better image segmenta- tion with classification: Guiding zero-shot models using class activation maps,

    H. Borgli, H. K. Stensland, and P. Halvorsen, “Better image segmenta- tion with classification: Guiding zero-shot models using class activation maps,” inInternational Conference on Multimedia Modeling. Springer, 2025, pp. 105–111. Sachin Ranjanreceived his Diploma from Tribhu- van University, Nepal, in 2015 and his B.E. degree from Uttarakhand Technical U...

    2025

  62. [62]

    He is currently pursuing M.S. degree in Elec- tronics Engineering at Incheon National University (INU), South Korea, where he is working as a Research Assistant at the Machine Intelligence and Data Science (MINDS) Lab. His research interests include image processing, machine learning, com- puter vision, robotics, 6G mobile communication systems, the Inter...

    1998