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REVIEW 4 major objections 4 minor 53 references

A trivalent planar qubit layout enables lattice surgery between surface-code patches with zero additional data qubits while preserving modular operation, cutting resource overhead and improving logical teleportation fidelity.

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2026-08-02 00:19 UTC pith:Q6AB73OY

load-bearing objection A careful, honest simulation study: the trivalent resource saving for lattice surgery is real, but the headline fidelity gains ride on an unmeasured gate-speed model and the abstract's scaling claim needs a fix. the 4 major comments →

arxiv 2607.15044 v2 pith:Q6AB73OY submitted 2026-07-16 quant-ph

Towards logical entanglement creation in trivalent planar architectures

Lukas B\"odeker , Luis Colmenarez , Sergey Blinov , Ants Remm , Simon Gustavsson , Markus M\"uller This is my paper
classification quant-ph MSC 81P7081P68 PACS 03.67.Pp03.67.Lx
keywords surface codelattice surgerytrivalent connectivitylogical teleportationquantum error correctionfluxoniumplanar architecturefault tolerance
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper extends the trivalent (degree-three connectivity) measurement scheme for the surface code to lattice surgery, the subroutine that creates logical entanglement between encoded qubits. It shows that in a trivalent layout, boundary ancilla qubits sit on only two sides of each patch, so two patches can be merged by interleaving their error-correction cycles without a stripe of extra data qubits. This shrinks the additional resources for a distance-d merge from d data qubits and d+1 ancillas to zero data qubits and one ancilla, and cuts the extra two-qubit gates from about 6d^2 to 2d^2. Simulations of logical-state teleportation show a lower logical error rate under a standard circuit-level noise model, with the advantage growing with code distance. Under an experimentally motivated noise model that assumes lower connectivity enables faster two-qubit gates (as expected for fluxonium qubits), logical teleportation fidelity improves by up to about 50% for distance three.

Core claim

The central claim is that lattice surgery—measuring the joint logical parity of two surface-code patches to create a Bell state or teleport a logical state—can be implemented in the trivalent architecture with strictly fewer auxiliary resources than in the conventional four-valent layout, without sacrificing modular operability of the two patches. Because the trivalent readout schedule places boundary ancillas on only two sides of each patch, the merging region between two patches is a single column of plaquette stabilizers, independent of code distance. Merging is done by running the two patches' QEC cycles in parallel, with one patch executing the adjoint of the other's circuit, and measur

What carries the argument

The load-bearing mechanism is the trivalent stabilizer-measurement schedule, a degree-three readout scheme for the surface code in which each weight-four plaquette is measured via ancilla qubits that couple to at most three neighbors, using bridge ancillas to relay error information and alternating each QEC round with its adjoint circuit. The paper's contribution is the observation that this arrangement leaves the boundary of each patch with ancillas on only two sides, so two patches can be merged by simply interleaving their alternating QEC cycles—one running the original circuit, the other the adjoint—and measuring the resulting extended boundary stabilizers. No data-qubit stripe is needed

Load-bearing premise

The predicted fidelity improvements hinge on the assumption that reducing valency from four to three lets two-qubit gates run about 25% faster with an error-rate decomposition p2=(1−α)0.4%+η·α·0.4%, which the authors state is hard to pin down experimentally; if no speed-up occurs, trivalent surgery is actually worse than four-valent at distances 5 and 7 under realistic idling noise.

What would settle it

Measure the two-qubit gate time and error rate for a fluxonium qubit coupled to three versus four neighbors under a fixed total capacitance budget. If the gate time does not drop by roughly a factor 3/4, or if the error rate does not follow the model's dependence on gate time, the predicted up-to-50% logical teleportation fidelity improvement will not materialize, and the trivalent scheme would be expected to underperform four-valent at d≥5 in realistic noise.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • A trivalent planar processor can run surface-code lattice surgery with fewer physical qubits, reducing the qubit footprint of multi-logical-qubit algorithms by O(d) per merge.
  • The reduction in two-qubit gates lowers the leading-order prefactor of the logical error rate, so the advantage over four-valent surgery grows as code distance increases.
  • The trivalent surgery protocol is compatible with modular operation: each patch can be initialized, measured, and error-corrected independently before and after the merge.
  • Under the modeled hardware speed-up (gate time about 3/4 of the four-valent value), the trivalent scheme's realistic-noise disadvantage in memory operation is compensated, and surgery fidelity improves by up to about 50%.
  • For fluxonium-based architectures, where capacitance budget limits connectivity, the trivalent layout is a natural fit that can turn the structural surgery advantage into an experimental one.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the 4/3 coupling-strength speed-up is even partially realized, the trivalent architecture's slightly higher idling penalty in repeated memory cycles becomes a secondary consideration, making the whole processor, not just surgery, competitive.
  • The reverse interleaving requirement (one patch runs the adjoint of the other's QEC cycle) implies a global synchronization constraint for multi-patch algorithms; future compilation strategies may need to schedule which patches are 'phase-aligned' to minimize waiting times.
  • The resource counting covers only the merging region; in a large processor where patches are packed, the savings in data qubits may also reduce routing and measurement constraints, an effect not quantified in the paper.
  • A natural extension is to test the trivalent surgery protocol on existing four-valent hardware by using a subset of couplings, as was done for the trivalent memory scheme; the predicted ~2% low-p improvement at d=3 is directly measurable.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

4 major / 4 minor

Summary. The paper studies the trivalent (degree-3) measurement scheme for the rotated surface code, originally introduced in Ref. [21], and extends it to lattice-surgery operations between logical patches. The authors present explicit circuit constructions, reproduce the memory-experiment comparison under a standard circuit-level noise model, and then introduce a trivalent lattice-surgery layout that avoids the additional stripe of data qubits required in the minimal four-valent modular layout. They report resource-count savings (Table 2) and simulate logical teleportation protocols under standard and experimentally motivated noise models, claiming a potential improvement in logical fidelity of up to ~25% in memory and ~50% in surgery when a reduced two-qubit gate time is assumed. The paper is notable for honestly reporting that, without this assumed gate-time improvement, the trivalent surgery protocol is worse than the four-valent one at d=5 and d=7 under the realistic noise model (Fig. 12).

Significance. The structural insight is valuable: the trivalent arrangement of boundary ancilla qubits allows lattice surgery without additional merging data qubits while preserving modularity, and the gate-count savings in Table 2 are concrete and checkable. The paper also contributes explicit circuits and a fair comparison with the four-valent scheme, including a transparent sensitivity analysis over the parameters η and α rather than a fit dressed as a prediction. The main weakness is that the headline fidelity improvement is conditional on an idealized and unmeasured hardware model for fluxonium qubits: the 4/3 coupling-strength argument is a capacitance-based estimate, and the error decomposition p2=(1−α)0.4%+η·α·0.4% is explicitly acknowledged as hard to determine experimentally. Since the paper's own Fig. 12 shows trivalent surgery performing worse at d=5,7 under realistic noise without the gate-time assumption, the performance claim is not yet established in an unconditional sense. The resource-saving claim is more robust and should be the primary stated contribution.

major comments (4)
  1. [Abstract and Table 2] The abstract states that the trivalent protocol reduces two-qubit gates by O(d) out of a total O(d^3), but Table 2 lists 2d^2 versus 6d^2−2 additional two-qubit gates, which is a difference of 4d^2−2 = O(d^2), not O(d). This is a load-bearing scaling claim. Either correct the abstract to 'by O(d^2) two-qubit gates out of a total O(d^3)' (which would be a relative saving O(1/d)), or clarify exactly which gate count is meant. As written, the stated asymptotic saving is inconsistent with the table.
  2. [Section III, Figs. 12 and 13] The central performance claim — improved logical teleportation fidelity — is not established under the experimentally motivated noise model without the additional gate-time assumption. Fig. 12 shows the trivalent protocol is worse than the four-valent protocol at d=5 and d=7 for λ around 1, and the improvement in Fig. 13 (up to ~50%) relies on η∈[0.75,1] and α∈[0,1] with p2=(1−α)0.4%+η·α·0.4%. The authors themselves state that this decomposition is 'hard to determine for a concrete experiment.' The 4/3 coupling-strength argument is an idealized capacitance model, not a measured hardware relation. The abstract and conclusion should therefore present the fidelity improvement as conditional on this assumed hardware benefit, not as a direct benchmark result.
  3. [Section II, Fig. 8] A similar issue affects the memory-experiment improvement of up to ~25%. At η=1, the trivalent memory scheme performs slightly worse than the four-valent scheme for the realistic noise model (Fig. 7). The improvement only appears when the gate time is reduced to η<1 and when α is sufficiently large. The text should more clearly separate the unconditional result (trivalent has a small structural disadvantage under realistic idle-dominated noise) from the conditional scenario (this disadvantage can be overcome if reduced valency improves gate speed as assumed).
  4. [Section III, gate-time comparison] The comparison between trivalent and four-valent surgery is asymmetric: the gate-time improvement η is applied only to the trivalent scheme, while the four-valent scheme is kept at η=1. If future four-valent hardware also benefits from faster gates or improved coupling, the comparison would change. The paper should state explicitly why the gate-time reduction is specific to the trivalent architecture, or should include a symmetric sensitivity analysis.
minor comments (4)
  1. [Section III, noise-model discussion] The text refers to 'Section B' when describing the noise model; this should be 'Section II B' or 'Appendix B' to be consistent with the section numbering.
  2. [Appendix B] Typo: 'controled' should be 'controlled'.
  3. [Fig. 7 caption] 'T 1,2 →T 1/2/λ' appears garbled; it should read T1,2 → T1,2/λ.
  4. [General] The abstract's 'potential improvement of up to ≈25% for distance-three' is ambiguous because the paper reports both memory and surgery improvements with different conditional assumptions. The abstract should identify which protocol and which noise model the 25% refers to.

Circularity Check

0 steps flagged

No significant circularity: the η/α scans are explicit sensitivity analyses, resource savings are direct circuit counts benchmarked externally, and self-citations are not load-bearing.

full rationale

No circular step is present in the paper's derivation chain. The trivalent surgery protocol is given as an explicit circuit construction, and the resource savings in Table 2 (0 vs d additional data qubits, 1 vs d+1 ancillas, 2d^2 vs 6d^2−2 two-qubit gates) are direct counts from the circuits, not fitted quantities. The authors externally benchmark the underlying trivalent stabilizer-measurement scheme by reproducing Ref. [21] memory results, and they credit the independent discovery of the resource savings to Ref. [28]: 'These savings were found independently by Ref. [28].' The headline fidelity improvements are conditional on an explicitly swept hardware model, not on a parameter fitted to a target result: the paper states 'This decomposition is hard to determine for a concrete experiment. Hence, we tune the decoherence-rooted part of the gate infidelity by a factor α∈[0,1]' and 'we therefore explore the whole range of α∈[0,1]'. This is a sensitivity analysis, not a fitted prediction renamed as a result. Moreover, the paper honestly reports the opposite of a forced conclusion: under the realistic unscaled noise model, Fig. 12 shows trivalent surgery performs worse than four-valent for d=5 and d=7, so the advantage is not built in by construction. The self-citations [51] and [53] appear only as context for modular operability and noisy links, respectively, and are not load-bearing for the trivalent surgery construction or its resource counts. No self-definitional reduction, imported uniqueness theorem, or ansatz smuggling via self-citation occurs. The realistic-noise disadvantages and the unmeasured gate-speedup premise are genuine limitations and correctness risks, but they are not circularity.

Axiom & Free-Parameter Ledger

2 free parameters · 5 axioms · 0 invented entities

The central protocol introduces no new physical entities. The main unfree content is the trivalent circuit construction (credited to Ref. [21]) and the lattice-surgery adaptation (partly credited to Ref. [28]). The paper's own free parameters (η, α) control the hardware-benefit model that produces the headline fidelity improvements; without them the realistic-noise comparison shows mixed results.

free parameters (2)
  • eta (η) = 0.75–1.0 (swept, not fitted)
    Scales the two-qubit gate time as t2 = η·47ns, modeling an idealized 4/3 coupling-strength gain from capacitance redistribution. Introduced in Sec. II B and used again in Sec. III.
  • alpha (α) = 0–1 (swept, not fitted)
    Sets what fraction of the two-qubit gate error is decoherence-rooted: p2 = (1−α)0.4% + η·α·0.4%. The authors explicitly say the decomposition is hard to determine for a concrete experiment (Sec. III).
axioms (5)
  • domain assumption The trivalent measurement scheme of Ref. [21] is fault tolerant and has essentially the same threshold as the four-valent scheme under a standard circuit-level noise model.
    Adopted as the starting point; the paper only reproduces it numerically for d=3,5,7 (Fig. 5) and does not re-derive it.
  • domain assumption Depolarizing two-qubit gates, measurement flips, and twirled amplitude-damping/dephasing idling channels adequately capture the relevant hardware noise.
    App. B states this noise model; coherent errors, crosstalk, and leakage are not included.
  • ad hoc to paper Reducing valency increases coupling strength by a factor of 4/3 and reduces gate time to 3/4 without degrading intrinsic gate quality.
    Sec. II B: 'In an idealized scenario...' — this is an unmeasured hardware premise on which the η-scaled fidelity improvements depend.
  • domain assumption Merging two patches by running O(d) rounds of the merged code's stabilizer measurements yields the joint logical parity fault-tolerantly, with the detection-region deformation shown in Fig. 10 being valid.
    Standard lattice-surgery assumption (Ref. [19]) extended to alternating adjoint circuits; supported by simulation, not by a formal proof.
  • standard math Minimum-weight perfect matching decoding with PyMatching, using weights determined by the error model, correctly decodes the surgery circuits.
    Used in all simulations (Figs. 5, 7, 11, 12, 13); standard assumption in the QEC literature.

pith-pipeline@v1.3.0-alltime-deepseek · 17262 in / 14829 out tokens · 149686 ms · 2026-08-02T00:19:01.977842+00:00 · methodology

0 comments
read the original abstract

Low-overhead quantum error-correction schemes are essential for enabling quantum computation on registers containing multiple logical qubits. For planar architectures with limited nearest-neighbor qubit connectivity, the surface code has emerged as the leading paradigm. Recent theoretical and experimental work has shown that a physical-qubit connectivity of degree three is sufficient to implement fault-tolerant quantum error correction. In this work, we study lattice surgery in the context of such trivalent architectures and introduce scalable circuit constructions to implement it. Compared with the four-valent measurement scheme, the trivalent lattice-surgery protocol reduces the required resources by $\mathcal{O}(d)$ qubits out of a total qubit count of $\mathcal{O}(d^2)$ and by $\mathcal{O}(d)$ two-qubit gates out of a total two-qubit gate count of $\mathcal{O}(d^3)$. We benchmark the logical fidelity of both lattice-surgery schemes in terms of experimentally realistic simulations targeting an implementation with a fluxonium qubit based architecture and find a potential improvement of up to $\approx25\%$ for distance-three. These results open a way for scalable planar trivalent qubit architectures to host a surface-code-based logical quantum processor.

Figures

Figures reproduced from arXiv: 2607.15044 by Ants Remm, Luis Colmenarez, Lukas B\"odeker, Markus M\"uller, Sergey Blinov, Simon Gustavsson.

Figure 1
Figure 1. Figure 1: Illustrations of a distance d = 3 rotated surface code or surface-17 patch. In (a) the definition of the code in terms of its stabilizer generators and logical operators is indicated. Generally, red stands for X-type operators and blue stands for Z-type operators. The support of the stabilizer generators corresponds to corner qubits of the colored plaquette, while the logical operators have support on the … view at source ↗
Figure 2
Figure 2. Figure 2: Comparison of the measurement circuits of single weight-four [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Circuitry for conducting a single QEC cycle for the trivalent measurement scheme. The next readout cycle [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Circuitry for initializing the ∣0⟩L state of the d = 3 rotated surface code fault tolerantly by conducting three rounds of stabilizer measurements using the trivalent circuit design. To be read from left to right and then top to bottom. gate execution and finite-duration (mid-circuit) mea￾surements [7, 8, 41–43]. During these periods, qubits accumulate errors that can be modeled by twirled amplitude-dampin… view at source ↗
Figure 5
Figure 5. Figure 5: Comparison of the four-valent and the triva [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Comparison of the qubit layout and connec [PITH_FULL_IMAGE:figures/full_fig_p006_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Comparison of the logical error rate per round [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Comparison of the logical error rate for the [PITH_FULL_IMAGE:figures/full_fig_p007_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Comparison of qubit layouts for performing [PITH_FULL_IMAGE:figures/full_fig_p008_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Merging and splitting of two surface-17 patches using the trivalent stabilizer-measurement scheme and [PITH_FULL_IMAGE:figures/full_fig_p009_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Comparison of the logical error rate for tele [PITH_FULL_IMAGE:figures/full_fig_p009_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: Comparison of the logical error rate for tele [PITH_FULL_IMAGE:figures/full_fig_p009_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: The logical error rate for the teleportation of [PITH_FULL_IMAGE:figures/full_fig_p010_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Circuitry for conducting three rounds of stabilizer measurements of the Fi14Ciitfdtithdf tbilitf thd [PITH_FULL_IMAGE:figures/full_fig_p012_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Full trivalent surgery circuit that was used for the presented simulations in the main text. To be read from Figure 15Full trivalent surgery circuit that was used for the presented simulations in the main textTo be read from [PITH_FULL_IMAGE:figures/full_fig_p015_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Coefficients of the leading-order quadratic expansion of the logical error rate per round for quantum [PITH_FULL_IMAGE:figures/full_fig_p017_16.png] view at source ↗

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