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REVIEW 3 major objections 5 minor 39 references

This paper claims that a shuttling-equipped surface-code processor tolerates 10% static hardware damage, retaining 48–60% of its pristine equivalent distance, so damage can be absorbed by a roughly constant twofold oversizing of the array.

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2026-08-01 04:44 UTC pith:MBRFJCLC

load-bearing objection Solid simulation study showing shuttling-based surface codes tolerate 10% damage with ~50% distance retention; the large-array convergence claim outruns the data. the 3 major comments →

arxiv 2607.22429 v1 pith:MBRFJCLC submitted 2026-07-24 quant-ph

A route to damage tolerance exceeding 10\% in shuttling-equipped quantum processors

Quinten Eggerickx , Simon C. Benjamin This is my paper
classification quant-ph PACS 03.67.Pp03.67.Lx
keywords surface codeshuttling spin qubitshardware defectsdamage tolerancequantum error correctionlatticework architectureroutingfault tolerance
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper tries to establish that shuttling-based quantum processors—where qubits move along predefined paths, as in silicon spin devices—can tolerate far more hardware damage than fixed-in-place systems. The authors take the surface code on a 2D lattice of shuttling corridors, randomly delete up to 20% of the nodes, and use route-solving software to steer each syndrome-extraction ancilla around the defects. Their central result is that at 10% damage the logical qubit retains about 48–60% of its pristine equivalent code distance, and because that retained fraction appears to converge as the array grows rather than falling without bound, the loss can be absorbed by oversizing the hardware by roughly a constant factor—about twofold in linear dimension. The practical stake is that early devices with few-percent defect rates, which are beyond the reach of in-place quarantine methods, might still host a working logical qubit.

Core claim

Under a circuit-level noise model with gate errors at 10^-3 and pure-dephasing shuttle and idling noise (shuttle error 2×10^-4, idling target 10^-3), the authors find that a surface-code logical qubit on a damaged shuttling latticework degrades gracefully: at 5% node deletion all tested arrays retain roughly three-quarters of their pristine equivalent distance, at 10% they retain 48–60%, and even at 20% every grid still hosts a functioning code, with the best distance converging to about 5 on all three grid sizes. The degradation is driven by two mechanisms—a fitting limit that removes the largest embeddable codes, and routing congestion that lengthens shuttling schedules and inflates the id

What carries the argument

The central mechanism is the pre-programmed shuttling schedule: every stabiliser ancilla follows a bespoke, collision-free itinerary through a truncated-square (octagon) latticework whose nodes are partially deleted, with routes found by a greedy space-time search under constraints that enforce stabiliser commutation and hook-error avoidance, and then compiled into a circuit-level simulation whose logical error rates are converted into an 'equivalent distance' by comparison with pristine codes under identical noise. The equivalent-distance metric—the distance a pristine code would need to match the damaged code's error rate—carries the argument, since it makes damage cost expressible as a fr

Load-bearing premise

The load-bearing premise is that the observed convergence of the retained distance fraction across 6x6, 8x8, and 10x10 arrays continues to a size-independent floor; only three sizes are measured, so larger arrays could in principle keep losing fraction and break the constant-oversizing strategy.

What would settle it

Simulate a 16x16 (or larger) latticework at 10% random node deletion with the same noise model and route solver, and compare the mean retained equivalent distance; if it falls significantly below the roughly 48% floor seen at 10x10, the convergence claim fails.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • If the convergence claim holds, a designer can provision for a fixed oversizing factor (about 2x at 10% damage) independent of target code size, rather than paying an ever-growing penalty.
  • A working logical qubit survives across the full 0–20% deletion range studied, with no catastrophic-failure fraction; even at 20% all grids converge to a distance-5 code.
  • Performance is limited primarily by schedule length (idling dephasing) rather than per-hop shuttle fidelity; halving the shuttle error gives only a few percentage points, so improving routing is a more direct lever than improving shuttle fidelity alone.
  • Damage tolerance of other qLDPC codes on the same shuttling latticework is a straightforward extension, potentially revealing which codes best cope with a damaged network.
  • Runtime-emerging damage could in principle be handled by re-solving schedules mid-execution, since the routing machinery is offline-computed and repeatable.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • We infer that the convergence of the retained fraction, observed on only three lattice sizes, needs a test on 16x16 or larger grids; if the floor continues to hold, the constant oversizing rule becomes a practical provisioning formula for defect-tolerant processors.
  • Because the paper's greedy router gives an upper bound on schedule length, we infer that optimal or near-optimal routing could push the congestion-limited regime to higher damage fractions, potentially raising the tolerable damage ceiling beyond 20%.
  • We infer that the 'fragmentation threshold'—where the best code confines itself to a single well-connected island—may be a general feature of damaged networks, and that architectures with higher vertex connectivity or more emitter/receiver nodes could shift it; this is testable by simulating different tilings.
  • Since the error budget is dominated by idling dephasing over the schedule, we infer that asynchronous syndrome extraction, decoupling the round time from the slowest stabiliser, could directly attack the makespan-dephasing product and recover part of the lost distance without hardware changes.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper studies a surface-code logical qubit on a truncated-square shuttling latticework in which a fraction f of lattice nodes are randomly deleted and only the largest connected component is retained. Ancilla itineraries are found with a greedy space-time route solver, compiled into Stim circuits, and evaluated with MWPM decoding under conservative circuit-level and shuttle/idling dephasing noise. Performance is expressed as an equivalent surface-code distance mapped from the pristine-code LER. For 6x6, 8x8, and 10x10 lattices at 10% deletion the authors report retained equivalent distances of 60.0%, 52.2%, and 48.4% of the undamaged distance, and claim this fraction converges to a nonzero large-array floor, so that oversizing the array by a roughly constant factor (about 2x in linear dimension) compensates for 10% damage. Two damage mechanisms are identified: a fitting ceiling for the largest codes and routing congestion that inflates makespan and hence dephasing.

Significance. If the convergence claim is correct, the result is practically significant: it would extend tolerable static damage well beyond the ~1% level reported for fixed-hardware quarantine methods, and the bounded oversizing factor is directly actionable for early spin-qubit devices with imperfect yield. The simulation pipeline is careful: noise parameters are grounded in demonstrated shuttling and dephasing values, comparisons use the same solver for damaged and pristine lattices, ensemble sampling targets SEM <10%, and the congestion mechanism is supported by strong makespan-LER correlations. The principal weakness is that the headline large-array limit and constant-factor oversizing conclusion are extrapolated from only three lattice sizes, and the proposed fragmentation mechanism does not operate at the 10% deletion level where the claim is made. The manuscript is honest about the greedy-router caveat, but the abstract and conclusion state the large-array floor more strongly than the data warrant.

major comments (3)
  1. [Abstract / Section VI.B, Table I] The central practical claim—that at 10% deletion the retained distance converges to ~48% and oversizing by a roughly constant factor compensates—is inferred from only three grid sizes. The sequence 60.0%, 52.2%, 48.4% in Table I cannot statistically distinguish exponential approach to a nonzero floor from a slow power-law decline; the decrements are 7.8 and 3.8 percentage points, and no uncertainty is reported for these entries. The abstract states the large-array limit as a result, while Section VI.B itself says the fraction 'appears to be converging.' Please either add larger lattice simulations (e.g., 12x12 and 16x16 at f=0.1) with a fitted asymptotic model, or revise the abstract and conclusion to state explicitly that the oversizing factor is shown only for the studied sizes and may be size-dependent.
  2. [Table I / Section V.e] The ensemble sampling criterion is a relative standard error of the mean LER* below 10%, but this does not directly bound the uncertainty of the tabulated retained-distance percentages. The differences between grid sizes (e.g., -7.8 vs -3.8 percentage points at f=0.1) may or may not be statistically significant; without error bars or confidence intervals on the means, the claimed 'sub-linear penalty' and convergence trend are not quantitatively supported. Please report SEM (or equivalent) for every entry in Table I and for the derived convergence trend.
  3. [Section VI.C / Fig. 10] The only mechanism offered for a size-independent floor is fragmentation into well-connected islands, but Fig. 10 and the surrounding text place the fragmentation threshold near 15-20% deletion. At f=0.1 the winning distance is still set by the fitting ceiling and congestion, not by a local island scale. Thus the three-point convergence at 10% lacks a supporting mechanism. A percolation-theoretic argument (e.g., scaling of the largest component) could motivate a finite floor, but in its absence the claim should be restricted to the simulated range and the convergence explicitly labeled as tentative.
minor comments (5)
  1. [Section V.f / Table I] The equivalent-distance mapping relies on a pristine log-linear fit that degrades near threshold (R2 < 0.95) and can require extrapolation for high-damage samples. Table I includes entries at f=0.2; please clarify whether any tabulated points depend on extrapolated LER values or degraded fits, and mark or exclude them if so.
  2. [Fig. 5 caption / Section VI.B] The top panel of Fig. 5 is described with '±1 std whiskers,' while other figures use SEM error bars. Please state explicitly which quantity is shown in each panel so the reader can gauge sampling uncertainty.
  3. [Section VI.B / Table I] The retained-distance percentages are normalized to each lattice's undamaged distance dmax = 2G-1, not to the distance of the code actually used on the damaged instance. This is clear in the text but should be restated in the Table I caption and Fig. 5 axis label.
  4. [Section VII] The discussion of 'penalise rather than delete' and 'asynchronous syndrome extraction' is valuable. Please consider adding a sentence noting that these variations could also change the convergence behavior, not just the absolute retained distance.
  5. [References] Reference [1] is cited as arXiv:2604.24739; please confirm the published/peer-reviewed status or mark it as a preprint. Also consider adding a data-availability statement for the simulation and routing code.

Circularity Check

0 steps flagged

No circularity: the simulation pipeline and equivalent-distance metric are self-contained; the convergence claim is an extrapolation, not a definitional reduction.

full rationale

The paper's derivation chain is self-contained. Damaged-lattice schedules are produced by the authors' own greedy router, compiled to Stim, and logical error rates are decoded with PyMatching. The equivalent-distance metric is a post-hoc calibration against a pristine reference curve (Section V.f), rebuilt under identical noise for each parameter set; it is not an input to the routing or error model. The 10%-damage retained fractions in Table I are direct simulation outputs, not fitted parameters renamed as predictions. The only self-citations are background references to prior defect-tolerance work by the same group (e.g., Refs. [5,6,25,26]) and are not load-bearing; no uniqueness theorem or prior ansatz is invoked to force the central claim. The 'convergence' of the retained fraction is inferred from only three lattice sizes (Section VI.B), so the large-array floor and constant-factor oversizing recommendation rest on an extrapolation. That is a correctness risk, not circularity, because the inference does not reduce to the paper's own definitions or fitted inputs.

Axiom & Free-Parameter Ledger

4 free parameters · 6 axioms · 0 invented entities

The central claim relies on a set of noise and modeling parameters (shuttle/idle dephasing, gate error, makespan reference) and several domain assumptions about the shuttling error model and the surface-code ordering. No new physical entities are introduced. The most fragile ledger item is the convergence extrapolation, which is not derived.

free parameters (4)
  • p_shuttle = 2e-4 (primary); 1e-4 (improved value)
    Per-hop pure-dephasing error on shuttle edge transits. Chosen as the knee of the d_eq sweep in Fig. 3; grounded in ~99.5% demonstrated fidelity and ~1e-5 theoretical projected error. The central retained-distance numbers depend on this value.
  • p_idle = 1e-3 (baseline)
    Dephasing error accrued over the ideal M_ideal=32-timestep makespan, setting T2. Chosen at the low edge of the tipping region in Fig. 4; about 20x more pessimistic than T2=10ms would imply. The congestion penalty (makespan*idle-rate) is central to the results.
  • p = 1e-3
    Circuit-level gate, initialization, and measurement error rate, standard in surface-code simulations; cited as consistent with demonstrated silicon spin-qubit fidelities. Not fitted to the damage result.
  • M_ideal = 32 timesteps
    Reference makespan used to convert p_idle into a T2 value. This is a modeling convention; the absolute timestep duration is not specified but cancels in the relative comparisons.
axioms (6)
  • domain assumption Pure dephasing is the dominant error channel for shuttling and idling spin qubits
    The full error model in Section Vb uses ZERROR for shuttle transits and idling, with depolarizing noise for gates. This is physically motivated for spin qubits but is a modeling choice; if other channels dominate, the LERs change.
  • standard math The N-Z hook-error-avoiding syndrome-extraction order is used and assumed valid for the surface code
    Cited to Tomita & Svore [27] and Heim et al. [28]. The router imposes the resulting global precedence constraints.
  • domain assumption Logical error rate vs code distance is log-linear below threshold for the pristine code
    Used to fit ln LER = a + b d' and invert to get d_eq (Section Vf). The paper reports R^2 > 0.97 for the reference fits but notes degradation near threshold.
  • domain assumption The greedy space-time BFS router produces valid routes respecting capacity and precedence constraints, and its makespan is an upper bound
    The router is used for all comparisons; the authors state that an optimal scheduler would reduce congestion and could raise optimum distances, so the headline results may be pessimistic.
  • ad hoc to paper Random uniform node deletion followed by retaining the largest connected component is an appropriate damage model
    Chosen in Section IIIa; the authors note in Section VII that correlated/clustered defects are not captured. Damage tolerance numbers could differ under other defect distributions.
  • ad hoc to paper The observed trend of retained distance fraction vs grid size converges to a finite limit
    Inferred from 6x6, 8x8, 10x10 data in Section VI.B; used to justify the large-array limit and oversizing factor. This is an extrapolation, not a proven scaling law.

pith-pipeline@v1.3.0-alltime-deepseek · 16912 in / 14266 out tokens · 155347 ms · 2026-08-01T04:44:52.484594+00:00 · methodology

0 comments
read the original abstract

This is a short study of an approach offering high tolerance to damage (i.e. defects or 'drop outs') in solid state fault-tolerant quantum computing. Our method is primarily aimed at semiconductor electron spin-qubit systems, which have been shown to support fast and high-fidelity shuttling along pre-defined paths. We adapt the recent CAbLECAR method of Chadwick and Chong: stabilisers are performed by ancillas which each follow a bespoke pre-programmed path. We consider the simple surface code but we damage the physical lattice, and rely on route-solving software to find efficient pathways under constraints enforcing stabiliser commutation and hook error avoidance. Solutions are then converted to detector error models for Stim and logical error rates are obtained. We express our results by gauging the logical performance against that of a pristine lattice, using the notion of a reduced equivalent surface-code distance; for reasonable underlying error rates we find that $10\%$ damage leaves roughly half of the pristine equivalent distance ($d_\text{equiv}\approx0.48\,d_\text{pristine}$ in the large-array limit, rising to $\approx0.60$ for our smallest array). This suggests that one can tolerate substantial damage by building oversized arrays. We note that investigating damage tolerance of other qLDPC codes is a straightforward generalisation, and potentially one could adapt to damage emerging at runtime.

Figures

Figures reproduced from arXiv: 2607.22429 by Quinten Eggerickx, Simon C. Benjamin.

Figure 1
Figure 1. Figure 1: FIG. 1. The truncated-square (octagon) latticework, pristine (a) and after [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. The distance- [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: sweeps the dephasing shuttle rate at a fixed 10% deletion fraction on the 6×6 grid. The mean equivalent distance is essentially flat across the low-rate range — 7.23 at 1.25 × 10−5 down to 6.59 at 2 × 10−4 , a loss of under 0.7 in equivalent distance over more than a decade of shuttling error rate. Beyond 2 × 10−4 it falls sharply (5.86 at 4 × 10−4 , 4.30 at 8 × 10−4 ), and the pristine fit quality degrade… view at source ↗
Figure 4
Figure 4. Figure 4: fixes the shuttle rate at this primary value and sweeps the idling target. Below ∼ 10−3 the winning code size sits on a stable d = 9 plateau; between 10−3 and 2 × 10−3 the winning distance collapses off that plateau and the equivalent distance tips downward in lockstep. We adopt pidle = 10−3 as our baseline — the low edge of this tipping region, i.e. the largest idling error still short of the collapse. As… view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. Equivalent distance retained under damage, as a percentage of each latticework’s undamaged distance [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. Distribution of the winning surface-code distance ( [PITH_FULL_IMAGE:figures/full_fig_p008_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. Per-distance behaviour vs deletion fraction, one line per distance [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. Routing congestion, not code size, degrades the logical error rate. [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9. Retained equivalent distance [PITH_FULL_IMAGE:figures/full_fig_p010_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10. Best-code placement across the fragmentation threshold; all six panels share a common cell size. Each shows one [PITH_FULL_IMAGE:figures/full_fig_p013_10.png] view at source ↗

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Reference graph

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