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Modular quantum processors can run fault-tolerant logical CNOTs across links an order of magnitude noisier than local gates, with only a small drop in the error threshold.

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2026-07-30 10:53 UTC pith:WK3WXJK7

load-bearing objection Solid systems-QEC paper: circuit-level distributed lattice-surgery CNOT thresholds hold up under a simple interface model, plus a clean vertex-cover reduction for GHZ ancillas; the α≃20 headline is only half-derived.

arxiv 2607.27204 v1 pith:WK3WXJK7 submitted 2026-07-29 quant-ph

Fault-Tolerant Logical Operations and Efficient State Preparation in Modular Quantum Architectures with Noisy Interfaces

Siddardha Chelluri , Riccardo Mengoni , Tom Darras , Julien Laurat , Eleni Diamanti , Ioannis Lavdas This is my paper
classification quant-ph
keywords modular quantum computingrotated surface codelattice surgeryfault-tolerant CNOTnoisy interconnectsdistributed GHZ statesvertex coverBell pairs
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper asks whether fault-tolerant quantum computing still works when logical qubits live on separate modules linked by noisy entanglement, not on one monolithic chip. Using the rotated surface code and lattice surgery, the authors simulate nonlocal logical CNOT gates fed by imperfect Bell pairs and find that interface two-qubit noise can be roughly ten times worse than local noise while the fault-tolerance threshold falls only by a few parts in a thousand. The reason is architectural: only a small fraction of the two-qubit gates cross the interface, so local gate noise still dominates the logical error budget. Building on that CNOT primitive, they give a protocol for assembling distributed logical GHZ states across a network of modules, and show that minimizing the number of modules that need extra ancilla patches is equivalent to a vertex-cover problem on a spanning tree of the network. A simple greedy heuristic finds low-ancilla trees in polynomial time. Together the results argue that distributed error correction can scale modular hardware without demanding near-perfect interconnects.

Core claim

Circuit-level simulations of lattice-surgery CNOTs between rotated surface-code patches on different QPUs show that raising the inter-QPU two-qubit error rate to about twenty times the local rate (α ≈ 20) lowers the fault-tolerance threshold by only about 2–3 × 10⁻³ relative to the fully local case. Threshold behavior is dominated by local gates because the nonlocality ratio stays small. The same nonlocal CNOT is then used to fuse local logical GHZ states into a global one, with ancilla placement reduced to a minimum vertex cover on a spanning tree of the QPU graph.

What carries the argument

Nonlocal lattice-surgery CNOT mediated by noisy Bell pairs (interface noise parameter α), together with the nonlocality ratio N_nl/N_l that explains why local noise still sets the threshold; ancilla minimization cast as minimum vertex cover on a spanning tree, solved by a greedy Star-Search heuristic.

Load-bearing premise

Interface noise is treated as a fixed depolarizing multiplier α ≈ 20 obtained by counting extra fault locations and assuming Bell-pair infidelity of order 10ε, without a hardware-specific entanglement model or correlated/biased errors.

What would settle it

Repeat the same circuit-level surface-code CNOT simulations (or a hardware experiment) with a realistic Bell-pair generation channel whose effective error is far above 20× local depolarizing noise or is strongly correlated; if the distributed–monolithic threshold gap then grows large or the threshold disappears, the resilience claim fails.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • Modular surface-code architectures need not demand interconnect fidelity comparable to local gates to stay below threshold for logical CNOTs.
  • Logical multipartite entanglement (GHZ) across modules can be prepared with only n−1 nonlocal fusions and a minimized ancilla footprint given by a tree vertex cover.
  • Star-like network layouts minimize ancilla count at the cost of sequential fusion depth O(n); more branched trees trade ancillas for near-logarithmic depth.
  • Resource estimates and compilers for modular FTQC can treat noisy interfaces as a secondary error budget once the nonlocality ratio is kept small.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the nonlocality-ratio argument generalizes, other lattice-surgery primitives (multi-target CNOTs, magic-state injection across modules) may inherit similar interface tolerance without new threshold analyses for every gate.
  • The vertex-cover framing suggests network topology itself becomes a first-class design knob: choosing QPU connectivity to admit low-cover spanning trees could cut physical ancilla overhead more than improving Bell-pair fidelity alone.
  • Latency and classical communication rounds from gate teleportation are left outside the noise model; including them could reintroduce a time–error trade-off that the static α model hides.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Circularity Check

0 steps flagged

No significant circularity: thresholds come from independent circuit-level Monte Carlo, and the ancilla–vertex-cover link is a proved reduction, not a restatement of inputs.

full rationale

The load-bearing quantitative claim—that inter-QPU two-qubit noise at α≈20 yields only a ~2–3×10⁻³ drop in the lattice-surgery CNOT threshold relative to the monolithic α=1 case—is obtained from circuit-level Stim/LOOM Monte Carlo under an explicit depolarizing model (Eq. 1), not by fitting α or the threshold gap to data. Appendix C sets α≃20 by a first-order fault-location count (α_TeleGate≃10ε from the teleportation circuit plus a stipulated α_Bell≃10ε); that is a modeling choice, not a fitted input renamed as a prediction, and the simulations then report outcomes under that choice. The nonlocality-ratio bounds in Appendix B are gate-count identities used to interpret why local noise dominates; they do not force the simulated logical error rates. On the GHZ side, Theorem 1 proves that ancilla minimization under Algorithm 1 equals min_T τ(T) (and τ(T)=ν(T) on trees by König); this is a standard graph-theoretic reduction from the protocol’s merge constraints, not a circular self-definition. The protocol is inspired by Ref. [48] (overlapping first author), but that citation supplies a prior unencoded fusion idea; the surface-code embedding, resource trade-offs, vertex-cover theorem, and Star-Search heuristic are developed and evidenced in this paper. No uniqueness theorem is imported to forbid alternatives, and no ansatz is smuggled in as a derived law. Overall the derivation chain is self-contained against its stated noise model and graph setup.

Axiom & Free-Parameter Ledger

2 free parameters · 6 axioms · 1 invented entities

Claims rest on standard QEC/stabilizer machinery plus a specific phenomenological interface model and the fusion protocol’s ancilla placement rule. No new physical entities; the main free modeling knob is α≈20 from fault counting. Graph results use classical König/tree facts once the protocol is fixed.

free parameters (2)
  • interface noise factor α = 20 (simulations); α=1 monolithic baseline
    Multiplies local two-qubit error for nonlocal gates; set to 20 in main simulations from α_Bell+α_TeleGate≃10ε+10ε first-order count (Appendix C), not measured on hardware.
  • Erdős–Rényi edge probability p in ancilla numerics = p=0.3
    Graph ensemble for Fig. 3 comparison of DFS/BFS/Star-Search; chosen as p=0.3 with 100 graphs per size.
axioms (6)
  • domain assumption Circuit-level independent depolarizing noise after each 1q/2q gate, with nonlocal 2q gates using error probability α·ε
    Stated in the Distributed Fault-Tolerant CNOT section and Eq. (1); standard phenomenological QEC noise, not derived from a device Hamiltonian.
  • domain assumption Logical CNOT realized by lattice surgery (ZZ then XX merges/splits plus ancilla Z measurement) on rotated surface-code patches
    Appendix A; standard Horsman/Litinski-style construction extended across a noisy interface via gate teleportation.
  • domain assumption Nonlocal physical CNOTs implemented by gate teleportation on noisy Bell pairs whose imperfections are absorbed into α
    Main text and Appendix C; no full entanglement-generation or distillation circuit is simulated.
  • ad hoc to paper Under Algorithm 1, every fusion edge needs an ancilla-enabled endpoint, so feasible ancilla sets are vertex covers of the fusion spanning tree
    Theorem 1 proof (Appendix E); follows from their choice that the nonlocal CNOT target sits in an ancilla QPU and that measured qubits are restored by local CNOTs.
  • standard math König’s theorem: on bipartite graphs (hence trees), minimum vertex cover equals maximum matching
    Invoked in Theorem 1 to set a(T)=τ(T)=ν(T).
  • domain assumption Identical noise for data/syndrome and control/ancilla/target qubits; decoding by minimum-weight matching (PyMatching)
    Simulation Results section; simplifies the threshold comparison.
invented entities (1)
  • Star-Search spanning-tree heuristic (Algorithm 2) no independent evidence
    purpose: Construct low vertex-cover spanning trees for ancilla placement without enumerating all trees
    Greedy center-growth procedure with O(nm) runtime claim (Theorem 2); a method, not a physical object, with empirical comparison only on ER graphs.

pith-pipeline@v1.2.0-grok45-kimik3 · 18679 in / 3611 out tokens · 71542 ms · 2026-07-30T10:53:57.309689+00:00 · methodology

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Modular quantum computing is a leading paradigm for scaling quantum computation beyond the resource limitations of monolithic devices. In this architecture, multiple quantum processing units (QPUs), employing identical or distinct qubit modalities, are interconnected via shared entanglement. Here, we investigate how errors at module interfaces and within individual QPUs affect fault-tolerant computation when qubits are encoded using the rotated surface code. Going beyond the logical-memory benchmark, we perform circuit-level simulations of fault-tolerant nonlocal CNOT gates implemented via lattice surgery between QPUs connected by noisy Bell pairs, and analyze the resulting logical error rates. Our results show that interfaces can tolerate noise up to an order of magnitude higher than intra-QPU noise, with only a minor reduction in the fault-tolerance threshold. We further develop an efficient protocol for preparing distributed fault-tolerant logical GHZ states, reducing ancilla overhead, time, and nonlocal Bell-pair consumption. We show that ancilla minimization in this setting is equivalent to a vertex-cover problem on an associated graph, and introduce a polynomial-time heuristic algorithm for finding low-overhead solutions. Our results provide quantitative evidence that distributed quantum error correction can enable scalable, fault-tolerant quantum computation in modular architectures.

Figures

Figures reproduced from arXiv: 2607.27204 by Eleni Diamanti, Ioannis Lavdas, Julien Laurat, Riccardo Mengoni, Siddardha Chelluri, Tom Darras.

Figure 1
Figure 1. Figure 1: FIG. 1. Modular architecture with rotated surface-code en [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. Threshold plots (logical error rate [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Comparison of three methods for constructing a [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figure 1
Figure 1. Figure 1: In our case, a rotated surface code patch en [PITH_FULL_IMAGE:figures/full_fig_p007_1.png] view at source ↗

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