Pith. sign in

REVIEW 3 major objections 5 minor 132 references

TCAD device models can be made to match real-chip RowHammer and RowPress facts once trap location, migration path, crosstalk, and bulk hole-trap density are treated as first-order parameters.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

Challenge this review Re-run · record.json Download PDF Read on arXiv ↗

T0 review · grok-4.5

2026-07-31 13:48 UTC pith:4254LRAW

load-bearing objection Solid architecture–device bridge that actually closes the main polarity/ACmin gaps prior models left open, with the usual TCAD caveat that a few trap densities are fitted rather than measured on the dies. the 3 major comments →

arxiv 2607.28233 v1 pith:4254LRAW submitted 2026-07-30 cs.AR cs.CR

Demystifying DRAM Read Disturbance: Bridging the Gap Between Experimental Characterization and Device-Level Modeling of RowHammer and RowPress Phenomena

Haocong Luo , Longda Zhou , Ataberk Olgun , \.Ismail Emir Y\"uksel , Nisa Bostanci , Zhigang Ji , Xing Wu , Onur Mutlu This is my paper
classification cs.AR cs.CR
keywords RowHammerRowPressDRAM read disturbanceTCAD simulationbitflip polarityACmincharge traps6F2 layout
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Existing device-level stories of RowHammer and RowPress do not fully explain what real DRAM chips actually do: double-sided hammering produces both 0-to-1 and 1-to-0 bitflips with little spatial overlap, 0-to-1 flips appear at lower aggressor activation counts than 1-to-0, NWL RowPress 0-to-1 flips are unobservable under normal bias, and ACmin for both polarities falls as aggressor-on time rises. This paper maps those facts onto the 6F2 cell layout (neighboring versus passing wordlines), then runs calibrated TCAD simulations and wafer leakage measurements that recover them. The updated picture is that charge-trap location sets double-sided polarity, shorter electron paths and capacitive crosstalk make 0-to-1 easier, process geometry favors more 1-to-0 cells at high hammer count, NWL RowPress leakage is too weak to beat retention under normal voltage, and bulk hole-trap density controls whether RowPress ACmin trends match silicon. A reader who designs tests or defenses cares because today’s mitigations and characterizations rest on incomplete first-order mechanisms; a matching model gives a principled basis for what to measure and what to harden.

Core claim

Prior device models miss major real-chip RowHammer and RowPress metrics of bitflip direction, count, and ACmin. Comprehensive TCAD simulations of a saddle-fin DRAM cell, plus wafer-level leakage measurements, recover those metrics when interface-trap location near NWL versus PWL, electron migration path length, capacitive wordline crosstalk, process-induced trap asymmetry, insufficient NWL RowPress leakage under normal bias, and bulk hole-trap density are included—yielding an updated first-order mechanism set (six takeaways) that replaces the incomplete prior accounts.

What carries the argument

Calibrated Sentaurus TCAD mixed-mode transient simulations of a 1z-class saddle-fin RCAT cell with placed interface electron traps, bulk hole traps, and wordline capacitive coupling. These simulations turn NWL/PWL aggressor roles and trap placement into predicted bitflip polarity and ACmin, then are checked against real-chip spatial patterns and wafer ISN measurements.

Load-bearing premise

The trap placements, interface and bulk trap densities, coupling-noise ratios, and voltage failure threshold used in the simulator are assumed to represent the tested commodity dies, not knobs chosen mainly to recover the observed trends.

What would settle it

Measure double-sided RowHammer polarity overlap on real dies: a high Jaccard index of cells that flip both 0-to-1 and 1-to-0 would contradict trap-location control of polarity; likewise, wafer ISN at VBBW under normal VNWL=VPP that is strongly negative would contradict the claim that NWL RowPress 0-to-1 is unobservable.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

  • Bit-error rate at a high fixed hammer count is not a faithful proxy for ACmin under double-sided RowHammer, because the two polarities have different mechanisms and different ACmin.
  • Characterization should reverse-engineer per-bit NWL/PWL mapping and report polarity-separated ACmin and spatial patterns, not only aggregate BER.
  • Mitigation and refresh design must handle both polarities and the fact that longer aggressor-on time strengthens RowPress leakage of both signs.
  • System-level disturbance models should encode competing trap-assisted and crosstalk paths rather than simple statistical bitflip rates.
  • Process and device work can target NWL-side interface quality and bulk hole-trap density as levers on which polarity dominates.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If trap location truly gates polarity, intentional process skew between NWL- and PWL-side interfaces could bias a die toward one polarity and simplify ECC or targeted refresh.
  • The same trap-and-path competition likely predicts polarity and ACmin shifts for combined RowHammer–RowPress and multi-row patterns as aggressor-on time varies.
  • Campaigns that rank dies only by aggregate high-AC BER may systematically mis-order true first-bitflip vulnerability relative to polarity-aware ACmin.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper aims to close the gap between real-chip RowHammer/RowPress characterization and device-level models. It first maps prior TCAD mechanisms (NWL/PWL electron migration and capacitive effects) onto three first-order observables—bitflip polarity, bitflip counts, and ACmin—then shows that existing models miss several multi-vendor DDR4 facts (both polarities under double-sided RH with little spatial overlap; lower ACmin for 0→1 than 1→0; unobservable NWL RowPress 0→1 under normal bias; ACmin falling with tAggON for both polarities). Using reverse-engineered 6F2 NWL/PWL layout, calibrated Sentaurus RCAT structures, single-trap and uniform-DIT studies, mixed-mode crosstalk, and wafer-level ISN measurements on industry-grade access transistors, the authors produce an updated mechanism set (Takeaways 1–6 / Table 3) and name the modeling knobs (trap location, DIT, DHT,bulk, Vnoise) that control agreement with experiment. Implications for characterization methodology and mitigation design are discussed.

Significance. If the updated mechanisms hold, the work supplies the first systematic, multi-metric bridge between commodity-chip RH/RP phenomenology and device physics, which the architecture/security and device communities both need. Strengths that should be credited explicitly include: multi-manufacturer DDR4 characterization with internal row mapping and true/anti-cell handling; spatial polarity patterns that cleanly match 6F2 NWL/PWL geometry; I–V calibration to manufacturer data; wafer-level leakage measurements that independently support the unobservability of NWL RowPress 0→1 (Takeaway 5); and an explicit inventory of which TCAD parameters decide match vs. mismatch. Even as a carefully constrained phenomenological fit, the paper is a useful foundation for system-level error models and for more efficient characterization campaigns.

major comments (3)
  1. [§5.6, Fig. 19, Takeaway 6, Table 3] §5.6 and Fig. 19: the experimentally observed decrease of ACmin,0→1 with tAggON is recovered only for sufficiently low bulk hole-trap density (DHT,bulk ≲ 1.02e16 cm−3 eV−1); higher DHT,bulk restores the competitive increase predicted by prior models. The manuscript does not report an independent process or electrical measurement of DHT,bulk (or a plausible range) on the tested 1z-class technology. Without that constraint, Takeaway 6 and the claim that the ACmin(tAggON) gap is closed remain a successful fit rather than a demonstrated physical mechanism. Please either (i) cite or add independent bounds on DHT,bulk for the relevant process, or (ii) reframe Takeaway 6 and Table 3 to state clearly that low DHT,bulk is a necessary modeling assumption whose validity is not yet metrologically confirmed on commodity dies.
  2. [§5.4, Takeaway 4, Fig. 15] §5.4 / Takeaway 4: the explanation that more 1→0 than 0→1 cells appear at high AC because NWL-adjacent saddle-fin regions host higher interface-trap density than PWL-side STI is explicitly qualitative and unsupported by NWL-vs-PWL trap metrology or even a cited process split. The low Jaccard overlap in Fig. 15 supports trap-location-determined polarity (Takeaway 1) but does not by itself establish a statistical density asymmetry. Either strengthen with process literature that quantifies the asymmetry, or mark Takeaway 4 as a plausible hypothesis rather than a device-level finding on equal footing with Takeaways 1–3 and 5–6.
  3. [§5.1, Table 2] §5.1 and Table 2: ACmin is defined as the activation count at which |ΔVSN| exceeds a fixed 0.1 V threshold. Sense-amplifier trip points and cell capacitance vary across vendors and are not 0.1 V; the ranking of 0→1 vs 1→0 ACmin and the tAggON slopes could in principle shift with threshold choice. A short sensitivity sweep (e.g., 50–150 mV) showing that the polarity ordering and the sign of dACmin/dtAggON are stable would make the bridge to real-chip ACmin much more convincing. If that sweep is already in hand, please add it; if not, state the limitation explicitly.
minor comments (5)
  1. [Figs. 7–10, 15] Fig. 7–10 and 15: module labels (S0–S4, H0–H3, M0) are not tied back to the die revisions in Table 1 in the figure captions; a one-line legend would help readers map results to process generation.
  2. [§3.2, §4.3] §3 Characteristic 3 vs. §4.3 Observation 3–5: the contrast with Zhou et al. [78] is central; a short explicit sentence stating which simulation assumptions in [78] (symmetric traps, no CC, etc.) are being relaxed would sharpen the novelty claim.
  3. [Fig. 13] §5.2 Fig. 13: units on the ΔVSN1 axes mix µV and mV across panels; please make the scale consistent or call out the order-of-magnitude difference in the caption.
  4. [§7] §7: the claim that BER at high AC is “not a direct proxy” of ACmin for double-sided RH is important for mitigation configuration; a quantitative example (e.g., rank correlation of BER vs ACmin across the tested modules) would make the methodological implication actionable.
  5. [§1, §5.6] Minor typos: “causeunin-tendedbitflips” / “nearbyunaccessed” spacing in §1; “ast AggON” in §5.6 heading.

Circularity Check

1 steps flagged

External chip benchmarks are independent, but several TCAD “matches” (esp. ACmin vs tAggON) are recovered by tuning free trap/noise knobs rather than predicting held-out quantities.

specific steps
  1. fitted input called prediction [§5.6, Fig. 19, Takeaway 6 / Table 3 (PWL RowPress ACmin vs tAggON)]
    "We identify that the density of hole traps in the bulk region of the device (DHT,bulk) is a key factor in modulating the strength of the PWL RowPress-induced 1-to-0 bitflip. ... When DHT,bulk is lower (i.e., blue triangles), it weakens the PWL RowPress-induced 1-to-0 bitflip and amplifies the decreasing trend of ACmin,0−to−1 as tAggON increases. Therefore, the experimentally observed decrease of ACmin for 0-to-1 bitflips with increasing tAggON can be explained by the insufficient strength of PWL RowPress-induced 1-to-0 bitflip in current devices."

    The target chip fact is that ACmin for both polarities falls as tAggON rises. The simulation recovers that sign only after DHT,bulk is lowered into a regime where 1→0 RowPress competition is weak; higher DHT,bulk restores the increasing ACmin,0→1 trend of prior models. The “explanation” is therefore the parameter choice that forces the observed slope, not an independent prediction of ACmin(tAggON). Related knobs (trap site, DIT, Vnoise ratio, 0.1 V threshold in §5.2–5.3) play the same role for polarity and ACmin ordering.

full rationale

The paper’s derivation chain is mostly non-circular: real-DRAM bitflip directions, spatial patterns, ACmin, and BER are measured on commodity modules and used as external benchmarks; wafer-level ISN leakage under NWL bias is a separate experimental constraint. Prior device models are checked against those benchmarks and found wanting, then Sentaurus structures are simulated. That is normal model–data confrontation, not X defined as Y. The only mild circularity is phenomenological: interface-trap sites, DIT, bulk hole-trap density DHT,bulk, and Vnoise ratio are varied until simulated polarity and ACmin(tAggON) recover the same chip trends the knobs were adjusted to explain (explicitly Fig. 19, where only sufficiently low DHT,bulk yields decreasing ACmin,0→1). The paper does not claim a parameter-free first-principles prediction of those curves, and it openly flags key parameters—so this is fitted alignment called mechanism update, not a tautology. Self-citations to overlapping-author gap/device papers supply background, not a uniqueness theorem that forces the result. Score 3 reflects one clear fitted-input pattern without collapse of the central empirical claims.

Axiom & Free-Parameter Ledger

6 free parameters · 6 axioms · 0 invented entities

The central bridge claim rests on standard semiconductor transport/trap physics plus a 6F2/saddle-fin structural model, commodity-chip representativeness, and several trap and coupling densities chosen so simulated leakage matches measured polarity and ACmin trends. No new particles or forces; the load-bearing extras are modeling parameters and the unmeasured process-asymmetry story for high-AC 1→0 dominance.

free parameters (6)
  • Interface trap density DIT = order 1e11–1e12 cm−2 eV−1 (swept)
    Swept (e.g., 2e11–1e12 cm−2 eV−1) to show ACmin ordering under double-sided RH; magnitude is not independently measured on the tested dies.
  • Bulk hole-trap density DHT,bulk = ~9.7e15–1.1e16 cm−3 eV−1 (examples)
    Identified as the knob that switches whether ACmin,0→1 rises or falls with tAggON; lower values chosen to match chip decrease (§5.6, Fig. 19).
  • Single-trap locations (sites 1–6) / trap region placement = sites 2 (NWL) and 4 (PWL) emphasized
    Which side of NWL vs PWL hosts the trap is selected to produce enhancement/suppression of each polarity; central to Takeaway 1.
  • Capacitive crosstalk Vnoise ratio and CC/CWL/RWL network = CC=515 fF, CWL=740 fF, RWL=1 kΩ; Vnoise ratio ~12–14%
    Noise ratios (12–14%) and coupling network set CC-enhanced 0→1 leakage strength (Fig. 17); not extracted from the same modules.
  • SN failure threshold ΔV = 0.1 V = 0.1 V
    Defines simulated ACmin; changes scale absolute activation counts.
  • Cell geometry / doping / work-function set for 1z-nm-like RCAT = nominal Table 2 + Fig. 11 dimensions
    Dimensions and doping taken as typical process values and I–V-calibrated; absolute ACmin inherits this choice.
axioms (6)
  • domain assumption Shockley–Read–Hall, Hurkx BTBT, mobility and quantum-correction models in Sentaurus adequately capture the dominant RH/RP leakage paths at the simulated bias.
    §5.1 physical models; standard TCAD stack without proof that no other mechanism dominates in the tested chips.
  • domain assumption Commodity DDR4 modules use 6F2-like alternating NWL/PWL adjacency so spatial polarity patterns reverse-engineer aggressor type.
    §2.2 and §4.2; matching is near-100% but one die shows 99.7% attributed to repair.
  • domain assumption Bitflips within a 64 ms refresh window under the stated hammer/press patterns are read-disturbance, not retention failures.
    §4.2 methodology claim used to interpret all chip maps.
  • ad hoc to paper A 0.1 V shift of SN from the initialized level is a valid proxy for the first observable sense-amp bitflip (ACmin).
    §5.1 failure definition; ties simulation ACmin to an internal voltage threshold rather than full array sensing.
  • ad hoc to paper NWL-adjacent saddle-fin regions statistically host higher interface-trap density than PWL-side STI regions in BCAT flows.
    §5.4 Takeaway 4; inferred from process literature, not measured on these chips.
  • standard math Standard electrostatics and circuit coupling: inter-WL capacitance produces Vnoise on the victim WL that modulates subthreshold leakage.
    §5.1 CC mixed-mode network; ordinary circuit physics.

pith-pipeline@v1.2.0-daily-grok45 · 30500 in / 4211 out tokens · 87108 ms · 2026-07-31T13:48:16.274874+00:00 · methodology

0 comments
read the original abstract

DRAM read disturbance, like RowHammer and RowPress, is a critical robustness issue where accessing DRAM can cause unintended bitflips in other unaccessed DRAM locations. DRAM read disturbance bitflips significantly impact the safe, secure, and reliable operation of DRAM-based computing systems. Many prior works experimentally characterize these bitflips and propose mitigations based on empirical results. Other device-level works study their underlying physical mechanisms, but these mechanisms do not fully explain all major empirical observations. Our goal is to bridge the gap between experimental characterization and device-level modeling and understanding of RowHammer and RowPress, providing a principled foundation for future work on understanding, characterizing, and mitigating DRAM read disturbance. We first identify and demonstrate gaps and inconsistencies between the physical mechanisms of RowHammer and RowPress described by existing device-level models and experimental characterization of their bitflips. We focus on three fundamental metrics that should map to first-order physical mechanisms: 1) bitflip directions, 2) bitflip counts, and 3) the minimum number of aggressor row activations that trigger the first bitflips (i.e., ACmin). Second, we present a comprehensive and rigorous set of TCAD simulations that match phenomena observed in experimental characterizations of RowHammer and RowPress bitflips. From our results, we 1) summarize updated device-level error mechanisms for understanding RowHammer and RowPress bitflips, and 2) identify key modeling and simulation parameters that significantly affect whether simulation results match real-chip characterization. We discuss implications for 1) rigorous, comprehensive, and efficient experimental characterization methodologies of DRAM read disturbance bitflips, and 2) the design of DRAM read disturbance mitigation techniques.

Figures

Figures reproduced from arXiv: 2607.28233 by Ataberk Olgun, Haocong Luo, \.Ismail Emir Y\"uksel, Longda Zhou, Nisa Bostanci, Onur Mutlu, Xing Wu, Zhigang Ji.

Figure 1
Figure 1. Figure 1: shows the logical organization of DRAM. DRAM stores data in the form of electric charge in the capacitor of each DRAM cell. DRAM cells are organized into a 2D array, and indexed by rows and columns. A row of DRAM cells share the same wordline (WL), which controls their respective access transistors [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Physical layout of DRAM cells showing a) the top [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: Device-Level mechanism of NWL single-sided [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Device-Level mechanism of PWL single-sided [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Device-Level mechanism of double-sided RowHam [PITH_FULL_IMAGE:figures/full_fig_p004_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Device-Level mechanism of a) NWL-induced Row [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Bitflip direction and spatial distribution of single [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Bitflip direction and spatial distribution of single [PITH_FULL_IMAGE:figures/full_fig_p006_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Fraction of 1-to-0 and 0-to-1 bitflips caused by NWL [PITH_FULL_IMAGE:figures/full_fig_p006_9.png] view at source ↗
Figure 11
Figure 11. Figure 11: (a) 3D view of the saddle-fin-based DRAM structure [PITH_FULL_IMAGE:figures/full_fig_p007_11.png] view at source ↗
Figure 14
Figure 14. Figure 14: (a) and (b) compare the ACmin of 1-to-0 and 0-to-1 bitflips under single- and double-sided RowHammer, respec￾tively, for trap locations 2 (black square) and 4 (red circle). We observe that when the trap is at location 2 (near NWL), 1) the ACmin of 1-to-0 bitflip for double-sided RowHammer reduces by 75.5% compared to single-sided RowHammer (NWL), and 2) we do not observe double-sided RowHammer 0-to-1 bitf… view at source ↗
Figure 13
Figure 13. Figure 13: Impact of different charge trap locations on the [PITH_FULL_IMAGE:figures/full_fig_p008_13.png] view at source ↗
Figure 15
Figure 15. Figure 15: Overlap between 0-to-1 and 1-to-0 bitflip positions [PITH_FULL_IMAGE:figures/full_fig_p008_15.png] view at source ↗
Figure 17
Figure 17. Figure 17: Analysis of CC-induced leakage under double-sided [PITH_FULL_IMAGE:figures/full_fig_p009_17.png] view at source ↗
Figure 16
Figure 16. Figure 16: Interface trap regions used for simulating double [PITH_FULL_IMAGE:figures/full_fig_p009_16.png] view at source ↗
Figure 18
Figure 18. Figure 18: (a) Device schematic and bias conditions used to char [PITH_FULL_IMAGE:figures/full_fig_p011_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: Dependence of ACmin on tAggON for PWL-induced RowHammer and RowPress; trap location 4 (near PWL), 0.4eV. (a) ACmin for 1-to-0 bitflip (ACmin,1−to−0), 0-to-1 bit￾flip (ACmin,0−to−1) as a function of tAggON under a relatively low bulk h-trap density (DHT,bulk = 1.02×1016 cm−3 eV−1 ). (b) ACmin for 0-to-1 bitflip under different bulk h-trap densities (DHT,bulk). The circled data points indicate the regime wh… view at source ↗

discussion (0)

Sign in with ORCID, Apple, or X to comment. Anyone can read and Pith papers without signing in.

Reference graph

Works this paper leans on

132 extracted references · 6 linked inside Pith

  1. [1]

    Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,

    Y. Kimet al., “Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ” inISCA, 2014

    2014

  2. [2]

    Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques,

    J. S. Kimet al., “Revisiting RowHammer: An Experimental Analysis of Modern DRAM Devices and Mitigation Techniques, ” inISCA, 2020

    2020

  3. [3]

    RowPress: Amplifying Read Disturbance in Modern DRAM Chips,

    H. Luoet al., “RowPress: Amplifying Read Disturbance in Modern DRAM Chips, ” inISCA, 2023

    2023

  4. [4]

    An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips,

    H. Luoet al., “An Experimental Characterization of Combined RowHammer and RowPress Read Disturbance in Modern DRAM Chips, ” inDSN Disrupt, 2024

    2024

  5. [5]

    Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript,

    D. Grusset al., “Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript, ” inDIMV A, 2016

    2016

  6. [6]

    Exploiting Hardware Vulnerabilities to Attack Embedded System Devices: A Survey of Potent Microarchitectural Attacks,

    A. P. Fournariset al., “Exploiting Hardware Vulnerabilities to Attack Embedded System Devices: A Survey of Potent Microarchitectural Attacks, ”Electronics, 2017

    2017

  7. [7]

    Attacking Deterministic Signature Schemes using Fault Attacks,

    D. Poddebniaket al., “Attacking Deterministic Signature Schemes using Fault Attacks, ” inEuroS&P, 2018

    2018

  8. [8]

    Throwhammer: Rowhammer Attacks Over the Network and De- fenses,

    A. Tataret al., “Throwhammer: Rowhammer Attacks Over the Network and De- fenses, ” inUSENIX ATC, 2018

    2018

  9. [9]

    OpenSSL Bellcore’s Protection Helps Fault Attack,

    S. Carreet al., “OpenSSL Bellcore’s Protection Helps Fault Attack, ” inDSD, 2018

    2018

  10. [10]

    Software-Only Reverse Engineering of Physical DRAM Map- pings for Rowhammer Attacks,

    A. Barenghiet al., “Software-Only Reverse Engineering of Physical DRAM Map- pings for Rowhammer Attacks, ” inIVSW, 2018

    2018

  11. [11]

    Triggering Rowhammer Hardware Faults on ARM: A Revisit,

    Z. Zhanget al., “Triggering Rowhammer Hardware Faults on ARM: A Revisit, ” in ASHES, 2018

    2018

  12. [12]

    Advanced Fault Attacks in Software: Exploiting the Rowhammer Bug,

    S. Bhattacharya and D. Mukhopadhyay, “Advanced Fault Attacks in Software: Exploiting the Rowhammer Bug, ” inFault Tolerant Architectures for Cryptography and Hardware Security, 2018

    2018

  13. [13]

    Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges,

    M. Seaborn and T. Dullien, “Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges, ” http://googleprojectzero.blogspot.com.tr/2015/03/ exploiting-dram-rowhammer-bug-to-gain.html, 2015

    2015

  14. [14]

    RowHammer — GitHub Repository,

    SAFARI Research Group, “RowHammer — GitHub Repository, ” https://github.com/ CMU-SAFARI/rowhammer, 2014

    2014

  15. [15]

    Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges,

    M. Seaborn and T. Dullien, “Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges, ”Black Hat, 2015

    2015

  16. [16]

    Drammer: Deterministic Rowhammer Attacks on Mobile Platforms,

    V. van der Veenet al., “Drammer: Deterministic Rowhammer Attacks on Mobile Platforms, ” inCCS, 2016

    2016

  17. [17]

    Flip Feng Shui: Hammering a Needle in the Software Stack,

    K. Razaviet al., “Flip Feng Shui: Hammering a Needle in the Software Stack, ” in USENIX Security, 2016

    2016

  18. [18]

    DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks,

    P. Pesslet al., “DRAMA: Exploiting DRAM Addressing for Cross-CPU Attacks, ” in USENIX Security, 2016

    2016

  19. [19]

    One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation,

    Y. Xiaoet al., “One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation, ” inUSENIX Security, 2016

    2016

  20. [20]

    Dedup Est Machina: Memory Deduplication as An Advanced Exploitation Vector,

    E. Bosmanet al., “Dedup Est Machina: Memory Deduplication as An Advanced Exploitation Vector, ” inS&P, 2016

    2016

  21. [21]

    Curious Case of Rowhammer: Flipping Secret Exponent Bits Using Timing Analysis,

    S. Bhattacharya and D. Mukhopadhyay, “Curious Case of Rowhammer: Flipping Secret Exponent Bits Using Timing Analysis, ” inCHES, 2016

    2016

  22. [22]

    Invited: Who is the Major Threat to Tomorrow’s Security? You, the Hardware Designer,

    W. Burlesonet al., “Invited: Who is the Major Threat to Tomorrow’s Security? You, the Hardware Designer, ” inDAC, 2016

    2016

  23. [23]

    A New Approach for RowHammer Attacks,

    R. Qiao and M. Seaborn, “A New Approach for RowHammer Attacks, ” inHOST, 2016. 13

    2016

  24. [24]

    Can’t Touch This: Software-Only Mitigation Against Rowhammer Attacks Targeting Kernel Memory,

    F. Brasseret al., “Can’t Touch This: Software-Only Mitigation Against Rowhammer Attacks Targeting Kernel Memory, ” inUSENIX Security, 2017

    2017

  25. [25]

    SGX-Bomb: Locking Down the Processor via Rowhammer Attack,

    Y. Janget al., “SGX-Bomb: Locking Down the Processor via Rowhammer Attack, ” inSOSP, 2017

    2017

  26. [26]

    When Good Protections Go Bad: Exploiting Anti-DoS Measures to Accelerate Rowhammer Attacks,

    M. T. Agaet al., “When Good Protections Go Bad: Exploiting Anti-DoS Measures to Accelerate Rowhammer Attacks, ” inHOST, 2017

    2017

  27. [27]

    The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser,

    O. Mutlu, “The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser, ” inDATE, 2017

    2017

  28. [28]

    Defeating Software Mitigations Against Rowhammer: A Surgical Precision Hammer,

    A. Tataret al., “Defeating Software Mitigations Against Rowhammer: A Surgical Precision Hammer, ” inRAID, 2018

    2018

  29. [29]

    Another Flip in the Wall of Rowhammer Defenses,

    D. Grusset al., “Another Flip in the Wall of Rowhammer Defenses, ” inS&P, 2018

    2018

  30. [30]

    Nethammer: Inducing Rowhammer Faults through Network Re- quests,

    M. Lippet al., “Nethammer: Inducing Rowhammer Faults through Network Re- quests, ” inEuroS&PW, 2020

    2020

  31. [31]

    GuardION: Practical Mitigation of DMA-Based Rowhammer Attacks on ARM,

    V. van der Veenet al., “GuardION: Practical Mitigation of DMA-Based Rowhammer Attacks on ARM, ” inDIMV A, 2018

    2018

  32. [32]

    Grand Pwning Unit: Accelerating Microarchitectural Attacks with the GPU,

    P. Frigoet al., “Grand Pwning Unit: Accelerating Microarchitectural Attacks with the GPU, ” inS&P, 2018

    2018

  33. [33]

    Exploiting Correcting Codes: On the Effectiveness of ECC Memory Against Rowhammer Attacks,

    L. Cojocaret al., “Exploiting Correcting Codes: On the Effectiveness of ECC Memory Against Rowhammer Attacks, ” inS&P, 2019

    2019

  34. [34]

    Pinpoint Rowhammer: Suppressing Unwanted Bit Flips on Rowhammer Attacks,

    S. Jiet al., “Pinpoint Rowhammer: Suppressing Unwanted Bit Flips on Rowhammer Attacks, ” inASIACCS, 2019

    2019

  35. [35]

    RowHammer: A Retrospective,

    O. Mutlu and J. S. Kim, “RowHammer: A Retrospective, ”IEEE TCAD, 2020

    2020

  36. [36]

    Terminal Brain Damage: Exposing the Graceless Degradation in Deep Neural Networks Under Hardware Fault Attacks,

    S. Honget al., “Terminal Brain Damage: Exposing the Graceless Degradation in Deep Neural Networks Under Hardware Fault Attacks, ” inUSENIX Security, 2019

    2019

  37. [37]

    RAMBleed: Reading Bits in Memory Without Accessing Them,

    A. Kwonget al., “RAMBleed: Reading Bits in Memory Without Accessing Them, ” inS&P, 2020

    2020

  38. [38]

    TRRespass: Exploiting the Many Sides of Target Row Refresh,

    P. Frigoet al., “TRRespass: Exploiting the Many Sides of Target Row Refresh, ” in S&P, 2020

    2020

  39. [39]

    Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers,

    L. Cojocaret al., “Are We Susceptible to Rowhammer? An End-to-End Methodology for Cloud Providers, ” inS&P, 2020

    2020

  40. [40]

    JackHammer: Efficient Rowhammer on Heterogeneous FPGA– CPU Platforms,

    Z. Weissmanet al., “JackHammer: Efficient Rowhammer on Heterogeneous FPGA– CPU Platforms, ”IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2020, 2020

    2020

  41. [41]

    PThammer: Cross-User-Kernel-Boundary Rowhammer through Implicit Accesses,

    Z. Zhanget al., “PThammer: Cross-User-Kernel-Boundary Rowhammer through Implicit Accesses, ” inMICRO, 2020

    2020

  42. [42]

    DeepHammer: Depleting the Intelligence of Deep Neural Networks Through Targeted Chain of Bit Flips,

    F. Yaoet al., “DeepHammer: Depleting the Intelligence of Deep Neural Networks Through Targeted Chain of Bit Flips, ” inUSENIX Security, 2020

    2020

  43. [43]

    SMASH: Synchronized Many-Sided Rowhammer Attacks from JavaScript,

    F. de Ridderet al., “SMASH: Synchronized Many-Sided Rowhammer Attacks from JavaScript, ” inUSENIX Security, 2021

    2021

  44. [44]

    Uncovering in-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications,

    H. Hassanet al., “Uncovering in-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications, ” inMICRO, 2021

    2021

  45. [45]

    Blacksmith: Scalable Rowhammering in the Frequency Domain,

    P. Jattkeet al., “Blacksmith: Scalable Rowhammering in the Frequency Domain, ” in S&P, 2022

    2022

  46. [46]

    Don’t Knock! Rowhammer at the Backdoor of DNN Models,

    M. C. Tolet al., “Don’t Knock! Rowhammer at the Backdoor of DNN Models, ” in DSN, 2023

    2023

  47. [47]

    Half-Double: Hammering From the Next Row Over,

    A. Kogleret al., “Half-Double: Hammering From the Next Row Over, ” inUSENIX Security, 2022

    2022

  48. [48]

    SpyHammer: Using RowHammer to Remotely Spy on Temperature,

    L. Orosaet al., “SpyHammer: Using RowHammer to Remotely Spy on Temperature, ” arXiv:2210.04084, 2022

    Pith/arXiv arXiv 2022

  49. [49]

    Implicit Hammer: Cross-Privilege-Boundary Rowhammer through Implicit Accesses,

    Z. Zhanget al., “Implicit Hammer: Cross-Privilege-Boundary Rowhammer through Implicit Accesses, ”IEEE TDSC, 2023

    2023

  50. [50]

    Generating Robust DNN with Resistance to Bit-Flip based Adversarial Weight Attack,

    L. Liuet al., “Generating Robust DNN with Resistance to Bit-Flip based Adversarial Weight Attack, ”IEEE TC, 2023

    2023

  51. [51]

    HammerScope: Observing DRAM Power Consumption Using Rowhammer,

    Y. Cohenet al., “HammerScope: Observing DRAM Power Consumption Using Rowhammer, ” inCCS, 2022

    2022

  52. [52]

    TrojViT: Trojan Insertion in Vision Transformers,

    M. Zhenget al., “TrojViT: Trojan Insertion in Vision Transformers, ” inCVPR, 2023

    2023

  53. [53]

    When Frodo Flips: End-to-End Key Recovery on FrodoKEM via Rowhammer,

    M. Fahr, Jr.et al., “When Frodo Flips: End-to-End Key Recovery on FrodoKEM via Rowhammer, ” inCCS, 2022

    2022

  54. [54]

    SpecHammer: Combining Spectre and Rowhammer for New Speculative Attacks,

    Y. Tobahet al., “SpecHammer: Combining Spectre and Rowhammer for New Speculative Attacks, ” inS&P, 2022

    2022

  55. [55]

    DeepSteal: Advanced Model Extractions Leveraging Efficient Weight Stealing in Memories,

    A. S. Rakinet al., “DeepSteal: Advanced Model Extractions Leveraging Efficient Weight Stealing in Memories, ” inS&P, 2022

    2022

  56. [56]

    SledgeHammer: Amplifying Rowhammer via Bank-level Parallelism,

    I. Kanget al., “SledgeHammer: Amplifying Rowhammer via Bank-level Parallelism, ” inUSENIX Security, 2024

    2024

  57. [57]

    ZenHammer: Rowhammer Attacks on AMD Zen-based Platforms,

    P. Jattkeet al., “ZenHammer: Rowhammer Attacks on AMD Zen-based Platforms, ” inUSENIX Security, 2024

    2024

  58. [58]

    Rubicon: Precise Microarchitectural Attacks with Page-Granular Massaging,

    M. Bölcskeiet al., “Rubicon: Precise Microarchitectural Attacks with Page-Granular Massaging, ” inEuroS&P, 2025

    2025

  59. [59]

    Posthammer: Pervasive Browser-based Rowhammer Attacks with Postponed Refresh Commands,

    F. de Ridderet al., “Posthammer: Pervasive Browser-based Rowhammer Attacks with Postponed Refresh Commands, ” inUSENIX Security, 2025

    2025

  60. [60]

    McSee: Evaluating Advanced Rowhammer Attacks and Defenses via Automated DRAM Traffic Analysis,

    P. Jattkeet al., “McSee: Evaluating Advanced Rowhammer Attacks and Defenses via Automated DRAM Traffic Analysis, ” inUSENIX Security, 2025

    2025

  61. [61]

    Phoenix: Rowhammer Attacks on DDR5 with Self-Correcting Synchronization,

    D. Meyeret al., “Phoenix: Rowhammer Attacks on DDR5 with Self-Correcting Synchronization, ” inS&P, 2026

    2026

  62. [62]

    GPUHammer: Rowhammer Attacks on GPU Memories are Practical,

    C. S. Linet al., “GPUHammer: Rowhammer Attacks on GPU Memories are Practical, ” inUSENIX Security, 2025

    2025

  63. [63]

    GPUBreach: Privilege Escalation Attacks on GPUs using Rowham- mer,

    C. S. Linet al., “GPUBreach: Privilege Escalation Attacks on GPUs using Rowham- mer, ” inS&P, 2026

    2026

  64. [64]

    GDDRHammer: Greatly Disturbing DRAM Rows — Cross-Component Rowhammer Attacks from Modern GPUs,

    Y. Huet al., “GDDRHammer: Greatly Disturbing DRAM Rows — Cross-Component Rowhammer Attacks from Modern GPUs, ” inS&P, 2026

    2026

  65. [65]

    GeForge: Hammering GDDR Memory to Forge GPU Page Tables for Fun and Profit,

    J. Wanet al., “GeForge: Hammering GDDR Memory to Forge GPU Page Tables for Fun and Profit, ” inS&P, 2026

    2026

  66. [66]

    PRowhammer: Propagating Bit-flips from CPU to GPU,

    M. Shuklaet al., “PRowhammer: Propagating Bit-flips from CPU to GPU, ” inISCA, 2026

    2026

  67. [67]

    ρHammer: Reviving RowHammer Attacks on New Architectures via Prefetching,

    W. Chenet al., “ρHammer: Reviving RowHammer Attacks on New Architectures via Prefetching, ” inMICRO, 2025

    2025

  68. [68]

    Rowhammer-Based Trojan Injection: One Bit Flip Is Sufficient for Backdooring DNNs,

    X. Liet al., “Rowhammer-Based Trojan Injection: One Bit Flip Is Sufficient for Backdooring DNNs, ” inUSENIX Security, 2025

    2025

  69. [69]

    A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses,

    L. Orosaet al., “A Deeper Look into RowHammer’s Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses, ” inMICRO, 2021

    2021

  70. [70]

    Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices,

    A. G. Yağlıkcıet al., “Understanding RowHammer Under Reduced Wordline Voltage: An Experimental Study Using Real DRAM Devices, ” inDSN, 2022

    2022

  71. [71]

    Spatial Variation-Aware Read Disturbance Defenses: Exper- imental Analysis of Real DRAM Chips and Implications on Future Solutions,

    A. G. Yağlıkçıet al., “Spatial Variation-Aware Read Disturbance Defenses: Exper- imental Analysis of Real DRAM Chips and Implications on Future Solutions, ” in HPCA, 2024

    2024

  72. [72]

    DRAMScope: Uncovering DRAM Microarchitecture and Character- istics by Issuing Memory Commands,

    H. Namet al., “DRAMScope: Uncovering DRAM Microarchitecture and Character- istics by Issuing Memory Commands, ” inISCA, 2024

    2024

  73. [73]

    Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies,

    H. Luoet al., “Revisiting DRAM Read Disturbance: Identifying Inconsistencies Between Experimental Characterization and Device-Level Studies, ” inVTS, 2025

    2025

  74. [74]

    Overcoming the Reliability Limitation in the Ultimately Scaled DRAM using Silicon Migration Technique by Hydrogen Annealing,

    S.-W. Ryuet al., “Overcoming the Reliability Limitation in the Ultimately Scaled DRAM using Silicon Migration Technique by Hydrogen Annealing, ” inIEDM, 2017

    2017

  75. [75]

    Trap-Assisted DRAM Row Hammer Effect,

    T. Yang and X.-W. Lin, “Trap-Assisted DRAM Row Hammer Effect, ”IEEE EDL, 2019

    2019

  76. [76]

    On DRAM RowHammer and the Physics of Insecurity,

    A. J. Walkeret al., “On DRAM RowHammer and the Physics of Insecurity, ”IEEE TED, 2021

    2021

  77. [77]

    Mitigating the Passing Word Line Induced Soft Errors in Saddle Fin DRAM,

    S. K. Gautamet al., “Mitigating the Passing Word Line Induced Soft Errors in Saddle Fin DRAM, ”IEEE TED, 2020

    2020

  78. [78]

    Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation,

    L. Zhouet al., “Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation, ” inIRPS, 2023

    2023

  79. [79]

    Unveiling RowPress in Sub-20 nm DRAM Through Comparative Analysis With Row Hammer: From Leakage Mechanisms to Key Features,

    L. Zhouet al., “Unveiling RowPress in Sub-20 nm DRAM Through Comparative Analysis With Row Hammer: From Leakage Mechanisms to Key Features, ” inIEEE Transactions on Electron Devices, 2024

    2024

  80. [80]

    Understanding the Physical Mechanism of RowPress at the Device- Level in Sub-20 nm DRAM,

    L. Zhouet al., “Understanding the Physical Mechanism of RowPress at the Device- Level in Sub-20 nm DRAM, ” inIRPS, 2024

    2024

Showing first 80 references.