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REVIEW 2 major objections 6 minor 61 references

This paper claims that magic-state supply, placement, routing, and layout pruning form one co-optimization problem, and that Harvest solves it with a protocol-agnostic resource model.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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Harvest co-optimizes placement, routing, scheduling, and magic-state supply for lattice-surgery quantum programs, reporting up to 17.8x speedup over sequential execution and reclaiming up to 72% of unused magic-state patches.

T0 review reviewed 2026-08-05 challenge →

load-bearing objection A genuinely integrated lattice-surgery compiler with a clean problem formulation, but the headline speedup is inflated by a sequential baseline that ignores magic-state latency, so the quantitative claims need re-benchmarking. the 2 major comments →

arxiv 2608.03315 v1 pith:ZU6YQ7YK submitted 2026-08-04 quant-ph

Harvest: Resource-Aware Quantum Compilation for Magic State Protocols

Jannik Pflieger , Aleksandra \'Swierkowska , Emmanouil Giortamis , Pramod Bhatotia This is my paper
classification quant-ph MSC 81P6868M20
keywords lattice surgerymagic statesquantum compilationresource-constrained schedulingsurface codeslayout pruningfault-tolerant quantum computing
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Harvest is a compiler for fault-tolerant quantum programs that run on topological codes via lattice surgery. The paper argues that magic-state supply, qubit placement, routing, and scheduling must be decided together, because operations independent at the circuit level can still collide on ports, routes, or magic-state terminals. It presents a patch-level pipeline that represents magic-state generation as a configurable resource model, schedules operations timestep by timestep under routing and availability constraints, then removes unused layout resources. On benchmark circuits the paper reports an average 4.83x speedup over sequential execution, up to 1.35x from circuit-aware placement, and up to 72% of unused magic-state patches reclaimed.

Core claim

The central claim is that lattice-surgery code generation can be treated as resource-constrained scheduling over explicit patch-level resources, making the time-footprint trade-off tractable across magic-state protocols. In Harvest's model, each Pauli-product operation is a spatial request for data-patch ports, a route through routing patches, and, for non-Clifford terms, a magic-state terminal; a schedule is valid only when dependencies hold, concurrent operations reserve disjoint resources, and every consumed magic state is available at its location and time. The pipeline lowers input circuits into a dependency DAG of Pauli-product operations, constructs a layout graph with circuit-aware p

What carries the argument

The load-bearing object is the resource model around H-IR: a layout graph $G_L$ whose nodes are data-patch ports, routing patches, and magic-state terminals, together with a magic-state availability relation $M \subseteq V_M \times \mathbb{N}_{\geq 0}$ saying when and where a non-Clifford state can be consumed. Around it, the scheduler's timestep construction treats each logical timestep as a temporary resource-allocation problem: it selects ready operations, assigns compatible ports and terminals, routes each as an approximate Steiner tree, measures contention $\Phi_t = \sum_r \max(0, \rho_t(r) - c(r))$, and reroutes against a congestion-plus-history cost $w_t(r) = \$\alpha$\,\rho_t(r)/c(r) +

Load-bearing premise

The reported speedups all compare against a sequential baseline that executes Pauli-products in dependency order without modeling magic-state preparation latency or routing conflicts; if that baseline is not a physically valid schedule, the speedup numbers are inflated.

What would settle it

Re-run the benchmark comparison with a serial baseline that pays magic-state preparation latency ($\mu$) and serializes operations whose routes or terminals overlap; if the average speedup falls well below $4.83\times$, the headline result depends on an unrealistic baseline. On small instances, compare Harvest's schedule length to an exhaustive search over valid schedules to test the heuristic's optimality gap.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • A single compiler pipeline can target both distillation and cultivation without scheduler rewrites, because protocol differences reduce to when and where magic states become available.
  • Realizable parallelism is close to the DAG-only bound for most workloads: QFT reaches 96% of that bound, Small 90%, and QAOA 87%.
  • Layouts can be provisioned conservatively for scheduling and then reported at their realized footprint: up to 72.0% of magic-state patches and 33.9% of routing patches are reclaimed in the Small family.
  • Magic-state capacity planning has measurable saturation points: with preparation latency $\mu = 4$, QAOA saturates around 24 patches and QFT around 48, while Ising remains supply-limited even at 64 patches.
  • Placement and scheduling interact: circuit-aware placement improves schedule length by up to 1.35x when routing congestion sets the critical path, but can slightly degrade other circuits.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Because the resource model is protocol-agnostic, the same scheduling core could plausibly model other location-and-time-constrained resources, such as factory outputs with staggered readiness or time-shared routing corridors.
  • The reported speedup should be read as against dependency-ordered serial execution, not a physically realized serial schedule; a baseline that pays magic-state preparation latency and resource conflicts would set a higher bar.
  • Pruned layouts are schedule-specific rather than minimal, so combining pruning with relayout or iterative recompilation could reduce footprint further; the paper does not claim the pruned layout is globally minimum.
  • The circuit-dependent placement results suggest a predictor of routing-limited critical paths could make circuit-aware placement conditional, avoiding the observed regressions.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 6 minor

Summary. Harvest is a resource-aware compilation pipeline for logical-level lattice surgery. It lowers circuits into Pauli-product DAGs, constructs a layout graph using circuit-aware placement, and schedules operations under dependency, routing, and magic-state availability constraints via a conflict-aware timestep construction (Algorithm 1). A post-scheduling pruner removes unused routing and magic-state patches. The central claims are a 4.83× average speedup (up to 17.8×) over sequential execution, up to 1.35× schedule-length improvement from circuit-aware placement, and up to 72.0% magic-state / 33.9% routing-patch pruning. The evaluation covers QAOA, QFT, Feynman, Square-Heisenberg, and QASMBench families.

Significance. If the reported speedups withstand scrutiny, Harvest is a useful integrated compiler: it makes all resource decisions explicit in H-IR, models magic-state generation as a configurable availability model rather than hard-coding one protocol, and honestly documents that placement is a heuristic and that pruned layouts are schedule-specific rather than globally minimal. The strongest quantitative claims, however, rest on the fairness of the sequential baseline, whose treatment of magic-state preparation latency is unspecified. The evaluation also does not compare against the closest existing resource-aware schedulers identified in the related work. The architecture and ablation breakdown are valuable, but the magnitude of the headline benefit needs re-baselining before it can be accepted as reported.

major comments (2)
  1. [§IX-A (Metrics and Baselines), Fig. 9] The speedup S = sequential_timesteps / scheduled_timesteps is only meaningful if the sequential baseline is a physically realizable schedule under the same magic-state resource model M defined in §IV-C. The baseline is described only as 'runs the Pauli-product operations in dependency order'; there is no statement that it advances M, waits μ timesteps for preparation, or resolves terminal/routing conflicts, whereas Harvest's own scheduler explicitly blocks on magic-state availability (§VII). If the baseline charges one timestep per dependency-ordered Pauli product, the 4.83×/17.8× speedups in the abstract and Fig. 9 are inflated by an incomplete denominator. Please specify the baseline's magic-state handling and re-evaluate against a sequential schedule that respects M; at minimum, report both variants.
  2. [§IX-A, §X (Table III)] The only comparators in the evaluation are the custom sequential and DAG-only baselines. The related-work section identifies Pure Magic [14], DASCOT [42], multi-qubit lattice surgery scheduling [21], and LSQCA [20] as the closest resource-aware systems, but no benchmark-level comparison is attempted. Without such a comparison — or a concrete statement of why input formats make it infeasible — the paper does not establish that Harvest improves on prior resource-aware schedulers; it only establishes an improvement over serial execution. A comparison on a common subset, e.g., the QAOA/QFT benchmarks, would substantially strengthen the evaluation.
minor comments (6)
  1. [Fig. 1 vs. Abstract/§IX-B] Fig. 1 reports an average speedup of 5.38×, while the abstract and §IX-B report 4.83×. Please clarify which experiment each number refers to or correct the inconsistency.
  2. [Table II, §IX-A, Fig. 12(c)] The benchmark list in §IX-A includes a 'Clifford' family and Fig. 12(c) plots 'Clifford', but Table II has no Clifford row. Add the missing row or remove the family.
  3. [§IX-A] The statement that all variants use the 'same ... magic-state configuration' is ambiguous. Define whether this includes identical availability times under M and whether the sequential baseline waits for magic-state preparation.
  4. [§VII] Report concrete values or ranges for the free parameters α, β, the rerouting budget, the latency bounds μ/μ_min/μ_max, and the layout-template filling ratios. Without these values the reported results are not reproducible.
  5. [§VI] The placement objective C(π) uses a distance d(p_a, p_b) that is never defined. State explicitly whether this is Manhattan distance on the patch grid.
  6. [§IX-A] The DAG-only baseline is described as an 'optimistic upper bound.' Since it ignores resource conflicts, it gives a lower bound on achievable schedule length (or an upper bound on parallelism), not an upper bound on timesteps. Suggest rewording to 'optimistic DAG-parallelism bound.'

Circularity Check

0 steps flagged

No significant circularity; Harvest is an empirical compiler evaluation with external benchmarks and no fitted-parameter predictions.

full rationale

The paper's central claims are measured outputs of an implemented scheduler against defined baselines, not quantities derived from fitted parameters or from self-citations. The speedup metric S = sequential_timesteps / scheduled_timesteps compares a dependency-ordered serial execution with Harvest's resource-aware schedule; the schedule length is produced by the routing/scheduling algorithm, not re-fit from the baseline. Circuit-aware placement uses an interaction-weight objective only as a heuristic ('we use this objective as a heuristic guide rather than solving the assignment problem optimally', §VI), and the reported up-to-1.35× placement speedup is an independent schedule-length comparison between row-major and circuit-aware placement. The pruning result is an accounting of resources referenced by the final schedule relative to a deliberately conservative initial layout; it is a measurement of over-provisioning, not a prediction entailed by the pruning rule. The magic-state model M is an input interface, and protocol comparisons vary M and report schedule outcomes. There are no load-bearing self-citations and no uniqueness arguments imported from the authors' prior work. The paper also explicitly acknowledges that the pruned footprint is schedule-specific and not globally minimal (§VIII), and that placement does not by itself determine the final schedule. Concerns about the sequential baseline omitting magic-state preparation latency are evaluation-fairness issues, not circularity, because the baseline is a reference point rather than an input that is re-derived as the claimed result.

Axiom & Free-Parameter Ledger

4 free parameters · 4 axioms · 0 invented entities

The central claim rests on the lattice-surgery abstraction (borrowed from prior work), the unit-capacity routing model, and a simplified magic-state availability interface. The compiler pipeline and H-IR are new software artifacts, not physical postulates. The headline evaluation additionally depends on an unvalidated sequential baseline, listed as an axiom/ad hoc assumption.

free parameters (4)
  • Magic-state preparation latency μ = 4 and 10 in experiments
    Configures the availability model; schedule length and saturation measurements depend on it (§IX-B).
  • Routing cost weights α, β = not reported
    Used in w_t(r) = α ρ_t(r)/c(r) + β h_t(r) during congestion negotiation; values are never given (§VII).
  • Rerouting budget = not reported
    Algorithm 1 reroutes only while the budget remains; the budget is not specified, affecting which operations get deferred (§VII).
  • Initial layout template filling ratio = 1/4, 1/9, 2/3
    The chosen layout template determines how many routing and magic-state patches are provisioned, and therefore the pruning percentages (§IX-D).
axioms (4)
  • domain assumption Surface-code patches realize Pauli-product measurements in one logical timestep with data, routing, and magic-state roles.
    Used throughout §II-A/B and §V; inherited from Litinski's model [10].
  • domain assumption Routing resources have unit capacity, and a timestep is conflict-free iff Φ_t=0.
    Stated in §VII: 'In our patch-level model, routing resources have unit capacity.'
  • domain assumption Magic-state generation can be abstracted as availability pairs M ⊆ V_M × N≥0, with distillation using fixed latency μ and cultivation a bounded range.
    Defined in §IV-C and used by the scheduler in §VII; abstracts away protocol-specific spatial constraints.
  • ad hoc to paper Sequential dependency-order execution without magic-state or routing constraints is a valid speedup baseline.
    Used for the headline speedup in §IX-A/B; this assumption is questionable because it ignores resource availability.

reviewed 2026-08-05 · how reviews work

0 comments
Cite this review

Pith. "Pith review of Harvest: Resource-Aware Quantum Compilation for Magic State Protocols." pith.science (2026). https://pith.science/paper/ZU6YQ7YK

@misc{pith2026260803315,
  author       = {Pith},
  title        = {Pith review of: Harvest: Resource-Aware Quantum Compilation for Magic State Protocols},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/ZU6YQ7YK}},
  note         = {Machine review of arXiv:2608.03315}
}
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abstract

Fault-tolerant quantum processors based on topological codes execute programs through lattice surgery, where operations must be mapped, routed, and supplied with magic states across a 2D grid of physical patches. Non-Clifford operations require these magic states, produced either by distillation factories or by cultivation, each trading footprint against preparation latency, and delivering a magic state to the data patches that consume it requires routing through the same shared layout as every other operation. Yet placement, routing, scheduling, and magic-state supply cannot be optimized in isolation: two operations with no circuit-level dependency can still contend for the same ports, routes, or magic-state terminals once placed, so a compiler that decouples instruction scheduling from magic-state generation, or hard-codes a single generation protocol, is forced to trade execution time against layout footprint instead of co-optimizing both across protocols. We present Harvest, a resource-aware compilation approach for lattice-surgery that co-optimizes magic-state consumption with circuit-aware placement and congestion-aware routing under a protocol-agnostic resource model, then reclaims unused layout footprint after scheduling. Across standard benchmark suites (QAOA, QFT, QASMBench), Harvest achieves an average speedup of $4.83\times$ (up to $17.8\times$) over sequential execution, improves schedule length by up to $1.35\times$ through circuit-aware placement, and reclaims up to $72.0\%$ of unused magic-state patches and $33.9\%$ of unused routing patches.

Figures

Figures reproduced from arXiv: 2608.03315 by Aleksandra \'Swierkowska, Emmanouil Giortamis, Jannik Pflieger, Pramod Bhatotia.

Figure 1
Figure 1. Figure 1: Number of timesteps with and without magic state [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Patch-level execution model (§II-A). (a) A physical surface-code patch is abstracted into a data, routing, or magic-state patch on a lattice-surgery layout. (b) Layout templates with different data-patch fillings. dependency-aware Pauli-product representation, uses a circuit￾aware layout constructor to place logical qubits and allocate routing and magic-state patches, a routing-aware scheduler to assign op… view at source ↗
Figure 3
Figure 3. Figure 3: Resource-aware compilation motivation (§II-D). [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Three effects motivating resource-aware lattice-surgery compilation (§III). [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Harvest architecture (§IV-A). Harvest sits between circuit-level frontends and lower-level lattice-surgery backends. It lowers input circuits to Pauli-product operations, constructs a logical lattice-surgery layout, schedules operations under routing and magic-state constraints, prunes unused auxiliary resources, and emits H-IR as a routed patch-level program. layout constructor builds it in three steps: l… view at source ↗
Figure 6
Figure 6. Figure 6: Transformation workflows (§VI). (a) The circuit transformer turns a quantum circuit into the circuit operation DAG GO. (b) The layout constructor builds the layout graph GL. TABLE I: Simplified schedule entry example in H-IR (§V). Field Value Timestep 0 Qubit indices [0] Magic terminal P:mL2:M_E:M Qubit ports P:q_0:W:Z Routing cells (1, 2) Port nodes P:mL2:M_E:M, P:q_0:W:Z connected by dependency edges inh… view at source ↗
Figure 7
Figure 7. Figure 7: Qubit placement (§VI). Row-major placement fol￾lows layout order, while circuit-aware placement uses the qubit interaction graph to improve locality between fre￾quently interacting qubits. placement gives the scheduler a better starting point without attempting to predict the complete execution. Layout-graph construction [PITH_FULL_IMAGE:figures/full_fig_p007_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Scheduling (§VII) and layout pruning (§VIII) workflow. [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: End-to-End performance (§IX-B). (a) Speedup over sequential execution per benchmark circuit. (b) Average logical timesteps with and without scheduling. (c) Average speedup by circuit family and distance to ideal DAG parallelism. TABLE II: Benchmark dataset. Summary of the circuit families, number of circuits, logical-qubit range, and range of transformed Pauli product operations. Family #Circuits #Qubits #… view at source ↗
Figure 10
Figure 10. Figure 10: Magic-state availability (§IX-B). Average speedup for 25–31-qubit Ising, QAOA, and QFT circuits on a shared layout under distillation and cultivation (µ = 4, 10). Methodology. We compare Harvest against a sequential base￾line. The baseline executes the transformed Pauli-product operations one after another in dependency order. Harvest uses the same transformed circuit, layout, placement, and magic￾state c… view at source ↗
Figure 11
Figure 11. Figure 11: Placement effectiveness (§IX-C). (a) Placement speedup of circuit-aware placement over row-major placement for different layout templates under Harvest scheduling. Values above one indicate that circuit-aware placement reduces the number of logical timesteps. (b) and (c) per-circuit change in speedup for Large and Medium benchmarks, respectively. Takeaway #2: Harvest benefits every benchmark fam￾ily, achi… view at source ↗
Figure 12
Figure 12. Figure 12: Resource efficiency (§IX-D). (a) Patch reduction by layout template and resource type; (b) percentage of removed patches relative to the initial layout as circuit size changes; and (c) patch reduction by circuit family. are larger. In relative terms, the largest reductions occur for smaller circuits, where the initial layout often contains more routing resources than the final schedule needs [PITH_FULL_I… view at source ↗

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Reference graph

Works this paper leans on

61 extracted references · 22 canonical work pages · 10 internal anchors

  1. [1]

    Scheme for reducing decoherence in quantum computer memory,

    P. W. Shor, “Scheme for reducing decoherence in quantum computer memory,”Physical Review A, vol. 52, no. 4, pp. R2493–R2496, 1995

    work page 1995

  2. [2]

    Fault-tolerant quantum computation with constant error rate,

    D. Aharonov and M. Ben-Or, “Fault-tolerant quantum computation with constant error rate,”SIAM Journal on Computing, vol. 38, no. 4, pp. 1207–1282, 2008

    work page 2008

  3. [3]

    Theory of fault-tolerant quantum computation,

    D. Gottesman, “Theory of fault-tolerant quantum computation,”Phys. Rev. A, vol. 57, pp. 127–137, Jan 1998. [Online]. Available: https://doi.org/10.1103/PhysRevA.57.127

    doi:10.1103/physreva.57.127 1998

  4. [4]

    An introduction to quantum error correction and fault-tolerant quantum computation,

    ——, “An introduction to quantum error correction and fault-tolerant quantum computation,”arXiv preprint arXiv:0904.2557, 2009

    Pith/arXiv arXiv 2009

  5. [5]

    Quantum error correction for quantum memories,

    B. M. Terhal, “Quantum error correction for quantum memories,”Rev. Mod. Phys., vol. 87, pp. 307–346, Apr 2015. [Online]. Available: https://doi.org/10.1103/RevModPhys.87.307

    doi:10.1103/revmodphys.87.307 2015

  6. [6]

    M. A. Nielsen and I. L. Chuang,Quantum Computation and Quantum Information: 10th Anniversary Edition. Cambridge University Press, 2010

    2010

  7. [7]

    Topological quantum memory,

    E. Dennis, A. Kitaev, A. Landahl, and J. Preskill, “Topological quantum memory,”Journal of Mathematical Physics, vol. 43, no. 9, pp. 4452– 4505, 2002

    2002

  8. [8]

    Surface codes: Towards practical large-scale quantum computation,

    A. G. Fowler, M. Mariantoni, J. M. Martinis, and A. N. Cleland, “Surface codes: Towards practical large-scale quantum computation,” Physical Review A, vol. 86, no. 3, Sep. 2012. [Online]. Available: http://dx.doi.org/10.1103/PhysRevA.86.032324

    doi:10.1103/physreva.86.032324 2012

  9. [9]

    Surface code quantum computing by lattice surgery,

    C. Horsman, A. G. Fowler, S. Devitt, and R. Van Meter, “Surface code quantum computing by lattice surgery,”New Journal of Physics, vol. 14, no. 12, p. 123011, 2012

    work page 2012

  10. [10]

    A game of surface codes: Large-scale quantum computing with lattice surgery,

    D. Litinski, “A game of surface codes: Large-scale quantum computing with lattice surgery,”Quantum, vol. 3, p. 128, 2019. [Online]. Available: http://arxiv.org/abs/1808.02892

    Pith/arXiv arXiv 2019

  11. [11]

    Universal quantum computation with ideal clifford gates and noisy ancillas,

    S. Bravyi and A. Kitaev, “Universal quantum computation with ideal clifford gates and noisy ancillas,”Physical Review A, vol. 71, no. 2, Feb. 2005. [Online]. Available: http://dx.doi.org/10.1103/PhysRevA.71. 022316

    doi:10.1103/physreva.71 2005

  12. [12]

    Magic-state distillation with low overhead,

    S. Bravyi and J. Haah, “Magic-state distillation with low overhead,” Physical Review A, vol. 86, no. 5, Nov. 2012. [Online]. Available: http://dx.doi.org/10.1103/PhysRevA.86.052329

    doi:10.1103/physreva.86.052329 2012

  13. [13]

    Magic state cultivation: growing t states as cheap as cnot gates,

    C. Gidney, N. Shutty, and C. Jones, “Magic state cultivation: growing t states as cheap as cnot gates,” 2024. [Online]. Available: https://arxiv.org/abs/2409.17595

    Pith/arXiv arXiv 2024

  14. [14]

    PureMagic: A Dynamic Scheduler for Lattice Surgery

    S. Hofmeyr, M. Weiden, J. Kalloor, J. Kubiatowicz, and C. Iancu, “Scheduling lattice surgery with magic state cultivation,” 2025. [Online]. Available: http://arxiv.org/abs/2512.06484

    work page internal anchor Pith review Pith/arXiv arXiv 2025

  15. [15]

    Opensurgery for topological assemblies,

    A. Paler and A. G. Fowler, “Opensurgery for topological assemblies,”

    work page

  16. [16]

    SurfBraid: A concept tool for preparing and resource estimating quantum circuits protected by the surface code

    A. Paler, “Surfbraid: A concept tool for preparing and resource estimating quantum circuits protected by the surface code,” 2019. [Online]. Available: https://arxiv.org/abs/1902.02417

    work page internal anchor Pith review Pith/arXiv arXiv 2019

  17. [17]

    Afs: Accurate, fast, and scalable error-decoding for fault-tolerant quantum computers,

    P. Das, C. A. Pattison, S. Manne, D. M. Carmean, K. M. Svore, M. K. Qureshi, and N. Delfosse, “Afs: Accurate, fast, and scalable error-decoding for fault-tolerant quantum computers,” in 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, 2022, pp. 259–273. [Online]. Available: https://doi.org/10.1109/HPCA53966.2022.00027

    arXiv 2022

  18. [18]

    Impacts of decoder latency on utility- scale quantum computer architectures,

    A. Khalid, A. Silva, G. A. Dagnew, T. Dvir, O. Wertheim, M. Gruda, X. Kong, M. Kramer, Z. Webb, A. Scherer, M. Mohseni, Y . Cohen, and P. Ronagh, “Impacts of decoder latency on utility- scale quantum computer architectures,” 2025. [Online]. Available: https://arxiv.org/abs/2511.10633

    arXiv 2025

  19. [19]

    Optimization of lattice surgery is np-hard,

    D. Herr, F. Nori, and S. J. Devitt, “Optimization of lattice surgery is np-hard,”npj Quantum Information, vol. 3, no. 1, Sep. 2017. [Online]. Available: http://dx.doi.org/10.1038/s41534-017-0035-1

    doi:10.1038/s41534-017-0035-1 2017

  20. [20]

    LSQCA: Resource-efficient load/store architecture for limited-scale fault-tolerant quantum computing,

    T. Kobori, Y . Suzuki, Y . Ueno, T. Tanimoto, S. Todo, and Y . Tokunaga, “LSQCA: Resource-efficient load/store architecture for limited-scale fault-tolerant quantum computing,” in2025 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2025, pp. 304–320. [Online]. Available: http://arxiv.org/abs/2412.20486

    Pith/arXiv arXiv 2025

  21. [21]

    Multi-qubit Lattice Surgery Scheduling

    A. Silva, X. Zhang, Z. Webb, M. Kramer, C. W. Yang, X. Liu, J. Lemieux, K.-W. Chen, A. Scherer, and P. Ronagh, “Multi-qubit lattice surgery scheduling,”LIPIcs, Volume 310, TQC 2024, vol. 310, pp. 1:1–1:22, 2024. [Online]. Available: http://arxiv.org/abs/2405.17688

    work page internal anchor Pith review Pith/arXiv arXiv 2024

  22. [22]

    Open quantum assembly language,

    A. W. Cross, L. S. Bishop, J. A. Smolin, and J. M. Gambetta, “Open quantum assembly language,” 2017. [Online]. Available: https://arxiv.org/abs/1707.03429

    Pith/arXiv arXiv 2017

  23. [23]

    OpenQASM 3: A broader and deeper quantum assembly language,

    A. W. Cross, A. Javadi-Abhari, T. Alexander, N. de Beaudrap, L. S. Bishop, S. Heidel, C. A. Ryan, P. Sivarajah, J. Smolin, J. M. Gambetta, and B. R. Johnson, “OpenQASM 3: A broader and deeper quantum assembly language,”ACM Transactions on Quantum Computing, vol. 3, no. 3, pp. 1–50, 2022

    2022

  24. [24]

    Qasmbench: A low-level qasm benchmark suite for nisq evaluation and simulation,

    A. Li, S. Stein, S. Krishnamoorthy, and J. Ang, “Qasmbench: A low-level qasm benchmark suite for nisq evaluation and simulation,”

  25. [25]

    Quantum error correction below the surface code threshold,

    R. Acharya, I. Aleiner, T. I. Andersen, M. Ansmann, F. Arute, and Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,”Nature, vol. 638, no. 8052, pp. 920–926, Feb 2025. [Online]. Available: https://doi.org/10.1038/s41586- 024-08449-y

    doi:10.1038/s41586- 2025

  26. [26]

    Efficient magic state factories with a catalyzed|CCZ⟩to2|T⟩transformation,

    C. Gidney and A. G. Fowler, “Efficient magic state factories with a catalyzed|CCZ⟩to2|T⟩transformation,”Quantum, vol. 3, p. 135, Apr

    work page

  27. [27]

    Topological quantum distillation,

    H. Bombin and M. A. Martin-Delgado, “Topological quantum distillation,”Physical Review Letters, vol. 97, no. 18, Oct. 2006. [Online]. Available: https://doi.org/10.1103/PhysRevLett.97.180501

    doi:10.1103/physrevlett.97.180501 2006

  28. [28]

    Improved simulation of stabilizer circuits,

    S. Aaronson and D. Gottesman, “Improved simulation of stabilizer circuits,”arXiv preprint quant-ph/0406196, 2004

    Pith/arXiv arXiv 2004

  29. [29]

    Mlir: A compiler infrastructure for the end of moore’s law,

    C. Lattner, M. Amini, U. Bondhugula, A. Cohen, A. Davis, J. Pienaar, R. Riddle, T. Shpeisman, N. Vasilache, and O. Zinenko, “Mlir: A compiler infrastructure for the end of moore’s law,” 2020

    work page 2020

  30. [30]

    Sparse Blossom: correcting a million errors per core second with minimum-weight matching,

    O. Higgott and C. Gidney, “Sparse Blossom: correcting a million errors per core second with minimum-weight matching,”Quantum, vol. 9, p. 1600, 2025. [Online]. Available: https://doi.org/10.22331/q-2025-01- 20-1600

    work page doi:10.22331/q-2025-01- 2025

  31. [31]

    Scalable surface-code decoders with parallelization in time,

    X. Tan, F. Zhang, R. Chao, Y . Shi, and J. Chen, “Scalable surface-code decoders with parallelization in time,”PRX Quantum, vol. 4, p. 040344, Dec 2023. [Online]. Available: https://doi.org/10.1103/PRXQuantum.4. 040344

    doi:10.1103/prxquantum.4 2023

  32. [33]

    Generating compilers for qubit mapping and routing,

    A. Molavi, A. Xu, E. Cecchetti, S. Tannu, and A. Albarghouthi, “Generating compilers for qubit mapping and routing,”Proc. ACM Program. Lang., vol. 10, no. POPL, Jan. 2026. [Online]. Available: https://doi.org/10.1145/3776720

    work page doi:10.1145/3776720 2026

  33. [34]

    Paulihedral: A generalized block-wise compiler optimization framework for quantum simulation kernels,

    G. Li, A. Wu, Y . Shi, A. Javadi-Abhari, Y . Ding, and Y . Xie, “Paulihedral: A generalized block-wise compiler optimization framework for quantum simulation kernels,” inProceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems. ACM, 2022, pp. 554–569. [Online]. Available: https://doi.org...

    arXiv 2022

  34. [35]

    Tackling the qubit mapping problem for nisq-era quantum devices,

    G. Li, Y . Ding, and Y . Xie, “Tackling the qubit mapping problem for nisq-era quantum devices,” inProceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS ’19. New York, NY , USA: Association for Computing Machinery, 2019, pp. 1001–1014. [Online]. Available: https://do...

    arXiv 2019

  35. [36]

    Lightsabre: A lightweight and enhanced sabre algorithm,

    H. Zou, M. Treinish, K. Hartman, A. Ivrii, and J. Lishman, “Lightsabre: A lightweight and enhanced sabre algorithm,” 2024. [Online]. Available: https://doi.org/10.48550/arXiv.2409.08368

    Pith/arXiv arXiv doi:10.48550/arxiv.2409.08368 2024

  36. [37]

    Effective and efficient parallel qubit mapper,

    H. Fu, M. Zhu, F. Chen, C. Zhang, J. Wu, W. Xie, and X.-Y . Li, “Effective and efficient parallel qubit mapper,”IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 44, no. 5, pp. 1774–1787, May 2025. [Online]. Available: https://doi.org/10.1109/TCAD.2024.3500784

    work page arXiv 2025

  37. [38]

    Route-forcing: Scalable quantum circuit mapping for scalable quantum computing architectures,

    P. Escofet, A. Gonzalvo, E. Alarc ´on, C. G. Almud ´ever, and S. Abadal, “Route-forcing: Scalable quantum circuit mapping for scalable quantum computing architectures,” in2024 IEEE International Conference on Quantum Computing and Engineering (QCE), vol. 01, 2024, pp. 909–

    work page 2024

  38. [39]

    A high performance compiler for very large scale surface code computations,

    G. Watkins, H. M. Nguyen, K. Watkins, S. Pearce, H.-K. Lau, and A. Paler, “A high performance compiler for very large scale surface code computations,”Quantum, vol. 8, p. 1354, 2024

    2024

  39. [40]

    Realistic Cost to Execute Practical Quantum Circuits using Direct Clifford+T Lattice Surgery Compilation

    T. LeBlond, C. Dean, G. Watkins, and R. S. Bennink, “Realistic cost to execute practical quantum circuits using direct clifford+t lattice surgery compilation,”ACM Transactions on Quantum Computing, vol. 5, no. 4, pp. 1–28, 2024. [Online]. Available: http://arxiv.org/abs/2311.10686

    work page internal anchor Pith review Pith/arXiv arXiv 2024

  40. [41]

    Lattice surgery compilation beyond the surface code,

    L. S. Herzog, L. Berent, A. Kubica, and R. Wille, “Lattice surgery compilation beyond the surface code,” 2025. [Online]. Available: https://arxiv.org/abs/2504.10591

    arXiv 2025

  41. [42]

    Dependency- aware compilation for surface code quantum architectures,

    A. Molavi, A. Xu, S. S. Tannu, and A. Albarghouthi, “Dependency- aware compilation for surface code quantum architectures,”Proceedings of the ACM on Programming Languages, 2025

    work page 2025

  42. [43]

    Ecmas: Efficient Circuit Mapping and Scheduling for Surface Code

    M. Zhu, H. Fu, J. Wu, C. Zhang, W. Xie, and X.-Y . Li, “Ecmas: Efficient circuit mapping and scheduling for surface code,” 2023. [Online]. Available: https://arxiv.org/abs/2312.15254

    work page internal anchor Pith review Pith/arXiv arXiv 2023

  43. [44]

    A sat scalpel for lattice surgery: Representation and synthesis of subroutines for surface-code fault-tolerant quantum computing,

    D. B. Tan, M. Y . Niu, and C. Gidney, “A sat scalpel for lattice surgery: Representation and synthesis of subroutines for surface-code fault-tolerant quantum computing,” in2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA). IEEE, Jun. 2024, p. 325–339. [Online]. Available: http: //dx.doi.org/10.1109/ISCA59077.2024.00032

    arXiv 2024

  44. [45]

    Topols: Lattice surgery compilation via topological program transformations,

    J. Zhou, Y . Liu, E. Decker, J. Kalloor, M. Weiden, K. Chen, C. Iancu, and G. Li, “Topols: Lattice surgery compilation via topological program transformations,” 2026. [Online]. Available: https://arxiv.org/abs/2601.23109

    arXiv 2026

  45. [46]

    C-Phase-Aware Compilation for Efficient Fault-Tolerant Quantum Execution

    D. Bharadwaj, S. Dangwal, Y . Hou, and G. S. Ravi, “C-phase-aware compilation for efficient fault-tolerant quantum execution,” 2026. [Online]. Available: https://arxiv.org/abs/2605.14042

    work page internal anchor Pith review Pith/arXiv arXiv 2026

  46. [47]

    Using azure quantum resource estimator for assessing performance of fault tolerant quantum computation,

    W. van Dam, M. Mykhailova, and M. Soeken, “Using azure quantum resource estimator for assessing performance of fault tolerant quantum computation,” 2024. [Online]. Available: https: //arxiv.org/abs/2311.05801

    Pith/arXiv arXiv 2024

  47. [48]

    Co-designed superconducting architecture for lattice surgery of surface codes with quantum interface routing card,

    C. Guinn, S. Stein, E. Tureci, G. Avis, C. Liu, S. Krastanov, A. A. Houck, and A. Li, “Co-designed superconducting architecture for lattice surgery of surface codes with quantum interface routing card,” 2023. [Online]. Available: https://arxiv.org/abs/2312.01246

    Pith/arXiv arXiv 2023

  48. [49]

    tqec: A python package for topological quantum error correction,

    A. Suau, Y . Zhang, P. Thakre, Y . Zhao, K. Dubey, J. A. Bolanos, A. Schelpe, T. Hao, P. Seitz, G. G. Guerreschi, ´A. E. ´A. P ´erez, R. Stahn, J. Lenssen, B. Reid, and A. Fowler, “tqec: A python package for topological quantum error correction,”Journal of Open Source Software, vol. 11, no. 120, p. 9142, 2026. [Online]. Available: https://doi.org/10.21105...

    doi:10.21105/joss.09142 2026

  49. [50]

    Magic-state distillation with the four-qubit code,

    A. M. Meier, B. Eastin, and E. Knill, “Magic-state distillation with the four-qubit code,” 2012. [Online]. Available: https://arxiv.org/abs/1204. 4221

    work page 2012

  50. [51]

    Linear-Time T-Gate Optimization via Random Abstraction

    A. Albarghouthi, “Linear-time t-gate optimization via random abstraction,” 2026. [Online]. Available: https://arxiv.org/abs/2605.13929

    work page internal anchor Pith review Pith/arXiv arXiv 2026

  51. [52]

    Reducing t gates with unitary synthesis,

    T. Hao, A. Xu, and S. Tannu, “Reducing t gates with unitary synthesis,” inProceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2. ACM, Mar. 2026, p. 1589–1604. [Online]. Available: http://dx.doi.org/10.1145/3779212.3790210

    arXiv 2026

  52. [53]

    Price and Payoff: Non-Determinism in Fault Tolerant Quantum Computation

    A. Awasthi, S. Sethi, S. Khan, G. S. Ravi, and J. M. Baker, “Price and payoff: Non-determinism in fault tolerant quantum computation,” 2026. [Online]. Available: https://arxiv.org/abs/2605.07983

    work page internal anchor Pith review Pith/arXiv arXiv 2026

  53. [54]

    Very low overhead fault-tolerant magic state preparation using redundant ancilla encoding and flag qubits,

    C. Chamberland and K. Noh, “Very low overhead fault-tolerant magic state preparation using redundant ancilla encoding and flag qubits,”npj Quantum Information, vol. 6, no. 1, Oct. 2020. [Online]. Available: http://dx.doi.org/10.1038/s41534-020-00319-5

    doi:10.1038/s41534-020-00319-5 2020

  54. [55]

    Logical Magic State Preparation with Fidelity Beyond the Distillation Threshold on a Superconducting Quantum Processor

    Y . Ye, T. He, H.-L. Huang, Z. Wei, Y . Zhang, Y . Zhao, D. Wu, Q. Zhu, H. Guan, S. Cao, F. Chen, T.-H. Chung, H. Deng, D. Fan, M. Gong, C. Guo, S. Guo, L. Han, N. Li, S. Li, Y . Li, F. Liang, J. Lin, H. Qian, H. Rong, H. Su, S. Wang, Y . Wu, Y . Xu, C. Ying, J. Yu, C. Zha, K. Zhang, Y .-H. Huo, C.-Y . Lu, C.-Z. Peng, X. Zhu, and J.-W. Pan, “Logical magic...

    work page internal anchor Pith review Pith/arXiv arXiv 2023

  55. [56]

    Magic state injection on ibm quantum processors above the distillation threshold,

    Y . Kim, M. Sevior, and M. Usman, “Magic state injection on ibm quantum processors above the distillation threshold,” 2024. [Online]. Available: https://arxiv.org/abs/2412.01446

    Pith/arXiv arXiv 2024

  56. [57]

    Efficient magic state cultivation with lattice surgery

    Y . Hirano, R. Toshio, T. Itogawa, and K. Fujii, “Efficient magic state cultivation with lattice surgery.” [Online]. Available: http: //arxiv.org/abs/2510.24615

    arXiv

  57. [58]

    Magic state cultivation on a superconducting quantum processor,

    E. Rosenfeld, C. Gidney, G. Roberts, A. Morvan, N. Lacroix, D. Kafri, J. Marshall, M. Li, V . Sivak, D. Abanin, A. Abbas, R. Acharya, L. A. Beni, G. Aigeldinger, R. Alcaraz, S. Alcaraz, T. I. Andersen, M. Ansmann, F. Arute, K. Arya, W. Askew, N. Astrakhantsev, J. Atalaya, R. Babbush, B. Ballard, J. C. Bardin, H. Bates, A. Bengtsson, M. B. Karimi, A. Bilme...

    arXiv 2025

  58. [920]

    Available: https://doi.org/10.1109/QCE60285.2024.00110

    [Online]. Available: https://doi.org/10.1109/QCE60285.2024.00110

    arXiv 2024

  59. [2019]

    Available: http://dx.doi.org/10.22331/q-2019-04-30-135

    [Online]. Available: http://dx.doi.org/10.22331/q-2019-04-30-135

    doi:10.22331/q-2019-04-30-135 2019

  60. [2020]

    OpenSurgery for Topological Assemblies

    [Online]. Available: https://arxiv.org/abs/1906.07994

    work page internal anchor Pith review Pith/arXiv arXiv 1906

  61. [2022]

    Available: https://arxiv.org/abs/2005.13018

    [Online]. Available: https://arxiv.org/abs/2005.13018

    Pith/arXiv arXiv 2005

This paper was first reviewed by deepseek-v4-flash on August 5, 2026.