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REVIEW 6 major objections 4 minor 46 references

Scalable Circuit Cutting: A Framework for Combined Gate and Wire Cuts Using Gate Groups

T0 review · 6 major / 4 minor · reviewed 2026-08-08 · deepseek-v4-flash

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Pith's one-line read The paper's central claim is that gate cutting, wire cutting, and joint cutting of gate groups can all be selected together by a two-stage graph-partitioning heuristic, which the authors report never performs worse than gate cutting alone…

desk verdict Plausible and useful graph-partitioning framework for combined gate/wire/joint cutting, but the unverified cost-objective encoding (raw vs log) undermines the 'never worse' guarantee and the headline overhead numbers until fixed. read the letter →

arxiv 2608.05287 v1 pith:3RBWDRCJ submitted 2026-08-05 quant-ph cs.ET

Fiona Jiali Fröhler , Yannick Stade , Christian Ufrecht , Daniel D. Scherer , Robert Wille This is my paper · ORCID
classification quant-phcs.ET
keywords quantumcircuitcuttinggatewirejointgroupsgraphpartitioningsamplingoverheadcutplacement
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

Circuit cutting breaks a quantum circuit too large for one device into smaller pieces that run independently and are stitched back together classically, but every cut multiplies the sampling overhead, so choosing cut locations well is essential. Existing methods typically optimize either gate cuts or wire cuts on their own, and those that consider both do not exploit joint cutting, where several gates are cut together at reduced cost. This paper argues that all three strategies -- gate cuts, wire cuts, and joint cuts of gate groups -- should be chosen together, and proposes a two-stage graph-partitioning heuristic that does so. The authors report that the method never performs worse than pure gate cutting, finds mixed cuts with lower overhead on benchmark circuits, and scales to 1000 qubits with moderate runtime. If the claim holds, quantum compilers could automatically produce near-optimal cut placements and get a diagnostic signal for whether a circuit is worth cutting at all.

What carries the argument

The load-bearing objects are the interaction graph and the circuit topology graph. The interaction graph has one node per qubit, edges weighted by the number of two-qubit gates, and a balanced Kernighan-Lin partition yields the initial gate-cut placement. The circuit topology graph adds gate vertices and wire edges to represent time, with edge weights $w_g = \log \kappa_g$ and $w_w = \log \kappa_w$ so that additive graph cost corresponds to multiplicative sampling overhead. Gate groups are modeled not as fixed-cost hyperedges but as partition-dependent cost functions, and the Kernighan-Lin D-values and swap gains are adjusted to include the group's current-versus-moved cost (Eqs. 2 and 3), with group-internal edges removed to avoid double-counting. The two-stage initialization is the mechanism that guarantees the final cut is never worse than the gate-only cut.

What would settle it

Take a small circuit with a known exact optimum, such as the paper's own 6-qubit example, and enumerate all valid bi-partitions to compute the true sampling overhead for each; if the heuristic ever returns a partition whose true overhead is higher than another valid partition it had rejected, the cost mapping is unfaithful. A concrete check is whether the paper's objective value for a gate group, computed as the sum of $\log \kappa$ edge weights plus the group adjustment, orders alternatives the same way the true overhead $\kappa^{2n_g}\kappa^{2n_w} S_{\text{group}}$ does.

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Extended reading notes

Core claim

The central claim is that the cut-placement problem for combined gate and wire cutting, extended with joint gate-group cuts, can be recast as a scalable balanced graph-partitioning problem without sacrificing any of the three cut types. The paper's two-stage method first partitions the qubit interaction graph to find a good gate cut, then refines that partition on a circuit topology graph that encodes temporal ordering, which allows wire cuts to replace expensive gate cuts when that lowers the objective. Gate groups enter as partition-dependent cost functions inside the Kernighan-Lin gain calculations, so the heuristic can recognize when cutting several gates together is cheaper than cutting them individually. Because the second stage is initialized with the first-stage partition, the authors argue the final solution is never worse than the gate-only cut; their experiments report substantial overhead reductions, including more than 90% on QFT circuits, with runtimes that scale to 1000 qubits. The paper's conclusion is that this makes circuit cutting practical for near-term devices and gives compilation pipelines a way to say early on whether a circuit is unsuitable for cutting.

Load-bearing premise

The algorithm's graph objective must exactly mirror the true sampling-overhead cost, meaning gate-group adjustments need to be on the same logarithmic scale as the edge weights and edges with multiple gates need the right multiplicative weight; if that mapping is wrong, the heuristic is optimizing a cost that does not match the actual sampling burden.

Editorial extensions

If this is right

  • Circuits that benefit from a mix of cut types will get a mixed solution, since the second stage can always replace gate cuts with cheaper wire cuts.
  • The final sampling overhead is bounded above by the pure gate cut, so adding wire cuts and joint cuts can only help or tie.
  • Dense circuits with many parallel gates see the largest gains from gate groups, with QFT reported at more than 90% overhead reduction.
  • Runtime scaling to 1000 qubits makes the method usable as an automated compiler pass rather than a one-off analysis.
  • Persistently high cut costs can be read as a diagnostic that the circuit is fundamentally hard to cut, enabling early go/no-go decisions.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the logarithmic scaling of gate-group costs is confirmed or fixed, the same graph model could absorb additional cut mechanisms, such as wire cuts with classical communication, by substituting their effective $\kappa$ values.
  • The paper restricts itself to bi-partitioning; a recursive or k-way extension using the same cost functions is a natural next step and would let the method handle more than two subcircuits.
  • Gate-group identification is currently manual, so an automatic pattern detector for the cascade, parallel, and other groupings would likely enlarge the reported advantages on dense circuits.
  • The diagnostic signal could be used pre-flight in a compiler to choose between circuit cutting, error mitigation, or distributed quantum execution before any samples are spent.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

6 major / 4 minor

Summary. This paper proposes a heuristic cut-placement method for quantum circuit cutting that combines gate cuts, wire cuts, and joint cuts of gate groups. The algorithm maps a circuit to an interaction graph for a stage-one Kernighan-Lin gate-cut search, then to a circuit topology graph for a stage-two refinement that also permits wire cuts, with gate-group costs incorporated through partition-dependent terms in the KL gain calculation. The authors benchmark against a Gurobi-based MIP gate-cutting approach, CutQC, and Qiskit's circuit cutting module, and report scalability tests up to 1000 qubits. The central claims are that the two-stage procedure never performs worse than pure gate cutting and that gate-group-aware joint cutting provides substantial overhead reductions, with QFT circuits cited as showing over 90% reduction.

Significance. If validated, the method would be a practically useful contribution to quantum compilation: it scales to hundreds of qubits, builds on established graph-partitioning machinery, and addresses a real gap by treating gate cuts, wire cuts, and joint gate groups in one heuristic. The overall structure is sensible, the use of published per-cut overhead constants is appropriate, and the evaluation spans several baselines. However, the quantitative claims currently rest on an under-specified optimization objective, an unproved monotonicity guarantee, a missing exact combined-cut baseline, and gate-group benchmarks whose groups are manually identified; these issues need to be resolved before the contribution can be fully assessed. No code or artifact is made available, which further limits independent verification of the empirical results.

major comments (6)
  1. [Sec. V.B and Sec. V.C, Eqs. (1)-(3)] The optimization objective is not fully specified. Edge weights are set to logarithms of the per-cut overhead factors, but the gate-group cost terms c_current, c_moved, and c_swapped in Eqs. (2) and (3) are described as 'the actual sampling overhead incurred by cutting that group.' If these group costs enter the gain calculations as raw multiplicative overhead values while edge weights are logarithmic, the KL heuristic minimizes a mixture of two different scales. For example, a two-CNOT parallel group with kappa=7 would enter as 7, while the same two gates cut individually contribute 2*log(3) if edge weights are accumulated per gate; this can make KL prefer a partition that is worse in true sampling overhead. Please define the exact scalar objective minimized by the adapted KL algorithm and apply a consistent logarithmic scale to all cost terms.
  2. [Sec. V.A and Sec. V.B, Eq. (1)] The weight of an edge that represents several two-qubit gates is ambiguous. The interaction graph construction increments an edge once per two-qubit gate, but Eq. (1) assigns a weight log(kappa_g) without stating whether an edge with m gates has weight m*log(kappa_g) or log(kappa_g). This matters because kappa_g is gate-type dependent and because the circuit topology graph may contain multiple gates on the same qubit pair. Additionally, when edges belonging to a gate group are removed from the interaction graph, the paper does not state how an aggregated edge containing both grouped and ungrouped gates is handled. Please state the weight accumulation rule explicitly and use it consistently in both stages.
  3. [Sec. IV and Sec. V.B] The claim that the two-stage procedure 'never performs worse than pure gate cutting alone' is asserted in Sec. IV and repeated in Sec. V.B, but no acceptance rule or invariant is described. The text does not say that the final KL refinement compares against the stage-one partition and retains the better solution, nor does it prove that replacing gate cuts with wire cuts is monotone in the objective. Without such a rule or proof, the guarantee is unsupported. Please either specify an explicit final comparison that keeps the better partition or provide a monotonicity argument.
  4. [Sec. VI.C, Table I] The most relevant exact baseline for the paper's central claim, the combined gate-and-wire cut solver of Brandhofer et al. [11], is cited in Sec. II.D but is absent from the benchmark table. Since MIP gate cutting and CutQC optimize only one cut type, they are not sufficient baselines for demonstrating the benefit of combined gate and wire cutting. The authors should compare against [11] on the small instances where that exact method terminates, or explicitly state why such a comparison is not possible.
  5. [Sec. VI.C, Table I, and Sec. VI.A] Gate-group identification is stated in Sec. VI.C to be manual rather than automatic, and the QFT-12 row of Table I lists '[Future Work]' under the gate-group column. The headline claim of an 'over 90% reduction' for dense QFT circuits therefore rests on a single completed 6-qubit instance with manually chosen groups, and the claimed scalability with joint cutting is not yet demonstrated. Please either provide an automatic group-finding method or clearly re-scope the gate-group results as a proof-of-concept with manual group selection.
  6. [Sec. II.A, Sec. III, and Table I] The manuscript is inconsistent about whether 'sampling overhead' means the product of per-cut kappa factors or the quantity S = kappa_g^(2 n_g) * kappa_w^(2 n_w) * S_group defined in Sec. III. Figures 2 and 4 and Example 2 report products such as 3*4=12, while the definition of S and the title of Table I refer to squared overhead factors. Since the relation S = g^2 holds only when every cost term is an unsquared kappa factor and group costs are handled consistently, the connection between the illustrative examples and the numerical overhead values in Table I needs to be stated explicitly. Please fix one convention and apply it throughout.
minor comments (4)
  1. [Sec. III] The sentence beginning 'Although combining gate and wire cutting with joint cutting can significantly reduce sampling overhead compared to individual cuts.' is a sentence fragment; it should be completed or joined to the preceding paragraph.
  2. [Abstract and Sec. II.D] The phrase 'for the first time' in the abstract is stronger than needed and could be read as claiming combined gate-and-wire cutting itself is new, although Sec. II.D already cites [11] for that combination. Please qualify the novelty claim to the scalable heuristic treatment of joint gate groups.
  3. [Table I] Several numeric entries such as '11.7×10^3' and '14886.5×10^4' mix mantissas and powers of ten in ways that are difficult to parse; please use a uniform scientific-notation format and add a legend explaining entries such as 'NA' and '[Future Work]'.
  4. [General] The paper would benefit from an explicit artifact availability statement; because the method is an empirical heuristic with many implementation details, releasing the Python/NetworkX code would substantially improve reproducibility.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the method optimizes an explicit graph objective using external overhead constants and is benchmarked against independent baselines.

full rationale

The derivation chain is self-contained in the sense required here: the sampling-overhead constants kappa_g, kappa_w, and the gate-group overhead formulas are taken as inputs from prior theoretical work (Sec. II), not fitted or predicted from this paper's own data. The parallel-gate formula kappa = 2^(n_g+1)-1 is attributed to Refs. [16]-[18]; although Ref. [16] is co-authored by C. Ufrecht, Refs. [17] and [18] are independent and the formula is treated as a stated external result, not as a conclusion derived from this framework. The benchmark results are comparisons against external tools (MIP [45], CutQC [25], Qiskit [36]) on MQT Bench circuits, so the reported overhead reductions are not reverse-engineered from constants fitted in this paper. The two-stage KL procedure is a heuristic that minimizes an explicit graph objective; the claim that it never performs worse than pure gate cutting is a design property of refining the stage-one partition, and any mismatch between the log-scaled edge weights and possibly raw group costs in Eqs. (2)-(3) is an objective-fidelity/correctness concern rather than circularity. The paper also explicitly flags manual gate-group identification as an open limitation (Sec. VI.C), which weighs against treating the group results as forced by construction. No load-bearing step reduces, by definition or by self-citation, to the paper's own output.

Assumptions & free parameters 2 free parameters · 4 assumptions · 0 invented entities

The framework itself introduces no new physics; it relies on prior overhead formulas, a heuristic graph partitioner, and an unproven non-worsening property for the two-stage refinement. Experimental hyperparameters, including the 3/4 balance ratio and 50 KL restarts, are chosen by hand. Gate-group identification is also a manual choice in the evaluation, which further limits the claim of a fully automatic scalable method.

free parameters (2)
  • partition balance ratio = 3/4 of qubit count
    Evaluation constrains each subcircuit to at most 3/4 of the original qubits (Sec. VI.A); this is a user-defined test setting, not derived from theory.
  • KL restarts = 50
    The algorithm runs Kernighan-Lin 50 times per instance and keeps the best result (Sec. VI.A); this number is chosen by hand and affects the runtime-quality tradeoff.
assumptions (4)
  • domain assumption Sampling overhead for n independent cuts scales as kappa^{2n}, with kappa_g=3 for CNOT, kappa_g=1+2|sin(theta)|, kappa_g=7 for swap, and kappa_w=4 for wire cuts.
    Taken from prior work [4], [5], [6], [12]; the optimizer minimizes this objective, and correctness of the claimed overhead reductions depends on these constants being the true minimal overheads (Sec. II.A).
  • domain assumption Gate-group overhead formulas, such as kappa=2^{n_g+1}-1 for parallel CNOTs and kappa=3 for cascades, are exact and position-independent.
    Citing [12], [16]-[18]; used as cost functions in Sec. II.C and Sec. V.C.
  • ad hoc to paper The two-stage refinement initialized from the first-stage partition never degrades the cut quality.
    Asserted in Sec. IV ('This two-level approach guarantees...') without a formal proof; KL swaps could in principle increase cost unless the search explicitly retains only improving moves.
  • ad hoc to paper Log-scaled edge weights plus gate-group cost adjustments form a faithful additive proxy for total sampling overhead.
    Eq. (1) and Sec. V.C; the paper does not specify whether group costs are log-scaled, and interaction-graph edges aggregate multiple gates into a single edge.

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Pith. "Pith review of Scalable Circuit Cutting: A Framework for Combined Gate and Wire Cuts Using Gate Groups." pith.science (2026). https://pith.science/paper/3RBWDRCJ

@misc{pith2026260805287,
  author       = {Pith},
  title        = {Pith review of: Scalable Circuit Cutting: A Framework for Combined Gate and Wire Cuts Using Gate Groups},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/3RBWDRCJ}},
  note         = {Machine review of arXiv:2608.05287}
}
read the original abstract

Quantum circuit cutting enables the execution of large circuits on devices with a limited number of qubits by partitioning circuits into independent subcircuits. However, this introduces a sampling overhead, which grows exponentially with the number of cuts, rendering the choice of cut placements critical for practical circuit cutting. Determining optimal cut placements remains computationally challenging, particularly as circuits grow in size. Additionally, existing circuit cutting approaches typically treat gate and wire cuts independently. Those combining both cutting approaches, however, do not take advantage of joint cutting, i.e., identifying common gate groups and cutting them jointly for a reduced overhead. This work presents a unified framework that combines gate and wire cutting within a single partitioning strategy, enabling more efficient circuit decompositions. Moreover, our approach incorporates joint cutting via a novel gate grouping technique, further reducing sampling overhead. By formulating the cut placement problem as a scalable graph partitioning task, our method efficiently identifies near-optimal cut placements for large circuits, also providing diagnostic feedback on whether circuits are suitable for cutting.

Figures

Figures reproduced from arXiv: 2608.05287 by the authors.

Figure 1
Figure 1. Different kinds of quantum circuit cuts and the circuit cutting workflow. [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Example illustrating the advantage of combined cutting. While pure gate or wire cuts may be optimal within their own categories, a unified strategy [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Examples of different types of gate groups and their associated [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (3 more)
Figure 6
Figure 6. Figure 6: Mapping circuit in Fig. 2 to a circuit topology graph to find gate [PITH_FULL_IMAGE:figures/full_fig_p004_6.png]
Figure 5
Figure 5. Figure 5: Mapping circuit in Fig. 2 to an interaction graph to find gate cuts. [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]
Figure 8
Figure 8. Figure 8: Scalability results and generated benchmark circuit. [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]

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