Balanced Routing for Symmetric Quantum Circuits

Samuel Punch

REVIEW 4 major objections 4 minor 9 references

Balanced Routing for Symmetric Quantum Circuits

T0 review · 4 major / 4 minor · reviewed 2026-08-07 · deepseek-v4-flash

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Pith's one-line read For cyclic circuits on heavy-hex, routing imbalance is an assignment choice wherever the patch shape allows a balanced assignment.

desk verdict Useful two-level picture of routing imbalance, with a genuinely new topological classification, but the 'proof' is pinned to one Qiskit version and no artifacts are shipped. read the letter →

arxiv 2608.06072 v1 pith:NPKC7IYC submitted 2026-08-06 quant-ph cs.ET

Samuel Punch This is my paper · ORCID

classification quant-phcs.ET MSC 81P68

keywords quantumcircuitcompilationroutingimbalancesymmetry-awareassignmentheavy-hexlatticeequivariantcircuitsSWAPtopologicalconstraintsexhaustivesearch

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper claims that, for cyclic symmetric circuits compiled onto a heavy-hex quantum chip, routing imbalance is not fixed by hardware topology. Whether any balanced assignment exists is fixed by the shape of the qubit patch, but whenever balance is possible, the compiler's logical-to-physical assignment decides how uneven the routing cost is, and a balanced assignment can spread the cost perfectly evenly at no extra circuit depth. The claim is established by exhaustive search over all connected patches: for a four-part ring, 108 of 124 connected patches admit a cost-free balanced assignment, and the 16 failures are exactly star-shaped patches; for a six-part ring no compact patch does it for free; for a fully connected four-part symmetry no patch does it at any depth. Under realistic simulated noise, balanced assignments reduce measured symmetry-breaking by about 93 percent relative to the worst-case concentrated assignment, with most of that reduction coming from the routing spread itself rather than from uneven qubit error rates. A sympathetic reader would care because it turns an apparent hardware limitation into a compiler optimization that costs nothing in depth.

What carries the argument

The load-bearing devices are the ring-distance profile and the duality lemma. The profile is the list of graph distances between consecutive logical roles on the physical patch, e.g. $(1,2,1,2)$ for a balanced four-part ring on a path; routing cost and its spread are read off this profile. The duality lemma equates measuring a rotated input on a fixed placement with measuring the unrotated input on a relabelled placement, turning symmetry-breaking into a property of the assignment. The exhaustive search enumerates every connected patch and every assignment up to rotation and reversal, using a graph-hash fingerprint only to count patch shapes, so each negative verdict is an impossibility proof. The closed-form balancing rule for the four-part ring assigns $\pi(0)=p_0$, $\pi(1)=p_1$, $\pi(2)=p_3$, $\pi(3)=p_2$ on a path and yields zero spread at the patch's cheapest depth.

What would settle it

Re-run the exhaustive assignment search with a different compiler's routing cost model over all 124 connected four-qubit patches: if any path-shaped patch shows a zero-spread assignment that costs more depth than its cheapest assignment, or any star-shaped patch admits a zero-spread assignment at any depth, the paper's central dichotomy is wrong. A live-device comparison with roughly uniform error rates would also settle it: the balanced assignment should reproduce the reported roughly 93 percent reduction in per-role spread; if it does not, the assignment-dependence claim fails.

Watch

Extended reading notes

Core claim

The central discovery is a two-level division of responsibility. For a cyclic symmetry, a ring of logical roles that should be interchangeable, the measured spread in per-role error is a statement about assignment: the paper's duality lemma shows that rotating the input is equivalent to relabelling which physical qubit plays which role, so the symmetry-breaking seen in experiments is literally the unevenness of routing across roles. The paper then proves, by exhaustive search over every connected patch of the 57-qubit heavy-hex lattice, that a patch's shape decides whether a balanced assignment exists and the assignment decides the actual imbalance when one exists. In concrete terms, on every path-shaped four-qubit patch the assignment that places the first two roles in order and swaps the last two yields ring-distance profile $(1,2,1,2)$, zero spread, and the patch's cheapest depth; star-shaped patches cannot host this profile; and fully connected four-part symmetry cannot be balanced on any compact patch at any depth because the sparse chip cannot place four qubits at equal distances.

Load-bearing premise

The load-bearing premise is that the routing cost model used by the compiler in the exhaustive search is the ground truth for what an assignment costs; a different compiler or routing algorithm that changed relative assignment costs could shift the free-lunch and no-free-lunch verdicts.

Editorial extensions

If this is right

For any cyclic block on a patch that admits balance, a compiler can eliminate routing imbalance for free, so symmetry-aware assignment should be a first-class optimization target rather than an afterthought.
Chip layouts can be compared by a new metric: how many balanced assignments the patch hosts; star-shaped four-qubit patches score zero for a four-part ring.
Benchmarks of cyclic workloads should report the spread of per-role routing cost, because the average gate count is identical for the balanced and concentrated assignments and hides the breaking.
On heavy-hex, a fully connected four-part symmetry cannot be balanced on any compact patch at any depth, so that symmetry class needs different hardware or a different circuit structure.
A six-part ring can be balanced only by paying extra depth, and the paper leaves open the optimization of that depth-for-balance trade.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

If the patch-shape characterization carries over to other sparse topologies, such as square or triangular lattices, then balanced-assignment capacity becomes a design metric for chip geometry, not just for heavy-hex.
Because the paper isolates the effect from error heterogeneity, one testable extension is to run the balanced-versus-concentrated comparison on chips with deliberately skewed error maps; the claim predicts the roughly 93 percent reduction persists as long as routing-cost spread is the dominant per-role difference.
The six-part no-free-lunch result turns into an optimization problem a symmetry-aware compiler could solve: minimize additional depth subject to zero spread for a six-part ring, with the smaller-chip exhaustive search as a certified baseline.
For multi-block circuits containing many cyclic blocks, assigning each ring independently could create cross-block depth tradeoffs, so a scheduler-level extension is needed.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Good to talk. I've read the Punch paper and I think it's worth taking seriously, though the strongest claims need a caveat. The genuinely new thing is the classification: on heavy-hex, a four-part ring can be balanced for free on any path-shaped patch (108 out of 124), while the 16 star-shaped patches fail, and the six-part ring has no free lunch on compact patches. That's a concrete, non-obvious result about how assignment, not just topology, sets routing imbalance. The closed-form rule for C4 is clean and useful, and the duality lemma (rotating input equals relabeling placement) is a neat way to make the mechanism precise.

The paper does several things well. The exhaustive search is the right tool for this question, and the authors are honest about scope: they flag the 19-qubit versus 57-qubit gap, the simulated error model, and that the rule stops at four. The simulation is also sensibly designed: balanced versus concentrated on the same path, same qubits, same average gate count, so the difference is attributable to the spread of routing cost. The statistical reporting is solid, with CIs and a paired test.

Now the soft spot, and it's the one the stress-test note puts its finger on. The "proof" of the counts is conditional on Qiskit 2.5.1's routing cost model. Table I itself reports a different worst-case spread for older versions (12 vs 9), so the exact numbers are version-specific. The balanced profile (1,2,1,2) might be zero-spread in one router but not another, and the "no free lunch" verdicts could change if a different router assigns costs differently. The paper asserts the effect doesn't depend on the routing algorithm, but that's a plausible claim, not a proven one. Because no code, seeds, or independent cost model are given, I can't check whether the 108/124 or the 0/62 are robust. That's a real reproducibility gap, not a nitpick.

The six-part result being only on the 19-qubit chip is minor since the paper labels it as a scoping limitation. The simulation is fine as a controlled comparison, though it's not live-device evidence.

Overall, the mechanism and the topological classification are valuable to the compiler community, and the paper deserves a serious referee. My recommendation: send it to review, but with a strong request for shipped code and a robustness check across router versions (or at least a cleaner statement that the counts are router-dependent). I'd bring it to reading group; it will spark a good discussion about what "proof" means when the cost model is a heuristic.

Referee Report

4 major / 4 minor

Summary. The paper studies how compiling cyclic-symmetric circuits onto heavy-hex hardware induces routing imbalance. It distinguishes two levels: whether a patch of qubits can host a balanced assignment (shape-dependent) and whether the actual assignment realizes it (compiler choice). The authors characterize four-qubit rings: on path-shaped patches the assignment (1,2,1,2) gives zero spread of per-role two-qubit gate counts at no extra depth, while star-shaped patches fail. For six-qubit rings, no compact patch gives a free balanced assignment; for fully connected four-part symmetry, balance is claimed to be impossible at any depth. Simulations with realistic noise claim a 92.7% reduction in raw symmetry-breaking and 87.0% in a decoherence-corrected metric relative to the worst-case concentrated assignment, with a 10.8% upper bound on the substrate-heterogeneity contribution. A closed-form balancing rule for the four-part ring is given. The paper explicitly scopes the six-part no-free-lunch result to a 19-qubit chip.

Significance. If the exhaustive verdicts are correct, the paper makes a useful conceptual point: routing imbalance for cyclic blocks is a compiler assignment choice whenever the patch geometry permits, and generic depth-minimizing passes do not reliably fix it. The exhaustive enumeration over all connected patches of the stated sizes is a strength, as is the explicit separation of 'exists at extra depth' versus 'free lunch' and the use of paired statistics with confidence intervals. The paper also honestly lists its limitations in the Discussion. However, the headline numbers are tied to a single compiler release, and the proof methodology for the 'at any depth' claims is not fully described, so the significance is conditional on those being clarified.

major comments (4)

[Abstract and Section V] The abstract states that 'Through exhaustive search on a 57-qubit “heavy-hex” lattice, we prove these topological constraints exactly. For a six-part ring, cost-free balance is impossible on compact patches.' However, Section V, under 'Plain statement of scope,' says the six-part no-free-lunch result is proved on the smaller 19-qubit chip (d=3), with extension to the 57-qubit layout explicitly left as a scoping limitation. As written, the abstract overstates the support for the six-part claim. Please either prove the six-part result on the full 57-qubit lattice (the paper estimates this as a half-hour computation) or qualify the abstract to match the stated scope.
[Section V, Table II] The 'Exists at any depth' verdicts are not backed by a described search over depth. The text explains that for each patch 'we generate every assignment up to the ring’s own rotations and reversals' and transpiles them; it does not describe how arbitrary extra SWAP insertions (that is, larger depths) are searched or bounded. The S4 conclusion that no patch balances at any depth is therefore stronger than the presented finite enumeration supports. The intuitive argument about four qubits not being at equal distance addresses direct interaction distances, not SWAP-sequence costs, which can in principle be modified by adding gates. Please specify the exact search space for the 'at any depth' verdicts, or provide a proof that suffices.
[Section V, Tables I and II] The free-lunch classifications are defined by two-qubit-gate counts from a single, unspecified invocation of Qiskit 2.5.1's routing pass. Table I itself reports that an older compiler version changed the worst-case spread from 12.0 to 9.0, showing that the cost model is version-dependent. No code, seeds, or independent routing-cost model are provided. Since the central exhaustive counts (108/124, 0/62, and the 27 vs 13 gate estimates) are statements about these counts, their robustness is not established. The sentence 'the exact number depends on the routing algorithm, but the effect does not' is an assertion; please either ship the search code with fixed seeds, test with an independent cost model, or explicitly delimit all headline claims as 'with respect to Qiskit 2.5.1.'
[Section VI] The claim that substrate error heterogeneity 'accounts for at most 10.8% of the matched-mean baseline effect' is not assessable because the channel-resolved ablation is not described: there is no specification of how error rates were varied, how the matched-mean baseline is defined, or how the 95% confidence bound was computed. This number is used to attribute the simulated effect to routing imbalance rather than qubit-quality variation, so the method needs to be reported in detail.

minor comments (4)

[Section IV, Eq. (5)] The expectation operator E_x and the variable x are not defined; clarify that the expectation is over measurement shots.
[Section IV] The resolution guard |\bar\mu| > 3\sigma_{\bar\mu} is never defined; provide the formula for \sigma_{\bar\mu}.
[Table II] The C6 row entry 'yes (d=5) no' is ambiguous; the column structure should make clear what the parenthetical refers to (chip size versus depth).
[Figure 1] The axis label 'orbit routing asymmetry' is unexplained; please define 'orbit' in the caption.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the central claims are established by exhaustive enumeration and a controlled noise simulation, not by definition or self-citation.

full rationale

The derivation chain is self-contained. Equation (2) is an exact duality identity showing that rotating the input equals relabelling roles on the chip; equation (3) then defines per-role error as a sum over compiled gate instances. The topological verdicts in Section V are produced by exhaustive enumeration of all connected patches and all assignments, with Qiskit 2.5.1 used to obtain two-qubit-gate counts; the balanced profile (1,2,1,2) is not defined as 'zero spread' but is found to have zero spread in the transpiled counts, while the concentrated profile (1,1,1,3) has spread 9.0. Section VI compares these two assignments on the same physical qubits with the same average gate count and error exposure, and the noise-inclusive spread is a separate measured quantity that could in principle have contradicted the gate-count spread; the reported 92.7% reduction, confidence intervals, Wilcoxon p-value, and 10.8% heterogeneity ablation make the comparison empirical rather than tautological. No parameter is fitted to the target result, and no load-bearing self-citation or imported uniqueness theorem is used. The disclosed limitations—dependence on Qiskit 2.5.1's routing cost model for the exact counts, and the six-part free-lunch verdict being proved only on the 19-qubit chip—are external-validity and scoping concerns, not circularity.

Assumptions & free parameters 1 free parameters · 4 assumptions · 0 invented entities

The central claim rests on the duality lemma, the compiler cost model, the completeness of the exhaustive search, and the representativeness of the simulated error rates. No free parameters are fitted to the target results, though one data-filtering threshold is hand-chosen.

free parameters (1)

Resolution guard threshold |\bar mu| > 3 sigma_{\bar mu} = 3 sigma
Chosen in Section IV to filter paths with vanishing signal before computing the decoherence-corrected metric; changing it would alter the reported 87.0% reduction and the n=212 sample.

assumptions (4)

standard math For the studied symmetries, the symmetry operation is a permutation of qubits, making Eq. (2) an exact identity.
Invoked in Section III as the duality lemma; it is a mathematical identity for permutations.
domain assumption The compiler's routing cost for a given assignment is a deterministic function of the hardware graph and the compiler version.
The exhaustive search computes costs using Qiskit 2.5.1; the 'proof' of free-lunch verdicts depends on this cost model (Table I).
ad hoc to paper The exhaustive search enumerates every connected patch of the stated size exactly once.
Claimed in Section V; no code or certificate is shipped, so the enumeration is not independently checkable.
domain assumption Simulated error rates drawn to match IBM Heron and Eagle devices are representative for the comparison.
Section VI; the simulation is the only evidence for the 92.7% reduction, so the error model is load-bearing.

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Cite this review

Pith. "Pith review of Balanced Routing for Symmetric Quantum Circuits." pith.science (2026). https://pith.science/paper/NPKC7IYC

@misc{pith2026260806072,
  author       = {Pith},
  title        = {Pith review of: Balanced Routing for Symmetric Quantum Circuits},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/NPKC7IYC}},
  note         = {Machine review of arXiv:2608.06072}
}

read the original abstract

Mapping quantum programs to restricted physical chips requires SWAP operations, incurring depth and error penalties. In symmetric programs, this routing overhead breaks theoretical symmetry because identical logical roles experience unequal shuffling. While often attributed to hardware topology alone, we show this is a two-level phenomenon. A qubit patch's shape dictates if it can host a balanced assignment. When balance is possible, the actual imbalance is set by the logical-to-physical assignment, meaning a balanced assignment can distribute routing costs perfectly evenly at no extra depth. Through exhaustive search on a 57-qubit "heavy-hex" lattice, we prove these topological constraints. For a four-part ring, 108 of 124 connected patches admit a cost-free balanced assignment, with the 16 exceptions being star-shaped. For a six-part ring, cost-free balance is impossible on compact patches. For a fully connected four-part symmetry, balance is structurally impossible at any depth. Simulations using realistic error rates show that, relative to the worst-case concentrated assignment, balanced assignments reduce symmetry-breaking by 92.7% (95% CI [+89.8%, +95.3%]) for the raw metric and 87.0% (95% CI [+79.6%, +94.1%]) for the decoherence-corrected measure (p = 2.45 x 10^-32). Substrate error heterogeneity accounts for at most 10.8% of this effect. Notably, switching to the compiler's highest generic optimization level did not yield a statistically significant change in routing imbalance, highlighting the need for targeted symmetry-aware passes. When patch geometry permits, routing imbalance is a compiler choice rather than a hardware limitation. Thus, symmetry-aware assignment should be a primary objective for compiler optimization and chip design.

Figures

Figures reproduced from arXiv: 2608.06072 by the authors.

**Figure 3.** FIG. 3. The simulated error field (IBM Heron): single-qubit [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

**Figure 4.** FIG. 4. Balanced versus concentrated on the same path, un [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

9 extracted references · 9 canonical work pages

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Pith tools

Reviewed August 7, 2026 · model on record in the stance chip above.

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work page 2024

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Theoretical guarantees for permutation- equivariant quantum neural networks,

L. Schatzki, M. Larocca, Q. T. Nguyen, F. Sauvage, and M. Cerezo, “Theoretical guarantees for permutation- equivariant quantum neural networks,” npj Quantum In- formation10, 12 (2024)

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Prov- ably Trainable Rotationally Equivariant Quantum Ma- chine Learning,

M. T. West, J. Heredge, M. Sevior, and M. Usman, “Prov- ably Trainable Rotationally Equivariant Quantum Ma- chine Learning,” PRX Quantum5, 030320 (2024)

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C. T¨ uys¨ uz, S. Y. Chang, M. Demidik, K. Jansen, S. Val- lecorsa, and M. Grossi, “Symmetry Breaking in Geomet- ric Quantum Machine Learning in the Presence of Noise,” PRX Quantum5, 030314 (2024)

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