Paper Citation Record · LEDGER

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems

As of 16 August 2026, this Paper Citation Record lists 19 of 19 outbound references and 0 inbound Pith citation observations for arXiv:1908.06532.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
1908.06532 v1

Coverage vector

measured 19 of 19 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-14T12:45:07.247253Z

measured 19 of 19 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-16T06:30:59.297886+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

19 of 19 outbound references displayed

verified exact0
verified fuzzy16
unresolved3
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 7180cb94-2a9d-45ae-825a-2fe20420b760 · outbound

This paper cites A scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors (DYNAPs),.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems A scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors (DYNAPs),

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:08.077922Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation d1e3c0db-9d80-427d-a8bf-300ce9ca9f5c · outbound

This paper cites Hierarchical address event routing for reconﬁgurable large-scale neuromorphic sys- tems,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems Hierarchical address event routing for reconﬁgurable large-scale neuromorphic sys- tems,

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:08.031189Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation efdccd91-4476-4963-8865-57ae43e2bf53 · outbound

This paper cites A million spiking-neuron integrated circuit with a scalable communication network and interface,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems A million spiking-neuron integrated circuit with a scalable communication network and interface,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.993882Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation e114afed-8558-4874-84e8-c4bae52e9669 · outbound

This paper cites The SpiNNaker project,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems The SpiNNaker project,

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-14T12:45:07.105924Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 512f30c6-9d42-4d5d-9c94-5584280ee087 · outbound

This paper cites Neurogrid: A mixed-analog-digital multichip system for large-scale neural simulations,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems Neurogrid: A mixed-analog-digital multichip system for large-scale neural simulations,

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-14T12:45:07.121070Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 373884b4-0fbc-4d19-8f47-dfb13832e410 · outbound

This paper cites an unresolved cited work.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems Unresolved cited work

Reference 6

Resolution: unresolved; raw_fallback, observed 2026-08-14T12:45:07.918027Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 2a2d9890-2462-4dc6-85de-69baf13df00e · outbound

This paper cites Neuromorphic sensory systems,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems Neuromorphic sensory systems,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.869280Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 7dbc76a9-2262-4c28-a60c-ce3a0ef15181 · outbound

This paper cites A re-conﬁgurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128k synapses,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems A re-conﬁgurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128k synapses,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.838816Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 39a9b228-d0a3-4238-b555-bbf0e3b6d53c · outbound

This paper cites Robust working memory in an asynchronously spiking neural network realized in neuromorphic VLSI,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems Robust working memory in an asynchronously spiking neural network realized in neuromorphic VLSI,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.800873Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 9c033f48-6e25-408a-b0a2-6f13715a088c · outbound

This paper cites Synthesizing cognition in neuromorphic electronic systems,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems Synthesizing cognition in neuromorphic electronic systems,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.762570Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation aa45e33b-bcb6-41dd-aee7-05efb4f52850 · outbound

This paper cites CAVIAR: A 45k neuron, 5M synapse, 12G connects/s aer hardware sensory– processing– learning–actuating system for high-speed visual object recognition and tracking,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems CAVIAR: A 45k neuron, 5M synapse, 12G connects/s aer hardware sensory– processing– learning–actuating system for high-speed visual object recognition and tracking,

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.717175Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation c736e621-99a4-4c74-a18e-c52a688c8f29 · outbound

This paper cites A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity,

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.634859Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation a4af1519-df03-4cef-a61e-62ff95bbbc93 · outbound

This paper cites A 240×180 130 dB 3µs latency global shutter spatiotemporal vision sensor,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems A 240×180 130 dB 3µs latency global shutter spatiotemporal vision sensor,

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.590368Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 79901ed0-721f-40d0-b949-0cd4f3aa3b44 · outbound

This paper cites A 1.5ns OFF/ON switching-time voltage-mode LVDS driver/receiver pair for asynchronous AER bit-serial chip grid links with up to 40 times event-rate dependent power savings,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems A 1.5ns OFF/ON switching-time voltage-mode LVDS driver/receiver pair for asynchronous AER bit-serial chip grid links with up to 40 times event-rate dependent power savings,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.538602Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 1a602d80-f617-4c26-9ebd-594a4b200f3b · outbound

This paper cites Eﬃcient self-timing with level-encoded 2-phase dual-rail (LEDR),.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems Eﬃcient self-timing with level-encoded 2-phase dual-rail (LEDR),

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.503701Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 96db5c95-51e2-4749-a7bb-634a311124de · outbound

This paper cites A high-speed clockless serial link transceiver,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems A high-speed clockless serial link transceiver,

Reference 16

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.466620Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 4a268d3e-19d0-4f4a-93be-2fed0e7c306d · outbound

This paper cites A0.35 µm sub-ns wake-up time ON-OFF switchable LVDS driver- receiver chip I/O pad pair for rate-dependent power saving in AER bit-serial links,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems A0.35 µm sub-ns wake-up time ON-OFF switchable LVDS driver- receiver chip I/O pad pair for rate-dependent power saving in AER bit-serial links,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.428111Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation 46f6e3cd-39d7-48f1-a209-abc5aa4ee0ea · outbound

This paper cites LVDS interface for aer links with burst mode operation capability,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems LVDS interface for aer links with burst mode operation capability,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.386096Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Observation bc89bed6-32bf-4fb2-8f07-7124a709606c · outbound

This paper cites Memory and information processing in neuromorphic systems,.

A clock-less ultra-low power bit-serial LVDS link for Address-Event multi-chip systems Memory and information processing in neuromorphic systems,

Reference 19

Resolution: verified fuzzy; raw_fallback, observed 2026-08-14T12:45:07.338154Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-16T06:30:59.297886+00:00.

Pith citing papers

No inbound Pith citation observations are available.