DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models

Anushka Mukherjee; Kang He; Kaushik Roy

REVIEW 2 major objections 4 minor 22 references

A closed-loop LLM agent fixes ~92% of local chip-layout DRC violations on a 60-layout test suite by letting verification guide every edit.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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2026-08-01 06:33 UTC pith:34NH2UAN

load-bearing objection Solid LLM-agent system for DRC repair with unusually careful ablations, but the 92.5% success rate is measured on a synthetic benchmark whose violation types are exactly the rule families the engine can fix. the 2 major comments →

arxiv 2607.22761 v1 pith:34NH2UAN submitted 2026-07-23 cs.AR cs.LG

DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models

Anushka Mukherjee , Kang He , Kaushik Roy This is my paper

classification cs.AR cs.LG

keywords design rule checkingDRC repairlarge language modelsagentic frameworkphysical verificationLVS equivalencebacktracking searchlayout automation

verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

DRC-Aid sets out to show that the tedious local loop of fixing chip-layout design-rule violations—edit geometry, re-run DRC, repair what broke—can be largely automated with an off-the-shelf LLM, without fine-tuning. The framework forces the LLM to work as a constrained selector: a deterministic Rule Engine converts each reported violation into a small menu of legal geometric edits, and the LLM picks among them while commercial DRC/LVS tools verify every step and a budgeted search backtracks when fixes introduce new problems. On a 60-layout FreePDK45 test suite the system achieves DRC-clean, LVS-equivalent repair in roughly 92% of cases and reduces total violations by about 98%, with LLM selection beating random (54.4%) and heuristic (83.3%) selection under identical infrastructure. If this holds, it means a large share of repetitive manual layout repair could be delegated to a tool-grounded agent rather than left to engineers or to prediction-only ML systems.

Core claim

The paper claims that local DRC repair can be cast as verification-in-the-loop search over a deliberately small action space. A deterministic Rule Engine turns each reported violation into a bounded menu of grid-snapped edits (move/shrink/expand in four directions), tagged legal, risky, or blocked. An off-the-shelf LLM chooses an edit from this menu using serialized geometry and history; Calibre DRC and LVS verify each step, while budgeted DFS with backtracking and a memory bank guide exploration. On 60 FreePDK45 layouts with 285 injected violations, this reaches DRC-clean, LVS-equivalent repair in ~92% of cases and ~98% total violation reduction, versus 54.4% for random and 83.3% for determ

What carries the argument

The load-bearing mechanism is the Rule Engine: a deterministic pre-processor that converts an ambiguous verification marker into ranked geometric hypotheses and a small action menu, shrinking a combinatorial space (shapes × edit types × directions × magnitudes) down to what an LLM can reason over. Around it, budgeted depth-first search with anchor protection and backtracking turns single edits into multi-step plans; the Connectivity Engine bundles compensatory routing edits when a move severs a net; a global Memory Bank fingerprints visited states so the search cannot cycle; and mandatory Calibre DRC plus LVS health checks provide immediate reward signals that reject edits which clear geomet

Load-bearing premise

The load-bearing premise is that the 60-layout FreePDK45 suite, with violations injected inside the six rule families the Rule Engine covers, represents the local DRC-repair problem; if real layouts involve rule types or geometry outside that coverage, the measured ~92% success rate may not transfer.

What would settle it

Run DRC-Aid, with its Rule Engine unchanged, on a test suite whose violations include rule categories outside the six it handles (e.g., density, antenna, via-array, or non-Manhattan polygon rules) or on a different PDK; if strict success falls far below ~92%, the claim that local DRC repair is automatable at this level is falsified.

Watch this falsifier — get emailed when new claim-graph text bears on it.

If this is right

Local DRC repair can be automated with off-the-shelf LLMs, provided the model only selects from a bounded, rule-engine-generated edit menu rather than inventing geometry from scratch.
Verification-in-the-loop is what makes repair safe: removing LVS checks drops strict success from ~92% to roughly 74%, even though raw violation clearance stays above 95%.
Static prompting is not a viable repair route (SSR at most 6.6%); the gain comes from the closed-loop agentic structure, not from the LLM alone.
When full repair is not achieved, the framework still returns LVS-equivalent partial candidates that clear 78–86% of violations, so failures degrade gracefully rather than corrupting the layout.
Every layout in the 60-case suite was strictly resolved by at least two of the six model–seed runs, suggesting residual failures are budget- or sampling-related rather than intrinsic to the geometry.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

The same architecture could likely port to other repetitive local-fix loops in physical design, such as post-route fixup or analog layout editing, wherever a deterministic rule layer can be defined; the authors list congestion and post-route scenarios as future work.
Because the deterministic heuristic already reaches 83.3% SSR, a cheap production variant could reserve LLM reasoning for the hard minority of layouts (roughly those with six or more markers), where the LLM's margin widens to about 20 points.
A sharper test of whether the LLM's advantage is genuinely semantic would be to shuffle or strip the geometric context from the action menu; if the SSR gap over the deterministic ranker vanishes, the gain is in prompt structure rather than spatial reasoning.
Per-rule-family success rates would reveal where the Rule Engine's geometric hypothesis construction is the bottleneck; the current aggregate numbers may hide rule types where the menu itself rarely contains a correct fix.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Desk Editor's Note

Solid LLM-agent system for DRC repair with unusually careful ablations, but the 92.5% success rate is measured on a synthetic benchmark whose violation types are exactly the rule families the engine can fix.

read the letter

Colleague,

Here's the take on DRC-Aid. The genuinely new thing is the combination: a deterministic rule engine that converts DRC markers into a bounded menu of geometric edits, an off-the-shelf LLM that selects actions from that menu, and verification-in-the-loop budgeted DFS with backtracking and a global memory bank. That combination is not in the prior literature—most DRC-ML work is diagnostic, and the SA repair baseline treats repair as cost minimization. The paper shows that with this coupling, an LLM selector reaches ~92% strict success (DRC-clean and LVS-equivalent) on their 60-layout benchmark, versus 54% random and 83% deterministic-heuristic. The softmax-over-ranking baseline does not match the LLM, which is the right control to show the LLM is doing more than sampling diversity.

The paper is unusually careful on the empirical side. Three seeds, mean±std, identical infrastructure for all policies, Calibre nmDRC/nmLVS as ground truth, and a component ablation showing each piece matters. The SA reimplementation is a reasonable attempt at a fair comparison. No sign of fitting-to-target: the LLM is not fine-tuned and the comparison is clean under identical infrastructure.

The soft spot is the benchmark, and it is load-bearing. The test suite is built by perturbing DRC-clean FreePDK45 cells with random amounts relative to rule thresholds. The rule engine only generates actions for spacing, width, enclosure, extension, containment, and overlap—exactly the rule families used to create the violations. So for every injected violation, the menu is guaranteed to contain an inverse of the perturbation. That puts an artificial upper bound on the 92.5%: the LLM never encounters a violation class its action space cannot express. Real DRC includes antenna, density, end-of-line, and compound geometry where the fix is not a one-shot inverse. The authors acknowledge the action-space limitation in passing and list broader coverage as future work, but the abstract's claim that DRC-Aid automates local DRC repair overstates what this evaluation can support.

Second, the benchmark and code are not released, and the setup relies on commercial tools. Independent reproduction of the headline number would require substantial reverse-engineering. Combined with the co-designed benchmark, that makes 92.5% an upper bound for a specific distribution, not a general capability.

Nothing here is broken internally. The central claim—LLM selection adds value over the baselines under identical infrastructure—holds for this benchmark. The paper deserves a serious referee; the main review push should be for artifact release and an evaluation on a broader or independent rule set, not for flaws in the method itself.

I'd bring it to reading group. It is a clean example of how to evaluate an LLM agent against proper baselines, and the benchmark-design issue is exactly what we should be debating. Cite it if you are in EDA or LLM-agent evaluation. Send it to review.

Referee Report

2 major / 4 minor

Summary. The paper presents DRC-Aid, a closed-loop agentic framework for local design-rule correction in IC layouts. A deterministic Rule Engine converts Calibre-reported violations into a bounded menu of geometric edits (move/shrink/expand on spacing, minimum-width, enclosure, containment, and overlap checks). An off-the-shelf LLM (Qwen3-Next-80B or Gemma-4-26B) selects among these edits, with budgeted depth-first search and backtracking, a global memory bank to avoid cyclic re-exploration, and mandatory Calibre nmDRC/nmLVS verification after every edit. The Connectivity Engine bundles compensatory routing edits when an action would sever electrical connectivity. Evaluated on a 60-layout suite derived from DRC-clean FreePDK45 standard cells, the framework reports ~92.5% strict success (DRC-clean and LVS-equivalent) and ~98% total violation reduction, with LLM selection outperforming random (54.4%), deterministic-heuristic (83.3%), softmax (82.8%), and a reimplemented simulated-annealing baseline (38.3%) under identical infrastructure. Ablations attribute the result to the structured coupling of constrained action generation, verification-in-the-loop, and LLM-based selection.

Significance. If the reported results hold, the paper makes a credible case that an off-the-shelf LLM can act as a strategic action selector in a verification-in-the-loop repair system, converting a combinatorial geometric search into a tractable menu-selection task. The work is carefully engineered: it reports mean±std over three seeds, includes a component-wise ablation table, compares LLM selection against non-LLM selectors under identical candidate generation, search budget, and Calibre verification, and explicitly controls for the possibility that the LLM's advantage is merely stochastic sampling over the same heuristic ranking. The use of commercial-grade Calibre nmDRC/nmLVS as the ground-truth verification is a strength. The main limitation is that the evaluation benchmark is self-constructed from perturbations that fall exactly within the rule families the Rule Engine can address, which limits external validity but does not undermine the internal consistency of the measurements.

major comments (2)

[Sec. 3.2.1 and Sec. 4.1] The evaluation benchmark is co-designed with the action space. Section 4.1 describes the 60-layout suite as constructed by perturbing DRC-clean FreePDK45 cells 'by randomized amounts calculated relative to the ruledeck thresholds,' and Table 1 shows the marker categories are spacing, enclosure, minimum width, and overlap — exactly the rule families for which the Rule Engine generates actions (Sec. 3.2.1). Consequently, for every injected violation, the Rule Engine's hypothesis construction will include an inverse of the perturbation as a candidate action, so the action menu is guaranteed to contain a repair for each isolated violation. The measured ~92.5% SSR is therefore an upper bound for a distribution tailored to the framework's capabilities and may not transfer to real-world DRC rules such as antenna, density, end-of-line, or multi-polygon interactions that the engine explicitly doe
[Table 4] The claim that LLM selection outperforms the deterministic heuristic lacks statistical support. The reported mean±std over three seeds for Gemma-26B (92.2±5.1) overlaps the deterministic heuristic's 83.3% in the sense that one Gemma seed achieves only 86.7%, a ~3.4-point margin. Qwen-80B (92.8±1.0) is more consistent, but with n=3 model-level repetitions the difference is not formally established. The authors should report per-seed paired comparisons (e.g., deterministic heuristic versus each LLM seed on the same 60 layouts), bootstrap confidence intervals, or focus the claim on the ≥6-marker subset where the gap (63.2% vs 82.5–84.2%) is more convincing. This point is load-bearing for the central claim that the LLM adds value beyond a fixed ranker.

minor comments (4)

[Sec. 3.2.1] The search-space equation uses notations C_layout, E_tp, E_dir, E_mag without formal definition. Please define each set and the Cartesian-product decomposition more precisely.
[Table 3] The configuration columns are hard to read because checkmark/dash patterns are not labeled per row. A textual description of each configuration or a clearer legend would improve reproducibility.
[Sec. 4.1] The statement '45–48 of 60 layouts requiring at least one backtrack across model–seed runs' is vague. Report the per-model, per-seed counts, or replace with a distribution.
[Abstract] The abstract reports '~92.5%' SSR, which is the average of 92.2% and 92.8%. State the per-model range or report the mean and std to be precise.

Circularity Check

0 steps flagged

No circularity: the core result is an empirical closed-loop measurement; benchmark/action-menu overlap is an external-validity limitation, not a circular reduction.

full rationale

I find no circular step in the claimed derivation chain. The central results (Sec. 4.2) are measured outcomes of a closed-loop system, not quantities derived from fitted inputs. The Rule Engine's action menu (Sec. 3.2.1) and the benchmark construction (Sec. 4.1) overlap in rule families (spacing, minimum-width, enclosure, extension, containment, overlap), so the test distribution is co-designed with the action space; this is a genuine threat to external validity and is partly conceded by the paper ('the engine does not generate other topology-changing actions'; 'broadening rule-deck coverage across technologies'). But it is not circularity: strict success is defined externally by Calibre nmDRC/nmLVS (Sec. 3.3.1), not by 'the menu contains the inverse perturbation,' and the random (54.4%) and heuristic (83.3%) baselines under the identical menu show that menu membership alone does not force the result. No parameter is fitted to the test set (LLMs are off-the-shelf, not fine-tuned), and no load-bearing self-citation appears in the reference list. The paper's own limitations confirm scope, but the 92.5% SSR claim remains an empirical finding about the evaluated distribution, not a tautology.

Axiom & Free-Parameter Ledger

4 free parameters · 3 axioms · 0 invented entities

No new physical entities are introduced. The framework relies on standard EDA tools and off-the-shelf LLMs. The main assumptions are that Calibre is ground truth, that the rule engine covers the benchmark's rule types, and that FreePDK45 layouts are representative of real repair tasks. The unnoted free parameters are search budgets and the temperature schedule, which are hand-tuned and could affect the headline numbers.

free parameters (4)

Global search cap (300 productive cycles) = 300
The budget cap is chosen by hand and bounds all runs; no sensitivity analysis is provided. It directly affects the trade-off between SSR and runtime.
Temperature schedule for LLM decoding = start 0.2, raised stepwise to at most 0.6
A heuristic schedule to encourage exploration after failures; not justified as optimal, and results may depend on it.
Per-node branch budget decay with depth and anchor-protection bonus = not specified exactly
The decay function and extra budget for improved states are not quantified. These control the search breadth and are load-bearing for the reported SSR.
Deterministic heuristic baseline lexicographic priority = violation coverage > primary class > smaller magnitude > tie-break
This baseline's strength is a free choice; the LLM's advantage may partly depend on how weak this heuristic is. It is defined ad hoc for the comparison.

axioms (3)

domain assumption Calibre nmDRC/nmLVS correctly reports all DRC violations and LVS mismatches
The framework treats Calibre as the ground truth (Sec 3.3.1). If the tool misses or misreports violations, the success metrics are affected.
domain assumption The Rule Engine's action menu is complete for the rule categories in the benchmark
Sec 3.2.1 states it only generates actions for spacing, minimum-width, enclosure, extension, containment, and overlap. The benchmark was deliberately constructed to be within this set, so this assumption holds by construction in the evaluation.
domain assumption FreePDK45 standard cells are representative of real physical-design DRC repair tasks
The test suite is derived from FreePDK45 (Sec 4.1). Generalization to other technologies/rule decks is untested and is acknowledged as a limitation in the conclusion.

pith-pipeline@v1.3.0-alltime-deepseek · 10929 in / 9179 out tokens · 95057 ms · 2026-08-01T06:33:11.297641+00:00 · methodology

0 comments

read the original abstract

Resolving Design Rule Violations (DRVs) in layouts entails an iterative loop of geometric edits and verification. We present DRC-Aid, a closed-loop agentic framework that automates local DRC repair by formulating it as verification-in-the-loop search. To constrain the combinatorial geometric repair space, a deterministic Rule Engine converts physical verification tool-reported violations into a bounded menu of geometric edits. An off-the-shelf Large Language Model (LLM) evaluates local geometric context to select edits from this menu, with budgeted depth-first search and backtracking. Immediate feedback from verification tools such as Calibre nmDRC/nmLVS enforces geometric compliance and guards against electrical-topology degradation, while a global Memory Bank prevents cyclic re-exploration. Evaluated on FreePDK45 layouts containing DRVs, DRC-Aid achieves DRC-clean, LVS-equivalent repairs in ~92.5% of cases with a ~98% total violation reduction, while residual cases yield partially repaired LVS-equivalent candidates. Under an identical search and verification infrastructure, LLM-based selection outperforms random (54.4%) and deterministic-heuristic (83.3%) policies, with the gap widening on cases with six or more violations.

Figures

Figures reproduced from arXiv: 2607.22761 by Anushka Mukherjee, Kang He, Kaushik Roy.

**Figure 1.** Figure 1: a) Iterative Search Exploration Loop of DRC-Aid b) Overview of the DRC-Aid Framework c) Illustrations of the [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗

**Figure 2.** Figure 2: a) Connectivity Engine actions b) Dynamic Prompt [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

discussion (0)

Reference graph

Works this paper leans on

22 extracted references · 2 canonical work pages

[1]

Chen-Chia Chang, Chia-Tung Ho, Yaguang Li, Yiran Chen, and Haoxing Ren. 2025. DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent. InProceedings of the 2025 International Symposium on Physical Design (Austin, TX, USA)(ISPD ’25). Association for Computing Machinery, New York, NY, USA, 143–151. doi:10.1145/3698364.3705347

arXiv 2025
[2]

Kahng, Sayak Kundu, and Bodhisatta Pramanik

Amur Ghose, Andrew B. Kahng, Sayak Kundu, and Bodhisatta Pramanik. 2026. Invited: Agentic AI for Physical Design R&D: Status and Prospects. InProceedings of the 2026 International Symposium on Physical Design(Germany)(ISPD ’26). 6 Association for Computing Machinery, New York, NY, USA, 133–141. doi:10. 1145/3764386.3779612

arXiv 2026
[3]

Google AI for Developers. 2026. Gemma 4 model card. https://ai.google.dev/ gemma/docs/core/model_card_4

2026
[4]

Khandakar Shakib Al Hasan, Syed Rifat Raiyan, Hasin Mahtab Alvee, and Wahid Sadik. 2026. CircuitLM: A Multi-Agent LLM-Aided Design Frame- work for Generating Circuit Schematics from Natural Language Prompts. arXiv:2601.04505 [cs.AI] https://arxiv.org/abs/2601.04505

Pith/arXiv arXiv 2026
[5]

Zhuolun He and Bei Yu. 2024. Large Language Models for EDA: Future or Mirage?. InProceedings of the 2024 International Symposium on Physical Design(Taipei, Taiwan)(ISPD ’24). Association for Computing Machinery, New York, NY, USA, 65–66. doi:10.1145/3626184.3639700

arXiv 2024
[6]

Wenli Huang, Bin Li, Wenchao Liu, Zhaohui Wu, Zonghan Lei, Songting Huang, and Chaozheng Qin. 2025. A DRC Automatic Repair Strategy for Standard Cell Layout Based on Improved Simulated Annealing Algorithm.Electronics14, 21 (2025). doi:10.3390/electronics14214267

work page doi:10.3390/electronics14214267 2025
[7]

Wei-Tse Hung, Jun-Yang Huang, Yih-Chih Chou, Cheng-Hong Tsai, and Mango Chao. 2020. Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network. InProceedings of the 2020 International Sympo- sium on Physical Design(Taipei, Taiwan)(ISPD ’20). Association for Computing Machinery, New York, NY, USA, 57–64. doi:10.1145/3372780.3375557

arXiv 2020
[8]

Riadul Islam and Dhandeep Challagundla. 2025. Pre-Global Routing DRC Vi- olation Prediction Using Unsupervised Learning. In2025 23rd IEEE Interre- gional NEWCAS Conference (NEWCAS). 450–454. doi:10.1109/NewCAS64648. 2025.11107147

arXiv 2025
[9]

Sungyu Jeong, Chanhyong Lee, Minsu Kim, Iksu Jang, Myungguk Lee, Junung Choi, and Byungsub Kim. 2024. A Layout-to-Generator Conversion Framework With Graphical User Interface for Visual Programming of Analog Layout Gener- ators.IEEE Access12 (2024), 125942–125954. doi:10.1109/ACCESS.2024.3409738

arXiv 2024
[10]

Kahng, J

A.B. Kahng, J. Lienig, I.L. Markov, and J. Hu. 2011.VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer Berlin. https://books.google.com/ books?id=DWUGHyFVpboC

2011
[11]

Kahng, Lutong Wang, and Bangqi Xu

Andrew B. Kahng, Lutong Wang, and Bangqi Xu. 2022. TritonRoute-WXL: The Open-Source Router With Integrated DRC Engine.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems41, 4 (2022), 1076–1089. doi:10.1109/TCAD.2021.3079268

arXiv 2022
[12]

Woosuk Kwon, Zhuohan Li, Siyuan Zhuang, Ying Sheng, Lianmin Zheng, Cody Hao Yu, Joseph Gonzalez, Hao Zhang, and Ion Stoica. 2023. Efficient Memory Management for Large Language Model Serving with PagedAttention. InProceedings of the 29th Symposium on Operating Systems Principles(Koblenz, Germany)(SOSP ’23). Association for Computing Machinery, New York, N...

arXiv 2023
[13]

Lavagno, G

L. Lavagno, G. Martin, I.L. Markov, and L.K. Scheffer (Eds.). 2016.Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology. CRC Press. https://doi.org/10.1201/9781315215112

work page doi:10.1201/9781315215112 2016
[14]

Shuowei Li, Ckristian Duran, Ritaro Takenaka, and Tetsuya Iizuka. 2025. Fully- Standard-Cell-Based Synthesizable Charge-Redistribution SAR ADCs and P&R- Based Layout Automation Framework.IEEE Access13 (2025), 83450–83469. doi:10.1109/ACCESS.2025.3569273

arXiv 2025
[15]

Jhen-Gang Lin, Yu-Guang Chen, Yun-Wei Yang, Wei-Tse Hung, Cheng-Hong Tsai, De-Shiun Fu, and Mango Chia-Tso Chao. 2023. DRC Violation Prediction with Pre- global-routing Features Through Convolutional Neural Network. InProceedings of the Great Lakes Symposium on VLSI 2023(Knoxville, TN, USA)(GLSVLSI ’23). Association for Computing Machinery, New York, NY, ...

arXiv 2023
[16]

Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, Yibo Lin, Runsheng Wang, and Ru Huang. 2025. LayoutCopilot: An LLM-Powered Multiagent Collaborative Framework for Interactive Analog Layout Design.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems44, 8 (2025), 3126–3139. doi:10.1109/TCAD.2025.3529805

arXiv 2025
[17]

Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Pinck- ney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Ankit Ji...

Pith/arXiv arXiv 2024
[18]

Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, and Zhiyao Xie. 2025. RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems44, 4 (2025), 1448–1461. doi:10.1109/TCAD.2024. 3483089

doi:10.1109/tcad.2024 2025
[19]

Haoxing Ren and Matthew Fojtik. 2021. Invited- NVCell: Standard Cell Lay- out in Advanced Technology Nodes with Reinforcement Learning. In2021 58th ACM/IEEE Design Automation Conference (DAC). 1291–1294. doi:10.1109/ DAC18074.2021.9586188

arXiv 2021
[20]

Stine, Ivan Castellanos, Michael Wood, Jeff Henson, Fred Love, W

James E. Stine, Ivan Castellanos, Michael Wood, Jeff Henson, Fred Love, W. Rhett Davis, Paul D. Franzon, Michael Bucher, Sunil Basavarajaiah, Julie Oh, and Ravi Jenkal. 2007. FreePDK: An Open-Source Variation-Aware Design Kit. In2007 IEEE International Conference on Microelectronic Systems Education (MSE’07). 173–174. doi:10.1109/MSE.2007.44

doi:10.1109/mse.2007.44 2007
[21]

Shailja Thakur, Jason Blocklove, Hammond Pearce, Benjamin Tan, Siddharth Garg, and Ramesh Karri. 2024. AutoChip: Automating HDL Generation Using LLM Feedback. arXiv:2311.04887 [cs.PL] https://arxiv.org/abs/2311.04887

Pith/arXiv arXiv 2024
[22]

An Yang, Anfeng Li, Baosong Yang, Beichen Zhang, Binyuan Hui, Bo Zheng, Bowen Yu, Chang Gao, Chengen Huang, Chenxu Lv, Chujie Zheng, Dayiheng Liu, Fan Zhou, Fei Huang, Feng Hu, Hao Ge, Haoran Wei, Huan Lin, Jialong Tang, Jian Yang, Jianhong Tu, Jianwei Zhang, Jianxin Yang, Jiaxi Yang, Jing Zhou, Jingren Zhou, Junyang Lin, Kai Dang, Keqin Bao, Kexin Yang, ...

Pith/arXiv arXiv 2025

[1] [1]

Chen-Chia Chang, Chia-Tung Ho, Yaguang Li, Yiran Chen, and Haoxing Ren. 2025. DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent. InProceedings of the 2025 International Symposium on Physical Design (Austin, TX, USA)(ISPD ’25). Association for Computing Machinery, New York, NY, USA, 143–151. doi:10.1145/3698364.3705347

arXiv 2025

[2] [2]

Kahng, Sayak Kundu, and Bodhisatta Pramanik

Amur Ghose, Andrew B. Kahng, Sayak Kundu, and Bodhisatta Pramanik. 2026. Invited: Agentic AI for Physical Design R&D: Status and Prospects. InProceedings of the 2026 International Symposium on Physical Design(Germany)(ISPD ’26). 6 Association for Computing Machinery, New York, NY, USA, 133–141. doi:10. 1145/3764386.3779612

arXiv 2026

[3] [3]

Google AI for Developers. 2026. Gemma 4 model card. https://ai.google.dev/ gemma/docs/core/model_card_4

2026

[4] [4]

Khandakar Shakib Al Hasan, Syed Rifat Raiyan, Hasin Mahtab Alvee, and Wahid Sadik. 2026. CircuitLM: A Multi-Agent LLM-Aided Design Frame- work for Generating Circuit Schematics from Natural Language Prompts. arXiv:2601.04505 [cs.AI] https://arxiv.org/abs/2601.04505

Pith/arXiv arXiv 2026

[5] [5]

Zhuolun He and Bei Yu. 2024. Large Language Models for EDA: Future or Mirage?. InProceedings of the 2024 International Symposium on Physical Design(Taipei, Taiwan)(ISPD ’24). Association for Computing Machinery, New York, NY, USA, 65–66. doi:10.1145/3626184.3639700

arXiv 2024

[6] [6]

Wenli Huang, Bin Li, Wenchao Liu, Zhaohui Wu, Zonghan Lei, Songting Huang, and Chaozheng Qin. 2025. A DRC Automatic Repair Strategy for Standard Cell Layout Based on Improved Simulated Annealing Algorithm.Electronics14, 21 (2025). doi:10.3390/electronics14214267

work page doi:10.3390/electronics14214267 2025

[7] [7]

Wei-Tse Hung, Jun-Yang Huang, Yih-Chih Chou, Cheng-Hong Tsai, and Mango Chao. 2020. Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network. InProceedings of the 2020 International Sympo- sium on Physical Design(Taipei, Taiwan)(ISPD ’20). Association for Computing Machinery, New York, NY, USA, 57–64. doi:10.1145/3372780.3375557

arXiv 2020

[8] [8]

Riadul Islam and Dhandeep Challagundla. 2025. Pre-Global Routing DRC Vi- olation Prediction Using Unsupervised Learning. In2025 23rd IEEE Interre- gional NEWCAS Conference (NEWCAS). 450–454. doi:10.1109/NewCAS64648. 2025.11107147

arXiv 2025

[9] [9]

Sungyu Jeong, Chanhyong Lee, Minsu Kim, Iksu Jang, Myungguk Lee, Junung Choi, and Byungsub Kim. 2024. A Layout-to-Generator Conversion Framework With Graphical User Interface for Visual Programming of Analog Layout Gener- ators.IEEE Access12 (2024), 125942–125954. doi:10.1109/ACCESS.2024.3409738

arXiv 2024

[10] [10]

Kahng, J

A.B. Kahng, J. Lienig, I.L. Markov, and J. Hu. 2011.VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer Berlin. https://books.google.com/ books?id=DWUGHyFVpboC

2011

[11] [11]

Kahng, Lutong Wang, and Bangqi Xu

Andrew B. Kahng, Lutong Wang, and Bangqi Xu. 2022. TritonRoute-WXL: The Open-Source Router With Integrated DRC Engine.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems41, 4 (2022), 1076–1089. doi:10.1109/TCAD.2021.3079268

arXiv 2022

[12] [12]

Woosuk Kwon, Zhuohan Li, Siyuan Zhuang, Ying Sheng, Lianmin Zheng, Cody Hao Yu, Joseph Gonzalez, Hao Zhang, and Ion Stoica. 2023. Efficient Memory Management for Large Language Model Serving with PagedAttention. InProceedings of the 29th Symposium on Operating Systems Principles(Koblenz, Germany)(SOSP ’23). Association for Computing Machinery, New York, N...

arXiv 2023

[13] [13]

Lavagno, G

L. Lavagno, G. Martin, I.L. Markov, and L.K. Scheffer (Eds.). 2016.Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology. CRC Press. https://doi.org/10.1201/9781315215112

work page doi:10.1201/9781315215112 2016

[14] [14]

Shuowei Li, Ckristian Duran, Ritaro Takenaka, and Tetsuya Iizuka. 2025. Fully- Standard-Cell-Based Synthesizable Charge-Redistribution SAR ADCs and P&R- Based Layout Automation Framework.IEEE Access13 (2025), 83450–83469. doi:10.1109/ACCESS.2025.3569273

arXiv 2025

[15] [15]

Jhen-Gang Lin, Yu-Guang Chen, Yun-Wei Yang, Wei-Tse Hung, Cheng-Hong Tsai, De-Shiun Fu, and Mango Chia-Tso Chao. 2023. DRC Violation Prediction with Pre- global-routing Features Through Convolutional Neural Network. InProceedings of the Great Lakes Symposium on VLSI 2023(Knoxville, TN, USA)(GLSVLSI ’23). Association for Computing Machinery, New York, NY, ...

arXiv 2023

[16] [16]

Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, Yibo Lin, Runsheng Wang, and Ru Huang. 2025. LayoutCopilot: An LLM-Powered Multiagent Collaborative Framework for Interactive Analog Layout Design.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems44, 8 (2025), 3126–3139. doi:10.1109/TCAD.2025.3529805

arXiv 2025

[17] [17]

Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Pinck- ney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Ankit Ji...

Pith/arXiv arXiv 2024

[18] [18]

Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, and Zhiyao Xie. 2025. RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems44, 4 (2025), 1448–1461. doi:10.1109/TCAD.2024. 3483089

doi:10.1109/tcad.2024 2025

[19] [19]

Haoxing Ren and Matthew Fojtik. 2021. Invited- NVCell: Standard Cell Lay- out in Advanced Technology Nodes with Reinforcement Learning. In2021 58th ACM/IEEE Design Automation Conference (DAC). 1291–1294. doi:10.1109/ DAC18074.2021.9586188

arXiv 2021

[20] [20]

Stine, Ivan Castellanos, Michael Wood, Jeff Henson, Fred Love, W

James E. Stine, Ivan Castellanos, Michael Wood, Jeff Henson, Fred Love, W. Rhett Davis, Paul D. Franzon, Michael Bucher, Sunil Basavarajaiah, Julie Oh, and Ravi Jenkal. 2007. FreePDK: An Open-Source Variation-Aware Design Kit. In2007 IEEE International Conference on Microelectronic Systems Education (MSE’07). 173–174. doi:10.1109/MSE.2007.44

doi:10.1109/mse.2007.44 2007

[21] [21]

Shailja Thakur, Jason Blocklove, Hammond Pearce, Benjamin Tan, Siddharth Garg, and Ramesh Karri. 2024. AutoChip: Automating HDL Generation Using LLM Feedback. arXiv:2311.04887 [cs.PL] https://arxiv.org/abs/2311.04887

Pith/arXiv arXiv 2024

[22] [22]

An Yang, Anfeng Li, Baosong Yang, Beichen Zhang, Binyuan Hui, Bo Zheng, Bowen Yu, Chang Gao, Chengen Huang, Chenxu Lv, Chujie Zheng, Dayiheng Liu, Fan Zhou, Fei Huang, Feng Hu, Hao Ge, Haoran Wei, Huan Lin, Jialong Tang, Jian Yang, Jianhong Tu, Jianwei Zhang, Jianxin Yang, Jiaxi Yang, Jing Zhou, Jingren Zhou, Junyang Lin, Kai Dang, Keqin Bao, Kexin Yang, ...

Pith/arXiv arXiv 2025