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REVIEW 4 major objections 5 minor 48 references

A 23-stage pipelined FPGA design keeps fully-connected probabilistic Ising machines running at 300 MHz, delivering an order-of-magnitude higher update throughput than a non-pipelined baseline at the same degree of parallelization.

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A 23-stage pipelined FPGA probability-bit engine keeps fully-connected Ising machine updates flowing at 300 MHz, giving about a 10x throughput gain over a non-pipelined design at equal parallelism.

T0 review reviewed 2026-08-01 challenge →

load-bearing objection A genuinely useful pipelined FPGA PIM for dense Ising problems, with measured 300 MHz operation; the main caveat is that the stall-free schedule is asserted rather than proven, though the 512-p-bit measurements back it up for the tested configurations. the 4 major comments →

arxiv 2607.21077 v1 pith:3AQ3U4PW submitted 2026-07-23 eess.SY cs.SY

A scalable and resource-efficient pipelined p-computer for probabilistic Ising machines

Deborah Volpe , Eleonora Raimondo , Andrea Grimaldi , Pedram Khalili Amiri , Stefano Chiappini , Anna Giordano , Mario Carpentieri , Hyunsoo Yang
show 2 more authors
Massimo Chiappini Giovanni Finocchio
This is my paper
classification eess.SY cs.SY
keywords probabilistic Ising machinep-bitsFPGApipeline architecturelocal-field updatefully-connected Ising modelcombinatorial optimizationLDPC decoding
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper argues that the bottleneck for dense, fully-connected probabilistic Ising machines on FPGAs — the local-field update step — can be removed by deep pipelining instead of by adding parallel hardware. It reports a 23-stage pipelined p-bit update path that overlaps spin evaluation with local-field updates, keeping the pipeline continuously filled, and a bandwidth-aware on-chip memory organization for coupling and bias matrices. The result, on an AMD ZCU106 board, is a 300 MHz clock (versus 40 MHz for an optimized non-pipelined baseline) and more than an order-of-magnitude higher update throughput at the same degree of parallelization, with logic area growing with parallelism rather than problem size. If correct, this makes native all-to-all Ising problems practical on reconfigurable hardware without sparsification or graph embedding.

Core claim

The paper's central claim is that a deeply pipelined update engine (23 stages in the validated design) lets a fully-connected probabilistic Ising machine sustain high update rates on dense problems using only a moderate, configurable degree of parallelization. The pipeline splits the critical path that limited the non-pipelined baseline to 40 MHz, and reorders local-field updates so the next p-bit evaluation can begin once its own field is ready, without waiting for the full update phase. A new local-field update starts every clock cycle, keeping the pipeline continuously filled, with strictly sequential p-bit sampling preserved. At fixed DOP the design reports over an order-of-magnitude hig

What carries the argument

The carrying mechanism is the 23-stage pipelined p-bit update path, which overlaps the two phases that a non-pipelined design runs sequentially: evaluating whether a spin flips (random comparison with tanh of the local field) and updating the local fields and energy for all other spins. The schedule prioritizes the update of p-bit i+1, so the next evaluation can begin as soon as that field is ready while remaining updates proceed in the background. The design is completed by a bandwidth-aware on-chip memory hierarchy — shared and paged memories, multi-row banking, symmetry-aware reuse, word packing — that streams coupling coefficients from Block RAM at one element per cycle per DOP, avoiding

Load-bearing premise

The load-bearing assumption is that the pipeline stays continuously filled and that the reordered local-field updates preserve exactly the sequential p-bit update order; if stalls appear as problem size grows, or if the reordering changes the effective sampling order, the order-of-magnitude throughput gain and the equivalence to software PIM sampling both fail.

What would settle it

Measure the p-bit update rate as a function of problem size N while holding DOP fixed past the synthesized range (e.g., N = 4096 or 8192 on a larger FPGA): if throughput falls proportionally to N/DOP rather than remaining near the 300 MHz limit, the pipeline is stalling and the central claim is refuted. Alternatively, run the pipelined design and a strictly sequential software PIM on the same dense instance and compare the distribution of spin configurations (or an update-order-sensitive statistic) with a statistical test; a significant difference would falsify the claimed sampling equivalence

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • Dense Ising formulations (portfolio optimization, LDPC decoding, Max-Cut on dense graphs) can be accelerated on FPGAs without sparsification, graph embedding, or external memory in the update loop.
  • At fixed DOP, the pipelined architecture's throughput remains nearly flat as problem size grows, whereas the non-pipelined baseline degrades roughly as N/DOP; this changes the scaling strategy for larger p-bit counts.
  • Logic utilization scales primarily with the chosen DOP rather than with the number of p-bits, so a balanced operating point (about 30% of p-bits as DOP) gives near-peak throughput at a fraction of full-parallelism resources.
  • The energy per Monte Carlo sweep is lower (about 52% reduction on validated designs) because the higher clock frequency more than offsets the increased dynamic power.
  • The same architecture can host multiple independent replicas sharing the coupling and bias memories, enabling annealing schemes such as parallel tempering or simulated quantum annealing.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the stall-free pipeline behavior persists at sizes beyond the synthesized range, the 23-stage structure should transfer to an ASIC where fine-grained SRAM banking and clock gating could push frequency and energy efficiency beyond the FPGA demonstrator.
  • The paper's reordering argument suggests that a formal proof of equivalence between the reordered schedule and strictly sequential Gibbs sampling would elevate the empirical validation into a guarantee; absent such a proof, the sampling-order claim rests on experiments.
  • Because pipeline depth is a property of the arithmetic path rather than of problem size, the approach could extend naturally to higher-order Ising models by reorganizing coefficient storage around hyperedges, as the paper sketches.
  • A consequence the authors leave implicit is that the architecture's advantage grows with problem density: workloads whose Ising matrices are already sparse would gain less, since the baseline's memory bottleneck is less severe there.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper presents a pipelined FPGA implementation of a fully-connected probabilistic Ising machine (PIM). The architecture uses a 23-stage pipeline to overlap p-bit evaluation with local-field and energy updates, combined with bandwidth-aware on-chip memory organization, and reports operating frequencies up to 300 MHz on an AMD ZCU106, compared to 40 MHz for a non-pipelined baseline. The central claim is that at fixed degree of parallelization (DOP), the pipelined design delivers more than an order-of-magnitude higher update throughput, with application demonstrations on portfolio optimization and LDPC decoding. The paper includes board-level measurements for 512-p-bit designs, synthesis-based estimates for larger sizes, and projections beyond 1024 p-bits.

Significance. If the central claim holds, the work is a meaningful step toward scalable digital PIMs for dense, fully-connected optimization problems, a regime where previous FPGA implementations rely on sparsity, graph embedding, or external memory. The paper's strengths include clear validation-level taxonomy (implemented/measured/estimated/projected), fixed-DOP comparison protocols, and board-measured 512-p-bit results at 300 MHz vs 40 MHz. However, the main contribution rests on an asserted but not formally demonstrated pipeline-fill and ordering guarantee, and the energy claims are based on Vivado power estimates rather than board measurements. These load-bearing points need to be substantiated before the performance claims can be fully accepted.

major comments (4)
  1. [Results B, paragraph 2 ('Thanks to the pipelined organization...')] The claim that 'a new local field update is launched at every clock cycle, guaranteeing that the pipeline remains continuously filled' is not supported by a quantitative condition. In a fully-connected model, each accepted spin flip generates N local-field increments. With an evaluation issue interval of L_ev + L_up cycles and a throughput of DOP increments per cycle, a necessary condition for avoiding a growing backlog is DOP >= N/(L_ev+L_up). The manuscript never states or verifies this condition for the reported operating points. For example, at N=2048 with L_ev+L_up=23, DOP >= 89 would be required, yet the paper does not report a validated 2048-p-bit configuration at that DOP. Table 1 itself concedes that stalls occur when DOP and pipeline depth are not properly tuned. The central 'order-of-magnitude' throughput claim therefore depends on an unproven schedule property; a formal deriv
  2. [Results B, paragraph 2 ('By carefully scheduling memory accesses...')] The assertion that the architecture 'preserves strictly sequential-update sampling for any DOP' is load-bearing for the equivalence to the software PIM baseline, but no formal invariant or proof is provided. Reordering local-field updates to prioritize p-bit i+1 may change the effective order in which state changes are observed by subsequent evaluations. The paper does not show a cycle-level schedule or RTL to rule out silent reordering or dropped updates. The empirical agreement with software PIM on invertible logics and Max-Cut instances is encouraging but cannot certify the 'any DOP' claim. Please provide either a proof of the ordering invariant or a detailed schedule showing exactly when each local-field update is applied relative to each spin evaluation.
  3. [Fig. 4b and Summary/Conclusion energy statements] The energy per sweep reduction (52% on validated designs, 29% on projections) is computed from Vivado power estimates, not board-level power measurements. The paper's own taxonomy in Results says that 'Estimated' applies only to power, and the Summary notes that 'explicit energy measurements will be important.' Yet the Conclusion states that 'the architecture improves the sampling time of 10x and reduce the energy consumption' without this caveat. The abstract also omits the estimated nature of the energy result. Figure 4b should be clearly labeled as estimated, and the text should carry the same caveat in the abstract and conclusion.
  4. [Data availability / reproducibility] The central claim rests on a specific pipeline schedule and on the absence of stalls. No RTL, cycle-accurate simulation results, or schedule traces are provided; the data availability statement says 'available upon reasonable request' only. Given that the paper's main contribution is an architectural scheduling claim, the absence of any machine-checked schedule or released RTL prevents independent verification of the load-bearing assumption. At minimum, the authors should release the schedule pseudocode with precise L_ev and L_up values and measured cycle counts for the reported designs.
minor comments (5)
  1. [Results A, paragraph 1] Typo: '16/10/2-bit fixed-point coefficient for for J and h' should read 'for J and h'.
  2. [Results B, paragraph 1 / Fig. 1 caption] The quantities L_ev and L_up are introduced but their numerical values (in cycles) are never specified. The reader cannot verify the issue-interval formula L_ev + L_up without these values. Please report them for the 23-stage configuration.
  3. [Results C / Fig. 3 caption] The figure labels and text mix 'measured' and 'projected' points in the same plot. The validation-level taxonomy is helpful, but the main-text descriptions (e.g., 'Results above 512 p-bits are a projection') should be visually encoded in the figures themselves (e.g., dashed lines) for clarity.
  4. [Methods, Portfolio optimization] The abbreviation 'MQT QAO' is not defined. It appears to refer to a software library; please provide a reference or full name.
  5. [Discussion / Table 1] The comparison with prior PIMs is careful, but the 'Highest reported operating frequency' claim should be qualified by the fact that update primitives differ across architectures (as the paper itself notes in the paragraph before Summary). Please make that qualification explicit in the caption of Table 1 as well.

Circularity Check

0 steps flagged

No central circularity: measured clock/schedule comparison drives throughput; main gap is an unproven stall-free/ordering assumption, not a definitional or fitted reduction.

full rationale

The central throughput claim (Abstract; Conclusion: 'more than an order-of-magnitude higher update throughput ... at fixed parallelism') is obtained from a structural schedule comparison, not from fitting. Results B gives the issue intervals: 'In the pipelined design a new p-bit evaluation is issued every L_ev + L_up cycles, against L_ev + N/DOP for the non-pipelined baseline: this difference is the origin of the throughput advantage.' Together with the measured 300 MHz vs 40 MHz clocks (Results C), this is an analytic/experimental comparison and would be falsifiable by a different schedule. No fitted constant is renamed as a prediction. The self-citations ([22] Raimondo et al. as software PIM; [48] Volpe et al. for λ estimation) are used as references or external procedures, and the validation also uses public datasets, LDPC BER, and TTS, so they are not load-bearing premises that force the architecture claim. The main weakness is the asserted but unproven stall-free/ordering property: 'a new local field update is launched at every clock cycle, guaranteeing that the pipeline remains continuously filled' and 'the proposed architecture preserves strictly sequential-update sampling for any DOP' (Results B). The paper itself concedes 'if the degree of parallelism and pipeline depth are not properly tuned, stalls occur and peak throughput is not achieved' (Table 1). This is a correctness/verification gap that would invalidate the speedup if real, but it is not a circular reduction: the architecture's throughput formula does not assume the truth of the sequential-sampling claim as its input. I therefore find no definitional self-consistency, fitted-input-as-prediction, or author-imported uniqueness; score 2 reflects minor same-group references and an unproven scheduling assumption, not load-bearing circularity.

Axiom & Free-Parameter Ledger

5 free parameters · 4 axioms · 0 invented entities

The central result is a measurement/synthesis claim, so the ledger mainly records design and benchmark parameters. No new physical entities are introduced.

free parameters (5)
  • Degree of parallelization (DOP) = 2-512 depending on config; ~30% of N for Fig 4
    Controls number of J-coefficients read/processed per cycle; chosen per design; throughput and area trade-off.
  • Pipeline depth = 23 stages
    Minimum depth to meet 300 MHz at 16-bit coefficient and 32-bit accumulation on ZCU106; a design choice.
  • Portfolio risk-aversion q = 1
    Fixed for all portfolio instances; not optimized; affects benchmark mapping but not architecture claim.
  • LDPC parity weight alpha = 5
    Fixed for all LDPC instances; not optimized; affects benchmark mapping but not architecture claim.
  • Penalty weight lambda (portfolio budget and LDPC Rosenberg) = Per-instance via MQT QAO [48] / qubovert defaults
    Problem-mapping hyperparameters set by external libraries; not fitted to the hardware result.
axioms (4)
  • domain assumption p-bit update rule m_i(t+1) = sgn(rand(-1,+1) + tanh(I_i(t))) is the correct stochastic model for the hardware.
    Adopted from Refs [22,25] and used as the basis of the update path; hardware sampling quality is validated empirically, not proven.
  • domain assumption Pipelined reordering of local-field updates preserves strictly sequential p-bit state-update ordering.
    Asserted in Results B ('strictly sequential-update sampling for any DOP') with no formal proof; if false, the sampling distribution and solution quality claims would need revision.
  • domain assumption LUT/linearization tanh approximation and xoshiro128++ PRNG do not materially alter the target Boltzmann/annealing distribution.
    Implemented via approximations (Supplementary Notes 4-5); only empirical checks on selected benchmarks support this.
  • domain assumption Performance trends measured at 512/1024 p-bits extrapolate to 2048/4096/8192 p-bit projections.
    Figures 3-4 label larger sizes as 'projected'; the scalability claim depends on the extrapolation being valid.

reviewed 2026-08-01 · how reviews work

0 comments
Cite this review

Pith. "Pith review of A scalable and resource-efficient pipelined p-computer for probabilistic Ising machines." pith.science (2026). https://pith.science/paper/3AQ3U4PW

@misc{pith2026260721077,
  author       = {Pith},
  title        = {Pith review of: A scalable and resource-efficient pipelined p-computer for probabilistic Ising machines},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/3AQ3U4PW}},
  note         = {Machine review of arXiv:2607.21077}
}
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read the original abstract

Probabilistic Ising machines (PIMs) based on probabilistic bits offer a hardware-friendly route to solve combinatorial optimization problems, but most digital implementations achieve high throughput by exploiting sparse interactions. This limits their applicability to dense problems, for which memory bandwidth and data movement become the dominant bottlenecks. Here, we show a resource-efficient pipelined Field-Programmable Gate Array architecture enabling high-throughput execution of fully-connected PIMs while maintaining scalability and modularity. This architecture design combines a deeply pipelined (>20 stages) probabilistic bit update path, which overlaps spin evaluation and local-field updates, with a bandwidth-aware on-chip memory organization for the coupling and bias matrices. The architecture supports 512 p-bits with 16-bit fixed-point coefficients and 1024 and 2048 p-bits with 10-bit and 2-bit coefficients, respectively, and operates at up to 300 MHz. At fixed degree of parallelization, it delivers an order-of-magnitude higher update rate than an optimized non-pipelined baseline, while improving the time-area trade-off for dense workloads. Validation on portfolio optimization and low-density parity-check decoding shows close agreement with software references and substantial reductions in time-to-solution relative to the non-pipelined design, establishing pipelining as an effective route to scalable digital probabilistic computing for dense optimization problems.

Figures

Figures reproduced from arXiv: 2607.21077 by Andrea Grimaldi, Anna Giordano, Deborah Volpe, Eleonora Raimondo, Giovanni Finocchio, Hyunsoo Yang, Mario Carpentieri, Massimo Chiappini, Pedram Khalili Amiri, Stefano Chiappini.

Figure 1
Figure 1. Figure 1: a Block diagram of the portfolio optimization problem: given 𝑀 assets, the goal is to determine the optimal weights w that maximize the expected return (based on the mean historical assets return 𝑢), while minimizing the risk, quantified by the assets covariance matrix 𝑆. b Block diagram of the LDPC communication chain, including encoder, bit-to-symbol mapper, noisy read channel, and decoder. The decoding … view at source ↗

discussion (0)

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Reference graph

Works this paper leans on

48 extracted references · 10 canonical work pages

  1. [1]

    Chung, K.T. et al. (2025). Neural combinatorial optimization with reinforcement learning in industrial engineering: a survey. Artificial Intelligence Review. https://doi.org/10.1007/s10462-024-11045-1

    work page doi:10.1007/s10462-024-11045-1 2025

  2. [2]

    Volpe, D. et al. (2024). Quantum-compliant users scheduling optimization in joint transmission mobile access networks. Quantum Information Processing. https://doi.org/10.1007/s11128-024-04471-1

    work page doi:10.1007/s11128-024-04471-1 2024

  3. [3]

    Bauer, M. et al. (2007). Accurate multiple sequence-structure alignment of RNA sequences using combinatorial optimization. BMC Bioinformatics. https://doi.org/10.1186/1471-2105-8-271

    work page doi:10.1186/1471-2105-8-271 2007

  4. [4]

    Le et al

    Ngoc Bao, L. Le et al. (2018). Application of Combinatorial Optimization in Logistics. 2018 4th International Conference on Green Technology and Sustainable Development (GTSD). https://doi.org/10.1109/GTSD.2018.8595447

    arXiv 2018

  5. [5]

    Date, P. et al. (2021). QUBO formulations for training machine learning models. Scientific Reports. https://doi.org/10.1038/s41598-021-89461-4

    work page doi:10.1038/s41598-021-89461-4 2021

  6. [6]

    Istrail, S. (2000). Statistical mechanics, three-dimensionality and NP-completeness. Proceedings of the thirty-second annual ACM symposium on Theory of computing. https://doi.org/10.1145/335305.335316

    arXiv 2000

  7. [7]

    and Vygen, J

    Korte, B. and Vygen, J. (2008). Approximation Algorithms, in Combinatorial Optimization, Springer Berlin Heidelberg, Berlin, Heidelberg, pp. 393–437

    2008

  8. [8]

    Hartmanis, J. (1982). Computers and Intractability: A Guide to the Theory of NP- Completeness (Michael R. Garey and David S. Johnson). SIAM Review. https://doi.org/10.1137/1024022

    doi:10.1137/1024022 1982

  9. [9]

    Chicano, F. et al. (2016). Editorial for the Special Issue on Combinatorial Optimization Problems. Evolutionary Computation. https://doi.org/10.1162/EVCO_e_00192. 30

    work page doi:10.1162/evco_e_00192 2016

  10. [10]

    Bellitti, M. et al. (2021). Entropic barriers as a reason for hardness in both classical and quantum algorithms. Physical Review Research. https://doi.org/10.1103/PhysRevResearch.3.043015

    doi:10.1103/physrevresearch.3.043015 2021

  11. [11]

    Johnson, M.W. et al. (2011). Quantum annealing with manufactured spins. Nature. https://doi.org/10.1038/nature10012

    doi:10.1038/nature10012 2011

  12. [12]

    and Nishimori, H

    Kadowaki, T. and Nishimori, H. (1998). Quantum annealing in the transverse Ising model. Physical Review E. https://doi.org/10.1103/PhysRevE.58.5355

    doi:10.1103/physreve.58.5355 1998

  13. [13]

    Chou, J. et al. (2019). Analog Coupled Oscillator Based Weighted Ising Machine. Scientific Reports. https://doi.org/10.1038/s41598-019-49699-5

    doi:10.1038/s41598-019-49699-5 2019

  14. [14]

    Ansari, M.S. et al. (2024). A comparison of Oscillatory Ising Machines and Simulated Bifurcation Machines for Solving Maximum Cut Problems. 2024 IEEE 24th International Conference on Nanotechnology (NANO). https://doi.org/10.1109/NANO61778.2024.10628622

    arXiv 2024

  15. [15]

    Cılasun, H. et al. (2025). A coupled-oscillator-based Ising chip for combinatorial optimization. Nature Electronics. https://doi.org/10.1038/s41928-025-01393-3

    doi:10.1038/s41928-025-01393-3 2025

  16. [16]

    Tatsumura, K. et al. (2019). FPGA-Based Simulated Bifurcation Machine. 2019 29th International Conference on Field Programmable Logic and Applications (FPL). https://doi.org/10.1109/FPL.2019.00019

    arXiv 2019

  17. [17]

    Goto, H. et al. (2019). Combinatorial optimization by simulating adiabatic bifurcations in nonlinear Hamiltonian systems. Science Advances. https://doi.org/10.1126/sciadv.aav2372

    doi:10.1126/sciadv.aav2372 2019

  18. [18]

    Tatsumura, K. et al. (2021). Scaling out Ising machines using a multi-chip architecture for simulated bifurcation. Nature Electronics. https://doi.org/10.1038/s41928-021- 00546-4

    work page doi:10.1038/s41928-021- 2021

  19. [19]

    Pervaiz, A.Z. et al. (2019). Weighted $p$ -Bits for FPGA Implementation of Probabilistic Circuits. IEEE Transactions on Neural Networks and Learning Systems. https://doi.org/10.1109/TNNLS.2018.2874565

    arXiv 2019

  20. [20]

    Camsari, K.Y. (2024). Probabilistic Computing with p-Bits: Optimization, Machine Learning and Quantum Simulation. 2024 IEEE International Magnetic Conference - Short papers (INTERMAG Short papers). https://doi.org/10.1109/INTERMAGShortPapers61879.2024.10576747

    arXiv 2024

  21. [21]

    Sun, L. et al. (2025). General oscillator-based Ising-machine models with phase- amplitude dynamics and polynomial interactions. Physical Review Applied. https://doi.org/10.1103/7s4v-4hs4

    work page doi:10.1103/7s4v-4hs4 2025

  22. [22]

    Raimondo, E. et al. (2025). High-Performance and Reliable Probabilistic Ising Machine Based on Simulated Quantum Annealing. Physical Review X. https://doi.org/10.1103/pcmz-w776

    doi:10.1103/pcmz-w776 2025

  23. [23]

    Yang, S. et al. (2025). 250 Magnetic Tunnel Junctions-Based Probabilistic Ising Machine

    2025

  24. [24]

    Grimaldi, A. et al. (2023). Evaluating Spintronics-Compatible Implementations of Ising Machines. Physical Review Applied. https://doi.org/10.1103/PhysRevApplied.20.024005

    doi:10.1103/physrevapplied.20.024005 2023

  25. [25]

    Aadit, N.A. et al. (2022). Massively parallel probabilistic computing with sparse Ising machines. Nature Electronics. https://doi.org/10.1038/s41928-022-00774-2

    doi:10.1038/s41928-022-00774-2 2022

  26. [26]

    Zhang, T. et al. (2024). A Review of Ising Machines Implemented in Conventional and Emerging Technologies. IEEE Transactions on Nanotechnology. https://doi.org/10.1109/TNANO.2024.3457533

    arXiv 2024

  27. [27]

    Mohseni, N. et al. (2022). Ising machines as hardware solvers of combinatorial optimization problems. Nature Reviews Physics. https://doi.org/10.1038/s42254-022- 00440-8. 31

    doi:10.1038/s42254-022- 2022

  28. [28]

    Minamisawa, A. et al. (2019). High-speed Sparse Ising Model on FPGA. 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS). https://doi.org/10.1109/MWSCAS.2019.8885105

    arXiv 2019

  29. [29]

    Zhang, T. et al. (2022). A Review of Simulation Algorithms of Classical Ising Machines for Combinatorial optimization. 2022 IEEE International Symposium on Circuits and Systems (ISCAS). https://doi.org/10.1109/ISCAS48785.2022.9937767

    arXiv 2022

  30. [30]

    Vengalam, U.K.R. et al. (2023). Efficient LDPC Decoding using Physical Computation

    2023

  31. [31]

    Buonaiuto, G. et al. (2023). Best practices for portfolio optimization by quantum computing, experimented on real quantum devices. Scientific Reports. https://doi.org/10.1038/s41598-023-45392-w

    doi:10.1038/s41598-023-45392-w 2023

  32. [32]

    Loiola, E.M. et al. (2007). A survey for the quadratic assignment problem. European Journal of Operational Research. https://doi.org/10.1016/j.ejor.2005.09.032

    work page doi:10.1016/j.ejor.2005.09.032 2007

  33. [33]

    Könz, M.S. et al. (2021). Embedding Overhead Scaling of Optimization Problems in Quantum Annealing. PRX Quantum. https://doi.org/10.1103/PRXQuantum.2.040322

    work page doi:10.1103/prxquantum.2.040322 2021

  34. [34]

    Maruyama, N. et al. (2025). Graph minor embedding can affect sampling degenerate ground states using quantum annealing. https://doi.org/10.7566/JPSJ.95.013002

    work page doi:10.7566/jpsj.95.013002 2025

  35. [35]

    and Wagner, F

    Stopfer, E. and Wagner, F. (2025). Quantum Portfolio Optimization: An Extensive Benchmark

    2025

  36. [36]

    and Lemieux, G.G.F

    Abdelhadi, A.M.S. and Lemieux, G.G.F. (2014). Modular multi-ported SRAM-based memories. Proceedings of the 2014 ACM/SIGDA international symposium on Field- programmable gate arrays. https://doi.org/10.1145/2554688.2554773

    arXiv 2014

  37. [37]

    Magar, K. et al. (2024). pc-COP: An Efficient and Configurable 2048-p-Bit Fully- Connected Probabilistic Computing Accelerator for Combinatorial Optimization. 2024 IEEE High Performance Extreme Computing Conference (HPEC). https://doi.org/10.1109/HPEC62836.2024.10938509

    arXiv 2024

  38. [38]

    Chowdhury, S. et al. (2025). Pushing the boundary of quantum advantage in hard combinatorial optimization with probabilistic computers. Nature Communications. https://doi.org/10.1038/s41467-025-64235-y

    doi:10.1038/s41467-025-64235-y 2025

  39. [39]

    Okuyama, T. et al. (2019). Binary optimization by momentum annealing. Physical Review E. https://doi.org/10.1103/PhysRevE.100.012111

    doi:10.1103/physreve.100.012111 2019

  40. [40]

    Duffee, C. et al. (2025). P -dits: Probabilistic d -dimensional bits for extended-variable probabilistic computing. Physical Review Applied. https://doi.org/10.1103/4ngx-cmz7

    doi:10.1103/4ngx-cmz7 2025

  41. [41]

    Ash BellettPortfolio Optimisation Dataset

  42. [42]

    Hicham Janati (2020). pyldpc

    2020

  43. [43]

    Boutros, A. et al. (2025). Field-Programmable Gate Array Architecture for Deep Learning: Survey and Future Directions. Proceedings of the IEEE. https://doi.org/10.1109/JPROC.2025.3623023

    arXiv 2025

  44. [44]

    Srinivasa, S. et al. (2021). Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation. 2021 22nd International Symposium on Quality Electronic Design (ISQED). https://doi.org/10.1109/ISQED51717.2021.9424263

    arXiv 2021

  45. [45]

    Orlandi, G. et al. (2025). Enabling fully connected probabilistic computing through a fast pipelined multi-operand adder. 2025 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). https://doi.org/10.1109/ISVLSI65124.2025.11130252

    arXiv 2025

  46. [46]

    Nikhar, S. et al. (2024). All-to-all reconfigurability with sparse and higher-order Ising machines. Nature Communications. https://doi.org/10.1038/s41467-024-53270-w

    doi:10.1038/s41467-024-53270-w 2024

  47. [47]

    Tamura, K. et al. (2021). Performance Comparison of Typical Binary-Integer Encodings in an Ising Machine. IEEE Access. https://doi.org/10.1109/ACCESS.2021.3081685. 32

    arXiv 2021

  48. [48]

    Volpe, D. et al. (2024). Towards an Automatic Framework for Solving Optimization Problems with Quantum Computers. 2024 IEEE International Conference on Quantum Software (QSW). https://doi.org/10.1109/QSW62656.2024.00019. Supporting Information Supporting Information is available from the author

    arXiv 2024

This paper was first reviewed by deepseek-v4-flash on August 1, 2026.