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RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

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arxiv 2312.08617 v5 pith:3HS7B7BT submitted 2023-12-14 cs.PL cs.AR

Shang Liu , Wenji Fang , Yao Lu , Qijun Zhang , Hongce Zhang , Zhiyao Xie This is my paper
classification cs.PLcs.AR
keywords generationopen-sourcecodellmscustomizeddatasetdesigngpt-3
verification ladder T0 review T1 audit T2 compute T3 formal
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The automatic generation of RTL code (e.g., Verilog) using natural language instructions and large language models (LLMs) has attracted significant research interest recently. However, most existing approaches heavily rely on commercial LLMs such as ChatGPT, while open-source LLMs tailored for this specific design generation task exhibit notably inferior performance. The absence of high-quality open-source solutions restricts the flexibility and data privacy of this emerging technique. In this study, we present a new customized LLM solution with a modest parameter count of only 7B, achieving better performance than GPT-3.5 on all representative benchmarks for RTL code generation. Especially, it outperforms GPT-4 in VerilogEval Machine benchmark. This remarkable balance between accuracy and efficiency is made possible by leveraging our new RTL code dataset and a customized LLM algorithm, both of which have been made fully open-source.

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Cited by 5 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. MACO: A Multi-Agent LLM Framework for Automated CGRA Hardware/Software Co-Design

    cs.AR 2025-09 reject novelty 6.0 of 10

    A multi-agent LLM framework that iteratively co-designs CGRA hardware and software parameters, reporting power and performance improvements over LLM and manual baselines.

  2. SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits

    cs.LG 2025-08 conditional novelty 6.0 of 10

    SynCircuit generates new, structurally valid RTL circuits with a directed-cyclic-graph diffusion model plus post-processing and MCTS, and shows they improve ML-based PPA prediction when added to training data.

  3. RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

    cs.LG 2025-07 conditional novelty 6.0 of 10

    RealBench measures LLM Verilog generation on complex open-source IP cores with formal verification, and all tested models score near zero on full system designs.

  4. VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs

    cs.SE 2025-07 conditional novelty 5.0 of 10

    A multi-role LLM prompting framework with PPA-aware in-context learning reports 25/29 functional correctness on RTLLM and up to 88% power, 76% area, and 73% timing gains over its own baseline.

  5. QiMeng: Fully Automated Hardware and Software Design for Processor Chip

    cs.AR 2025-06 conditional novelty 4.0 of 10

    QiMeng is a proposed three-layer architecture for automating processor hardware and software design, with several published components but no integrated implementation yet.

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