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REVIEW 5 major objections 5 minor 56 references

InterPlace selects inter-chip coupler placements with a multi-objective cost model that lowers on-chip SWAP and inter-chip operation counts, improving circuit fidelity by up to 53% on simulated multi-chip systems.

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InterPlace selects inter-chip coupler placements in modular quantum systems via a multi-objective cost model, cutting SWAPs and inter-chip operations by up to 33.3% and boosting simulated fidelity by up to 53.0%.

T0 review reviewed 2026-08-04 challenge →

load-bearing objection Plausible co-design idea for coupler placement, but the evaluation is circular and the headline 53% fidelity gain is arithmetically inconsistent; worth refereeing after a major revision. the 5 major comments →

arxiv 2509.10409 v1 pith:44YKTGEM submitted 2025-09-12 quant-ph

Optimizing Inter-chip Coupler Link Placement for Modular and Chiplet Quantum Systems

Zefan Du , Pedro Chumpitaz Flores , Wenqi Wei , Juntao Chen , Kaixun Hua , Ying Mao This is my paper
classification quant-ph
keywords quantum computingmodular quantum systemschiplet architectureinter-chip coupler placementqubit mappingcost modeltime-to-fidelityfidelity optimization
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

InterPlace is a pre-fabrication framework for deciding where inter-chip couplers should connect qubits in modular or chiplet quantum systems. It models the placement choice as a constrained network design problem and scores candidate link sets with a weighted cost function that includes average routing distance, fidelity-aware latency, congestion, per-qubit degree limits, and spatial sparsity. The paper claims that lower InterPlace cost predicts fewer on-chip SWAP gates and inter-chip operations across several compilers, and that the lowest-cost placement yields up to 53.0% higher fidelity and 33.3% fewer combined operations than high-cost baseline placements. These claims matter because current design practice treats coupler placement as a packaging decision rather than something that co-optimizes with compiler behavior; if the cost model is right, chip architects can choose link locations before fabrication and let compilers benefit immediately.

Core claim

InterPlace's central claim is that inter-chip coupler placement can be optimized before fabrication by minimizing a global cost function, and that doing so improves system-level performance in a way no compiler can fully recover later. Each candidate pair of qubits (u,v) across two chips is assigned a per-pair Time-to-Fidelity value, AvgTTFpair(u,v)=TTF_A(u)+TTF_coupler(u→v)+TTF_B(v), where TTF_A(u) is the average shortest TTF from all qubits in chip A to u, TTF_B(v) the analogous egress cost on chip B, and the coupler term is t_coupler + λ ln(1/(1−ε_coupler)). The optimization then selects n links minimizing the weighted sum of Average Path Length, Effective Path Cost, Congestion, Qubit Ove

What carries the argument

The central mechanism is the multi-objective cost model (Eq. 1), whose five terms encode routing efficiency (Average Path Length), noise- and latency-aware communication quality (Effective Path Cost via Time-to-Fidelity), spatial congestion, per-qubit degree overload, and endpoint sparsity. The Time-to-Fidelity metric converts gate time and error rate into a single effective delay, t + λ ln(1/(1−ε)), which is precomputed with Dijkstra's algorithm on each chip's graph and then averaged per candidate endpoint. The greedy-plus-refinement solver enforces hard constraints (maximum qubit degree D_max, minimum physical spacing δ, link budget n) and returns a link set L whose cost is claimed to corr

Load-bearing premise

The ranking of coupler placements depends on the assumed gate-error and latency numbers fed into the Time-to-Fidelity metric; if the real chip-to-chip couplers have different error rates or correlated noise, the selected placements may not be the best on actual hardware.

What would settle it

On a two-chip device with reconfigurable inter-chip couplers, measure the actual success probability of the same benchmark circuits under InterPlace-optimized placement and under a high-cost placement. If the optimized placement does not reliably yield higher measured fidelity, the cost model's ranking is not predictive of real hardware performance.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

If this is right

  • Lower InterPlace cost consistently predicts lower combined on-chip SWAPs and inter-chip operations across multiple compilers and circuit families, so the cost model can be used as a pre-fabrication proxy for routing quality.
  • Increasing the number of inter-chip links does not automatically help; good placement is what converts extra couplers into lower overhead and higher fidelity, so link-budget decisions should be made jointly with placement.
  • The framework scales to larger systems: cost reductions persist when the number of chips grows from 2 to 5 and when chips grow to hundreds of qubits, suggesting placement optimization becomes more, not less, important in larger modular systems.
  • Because the search runs once at design time, the offline cost is amortized over all future circuits and compilers, making it practical to include in the hardware design flow.
  • Fidelity improvements are largest in circuits with many two-qubit operations (e.g., the quantum Fourier transform), where reducing SWAP and inter-chip gates directly cuts error accumulation.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same cost function could be reused to compare coupler technologies, not just positions: by plugging in different latency/error figures for short-range vs. long-range links, the framework would output which physical link type deserves the higher link budget.
  • A natural extension is a closed loop with calibration: after a device is fabricated, measured error rates could re-run the solver to decide which of several spare couplers to activate, adapting placement to drift.
  • The TTF model treats errors as independent; adding measured crosstalk correlations to the edge weights or the congestion term could change the ranking of placements in dense layouts, and would be testable in the same simulator.
  • The reported fidelity gains are from circuits up to 30 qubits; scaling the fidelity simulation to larger circuits would test whether the advantage holds when SWAP overhead grows with system size.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

5 major / 5 minor

Summary. The paper introduces InterPlace, a hardware-aware framework for selecting inter-chip coupler link placements in modular and chiplet quantum processors. The core contribution is a five-term cost model (Eq. 1) combining average path length, fidelity-aware effective path cost (via a Time-to-Fidelity model), congestion, qubit overload, and sparsity penalties. A constrained optimization procedure selects a fixed number of coupler links while respecting degree and spacing limits. The framework is implemented in Python/Qiskit and evaluated on simulated multi-chip systems built from IBM fake backends, with 5 compilers and 2–5 chips. The paper reports that lower InterPlace cost leads to fewer on-chip SWAPs and inter-chip operations and improved fidelity, with headline claims of up to 53.0% fidelity improvement and 33.3% reduction in combined operations.

Significance. If the central claim were robustly supported, InterPlace would make a useful contribution to architectural co-design for modular quantum systems, a topic of growing practical importance. The cost model is plausible and the paper demonstrates a working software pipeline across multiple compilers and moderately large simulated systems. The use of realistic IBM backend snapshots and several chip topologies is a strength. However, the empirical validation as presented does not currently establish that InterPlace cost values predict real routing/fidelity outcomes across the placement space, because the evaluation compares only extremes selected by the same model and lacks statistical controls. The paper's headline fidelity number is also arithmetically inconsistent.

major comments (5)
  1. [§6.2.1, Fig. 7; §6.4, Fig. 10] The evaluation compares only three placements per configuration: 'lowest', 'median', and 'highest' cost, all selected using the identical cost model (Eq. 1) being validated. This is largely circular: it demonstrates that the model's own extremes differ, but not that the cost metric predicts real-world routing/fidelity performance across the placement space. To support the claim that lower cost causes lower SWAP overhead and higher fidelity, the authors should sample a distribution of random placements spanning the cost range, show a correlation (with error bars), and include multiple seeds and circuits. As reported, the head-to-head differences could be selection artifacts of the model's own ranking.
  2. [§6.4, Fig. 10 and Abstract] The headline fidelity improvement is reported inconsistently. For QFT, fidelity is said to increase from 8% (highest-cost) to 17% (lowest-cost), and the paper calls this a '53.0% increased'. The standard relative-change formula gives (17−8)/8 = 112.5%; the 53.0% figure uses the new value as denominator. This contradicts the immediately preceding Random(depth 30) example, which correctly reports (25−19)/19 = 31.6% using the old-fidelity denominator. The abstract and conclusion repeat the 53.0% claim. This arithmetic inconsistency must be corrected, and the claim should be recomputed with a stated, consistent convention.
  3. [§6.1.5, §6.2, Table 1, Fig. 8] For each configuration the paper appears to use a single random circuit (e.g., 'a random 40-qubit circuit', 'a random 30-qubit circuit', 'Random(60)', etc.) with no error bars, no multiple seeds, and no report of variance. Because routing and SWAP counts are highly circuit-dependent, a single instance cannot support claims such as 'consistently reduces' or 'reliably predicts'. At minimum, the authors should run several random circuits per configuration and report mean ± standard deviation, or per-instance scatter plots showing cost versus overhead.
  4. [§4.1.2, Eq. (4); §6.1.2] The Time-to-Fidelity model contains a scaling factor λ in TTF_edge(e) = t_gate(e) + λ·ln(1/(1−ε_gate(e))). This λ directly controls the relative weight of gate error versus time in the effective path cost, and hence materially affects which coupler placements are selected. The evaluation settings state α=γ=δ=ε=1 and β=10, but never state the value of λ used in the experiments, nor any sensitivity analysis. Without this value the experimental results are not reproducible, and the claimed insensitivity to model parameters is unsubstantiated.
  5. [§6.1.4, §6.4] The fidelity evaluation appears to assume independent per-gate errors, with SWAPs modeled as three CNOTs and coupler CNOTs fixed at 3.5% error / 235 ns. This independent-error model is a clean abstraction, but real multi-chip systems exhibit crosstalk, calibration drift, and correlated errors that can change the relative ranking of placements. The paper should explicitly state this assumption as a limitation and, ideally, perform a sensitivity analysis over the coupler error rate and latency to show that the qualitative conclusions are not artifacts of the particular simulated values. A single point estimate from the IBM Flamingo report is not sufficient to establish physical transferability.
minor comments (5)
  1. [§4.1.1, Eq. (2)] The +1 term for the inter-chip hop is constant for fixed n, as the paper notes. For clarity, this could be stated as an additive constant that does not affect optimization, and Eq. (2) could be simplified to suppress the constant when n is fixed.
  2. [§5.2, Phase 1] The text says 'an n×n cost matrix', but there are |V_A| × |V_B| candidate pairs; n×n is misleading unless n here denotes the number of candidate links. Please clarify the notation.
  3. [§6.4, Fig. 10 caption] The caption says 'Each category shows ten bars: the first five are InterPlace results... the last five are the matched baseline', but the figure appears to show six groups with ten bars each. The caption and figure should be aligned.
  4. [General] The paper does not state the random seed(s) used for circuit generation, baseline placement selection, or solver stochasticity, nor does it mention plans for releasing code. This hampers reproducibility; please provide seeds or an artifact appendix.
  5. [Various] Typos and minor wording issues include 'a more challeng set setting' (§6.2.1), 'Inter-Chip' inconsistency, and 'the Inter-chip coupler operations directly fidelity' (§6.4). A careful proofread is needed.

Circularity Check

2 steps flagged

Headline gains are measured between the model's own lowest- and highest-cost placements; since the cost function is built from path-length and error proxies for the outcome metrics, the evaluation is a self-consistency check rather than an independent prediction.

specific steps
  1. other [Section 6.1.3 and Section 6.2.1]
    "As baseline comparisons, we emulate different Inter-chip linkage combinations and find (1)Lowest cost: this is the solution InterPlace provides. (2)Median cost: it is one representative random selection. (3)Highest cost: this is the linkage that offers the highest cost value based on our model."

    All headline results (Figs. 7, 8, 10; Table 1) compare the model's chosen best placement against one median and one worst placement, both ranked by the same Eq. 1. The 'highest-cost' baseline is, by definition, the placement the model scores worst; the 'lowest-cost' baseline is the one it selects. Showing that the low-cost placement has fewer SWAPs and higher fidelity than the high-cost placement is a consistency check between the cost model and compiled outcomes, not a predictive test over the placement space. The up-to-53.0% fidelity gain is the gap between the model's own best and worst endpoints, so the headline improvement is a selection artifact of the objective being validated.

  2. self definitional [Section 4.1.1-4.1.2 and Section 6.1.4]
    "Average Path Length— promotes central placement of coupler endpoints to minimize average on-chip routing distance, reducing SWAP overhead and logical circuit depth. Effective Path Cost— incorporates both communication latency and error rates through a Time-to-Fidelity (TTF) model, producing a fidelity-aware delay metric. ... Fidelity: It quantifies how closely the transpiled circuit matches the ideal output by compounding error from two-qubit gates, SWAPs (treated as three CNOTs), and Inter-chip couplers."

    The cost function's dominant terms are built from the same quantities used as outcome metrics: APL is mean shortest-path distance (the paper states each additional hop corresponds to a SWAP), and EPC is a TTF penalty combining gate time and error, while the fidelity outcome is the compounded error of two-qubit gates, SWAPs, and couplers. Thus low APL/EPC is expected to produce lower SWAP counts and higher fidelity under any transpiler by construction. The evaluation cannot separate this built-in proxy relationship from an independent empirical discovery; it demonstrates that the objective correlates with its own design targets.

full rationale

InterPlace's cost model is not fitted to the evaluation data; it is a hand-specified multi-objective function (Eq. 1), and the self-citations [15]-[17] are not load-bearing. However, the validation loop is partly circular: the 'lowest', 'median', and 'highest' placements are all defined by the same cost model being validated, and the cost model's chief terms explicitly proxy for the SWAP and fidelity metrics used as outcomes. Consequently, the reported reductions (up to 53.0% fidelity, up to 33.3% overhead) are the gap between the model's own best and worst endpoints, not a prediction over an independent sample of placements. Because the compiled SWAP/fidelity numbers are produced by external compilers, there is genuine empirical content, so this is not fully tautological (not an 8-10). Separately, the QFT fidelity claim is arithmetically inconsistent (8% to 17% is a 112.5% relative increase, not 53.0%), and no error bars or seeds are reported; these are correctness/robustness concerns rather than additional circularity.

Axiom & Free-Parameter Ledger

5 free parameters · 5 axioms · 0 invented entities

The central claim rests on a hand-tuned weighted cost model with an unstated TTF scaling parameter, simplified congestion, and simulated hardware assumptions. No new physical entities are introduced.

free parameters (5)
  • TTF scaling lambda = not stated
    In Eq. 4 and 7, lambda weights the logarithmic error penalty in the TTF metric; it is never assigned a value, yet it scales all path costs used in the objective.
  • Cost weights (alpha, beta, gamma, delta, epsilon) = (1, 10, 1, 1, 1)
    Set by hand to balance term magnitudes in Eq. 1; no sensitivity analysis is shown, so the optimal placement may depend on this arbitrary choice.
  • D_max (per-qubit degree limit) = not stated for experiments
    Used in overload penalty and hard constraints (Eqs. 12, 14-15); example uses 2, but experimental values are not reported.
  • delta (minimum coupler spacing) = not stated
    Hard constraint in Eq. 16; no value given for the evaluation.
  • eta (congestion distance weight) = unused
    Defined in Eq. 9 but the approximation Eq. 10 uses only max(load), so eta is effectively dropped without discussion.
axioms (5)
  • domain assumption TTF formula: t + lambda * ln(1/(1-eps)) models latency-fidelity trade-off
    Eq. 4; the logarithmic penalty is plausible but not derived from first principles.
  • domain assumption Fidelity estimates compound independent gate errors
    Sec 6.1.4: fidelity is computed by multiplying (1-error) over gates, SWAPs as 3 CNOTs, and inter-chip couplers; neglects crosstalk, leakage, and correlated errors.
  • domain assumption Each on-chip hop requires a SWAP operation
    Sec 4.1.1: path length is equated with SWAP overhead; in practice compilers can use other routing or re-synthesis.
  • domain assumption Inter-chip CNOT has 3.5% error and 235 ns time, SWAP is 3x error
    Sec 6.1.2: taken from IBM Flamingo report [21]; a single hardware assumption that strongly affects results.
  • ad hoc to paper Congestion approximation max(load(u), load(v)) is adequate
    Sec 4.1.3, Eq. 10: replaces the distance-weighted congestion with a max-degree heuristic for computational efficiency; validity untested.

reviewed 2026-08-04 · how reviews work

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Cite this review

Pith. "Pith review of Optimizing Inter-chip Coupler Link Placement for Modular and Chiplet Quantum Systems." pith.science (2026). https://pith.science/paper/44YKTGEM

@misc{pith2026250910409,
  author       = {Pith},
  title        = {Pith review of: Optimizing Inter-chip Coupler Link Placement for Modular and Chiplet Quantum Systems},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/44YKTGEM}},
  note         = {Machine review of arXiv:2509.10409}
}
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read the original abstract

Quantum computing offers unparalleled computational capabilities but faces significant challenges, including limited qubit counts, diverse hardware topologies, and dynamic noise and error rates, which hinder scalability and reliability. Distributed quantum computing, particularly chip-to-chip connections, has emerged as a solution by interconnecting multiple processors to collaboratively execute large circuits. While hardware advancements, such as IBM's Quantum Flamingo, focus on improving inter-chip fidelity, limited research addresses efficient circuit cutting and qubit mapping in distributed systems. This project introduces InterPlace, a self-adaptive, hardware-aware framework for chip-to-chip distributed quantum systems. InterPlace analyzes qubit noise and error rates to construct a virtual system topology, guiding circuit partitioning and distributed qubit mapping to minimize SWAP overhead and enhance fidelity. Implemented with IBM Qiskit and compared with the state-of-the-art, InterPlace achieves up to a 53.0\% improvement in fidelity and reduces the combination of on-chip SWAPs and inter-chip operations by as much as 33.3\%, demonstrating scalability and effectiveness in extensive evaluations on real quantum hardware topologies.

Figures

Figures reproduced from arXiv: 2509.10409 by Juntao Chen, Kaixun Hua, Pedro Chumpitaz Flores, Wenqi Wei, Ying Mao, Zefan Du.

Figure 1
Figure 1. Figure 1: Rigetti’s multi-chip Architecture. The Cepheus￾1-36Q multi-chip system connects four 9-qubit chip with inter-chip couplers [1] . These constraints have led to a growing consensus: the future of scalable quantum systems lies in modular architectures, where smaller quantum chips are interconnected to act as a unified processor [15, 16, 33, 37]. Modularity offers multiple advantages. It enhances fab￾rication … view at source ↗
Figure 2
Figure 2. Figure 2: Representative qubit connectivity graphs. 3.3 Multi-Chip Architectures & Inter-Chip Coupling In multi-chip quantum systems, inter-chip qubit communi￾cation is enabled by physical couplers that connect qubits from different modules. These couplers exhibit variability in fidelity, latency, and physical footprint. For instance, IBM’s m-couplers support short-range high-fidelity links, while l-couplers enable … view at source ↗
Figure 3
Figure 3. Figure 3: Coupler congestion. The left panel (a) il￾lustrates high congestion, where multiple links share the same endpoint, leading to a larger penalty Í (𝑢,𝑣) ∈ L max(load(𝑢), load(𝑣)). The right panel (b) shows reduced congestion, where links are spread across different endpoints. Two-case comparison. Using the approximation above, consider the two configurations in [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: Spatial sparsity. The left panel (a) depicts clustered endpoints in Module A, resulting in a high sparsity cost. The right panel (b) shows distributed endpoints across Module A, which lowers the cost. The penalty aggregates over pairs of links using dist( (𝑢, 𝑣), (𝑢 ′ , 𝑣′ )) = 𝑑𝐺𝐴 (𝑢, 𝑢′ ) + 𝑑𝐺𝐵 (𝑣, 𝑣′ ). 5 InterPlace System Design The InterPlace cost model addresses the inter-chip coupler placement probl… view at source ↗
Figure 6
Figure 6. Figure 6: InterPlace Framework Overview. Top: workflow from device inputs through TTF-based preprocessing to a constrained multi-objective optimizer; output is the selected link set and metrics.Bottom: (a) two on-chip topologies; (b) random couplers induce congestion, overload (deg>𝐷max), and clustering; (c) optimized couplers distribute endpoints and minimize total cost. 6.1 Implementation and Evaluation Settings 6… view at source ↗
Figure 7
Figure 7. Figure 7: Relationship between InterPlace cost (Eq. 1) and Inter-chip operations + On-chip SWAPs for a random 40-qubit circuit of depth 10. Two configurations are shown: a homogeneous system of two identical CairoV2(27) chips (left) and a heterogeneous system composed of an Auckland(27) chip connected to a CairoV2(27) chip (right). Bars show On-chip (darker) and Inter-chip (lighter) SWAPs, with colors denoting compi… view at source ↗
Figure 8
Figure 8. Figure 8: SWAP counts versus cost for coupler link sets of different sizes. Each panel shows results for a random 30-qubit circuit with 𝑘 = 1–4 couplers placed in a system with one Auckland(27) and one CairoV2(27). Bars show SWAP counts, separated into On-chip (dark) and Inter-chip (light) components, while the line marks the total SWAP count. Colors denote five compilers. Increasing 𝑘 enlarges the design space for … view at source ↗
Figure 9
Figure 9. Figure 9: Cost comparison of the lowest (InterPlace), median, and highest-cost coupler link strategies across different chip sizes. Red numbers indicate the Inter-chip operations under the UCC compiler for random circuits with 100, 150, and 200 qubits on two-chip systems of 130, 254, and 312 qubits. 6.3 Scalability of InterPlace Cost Modeling In this subsection, we investigate the scalability of InterPlace. We study… view at source ↗
Figure 10
Figure 10. Figure 10: Fidelity comparison of our optimized coupler selection (InterPlace) versus a random baseline across six 30-qubit circuit families compiled with five backends on a system with two connected Auckland(27). Each category shows ten bars: the first five are InterPlace results, one per compiler in fixed order; the last five are the matched baseline. amortized across all future workloads and compilers, ensur￾ing … view at source ↗

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Reference graph

Works this paper leans on

56 extracted references · 9 linked inside Pith

  1. [1]

    d.].https://investors.rigetti.com/static-files/fbac3801-223f-4f0f- a207-47d25084a1d7

    [n. d.].https://investors.rigetti.com/static-files/fbac3801-223f-4f0f- a207-47d25084a1d7. [Accessed 20-08-2025]

    2025

  2. [2]

    [n. d.]. GitHub - CQCL/tket: Source code for the TKET quantum compiler, Python bindings and utilities — github.com.https://github. com/CQCL/tket. [Accessed 01-09-2025]

    2025

  3. [3]

    [n. d.]. GitHub - unitaryfoundation/ucc: Unitary Compiler Collection — github.com.https://github.com/unitaryfoundation/ucc. [Accessed 01-09-2025]

    2025

  4. [4]

    [n. d.]. International Year of Quantum Sci@ ence and Technology. https://www.quantum2025.org/. Accessed: 2025-04-09

    2025

  5. [5]

    [n. d.]. Meet Willow, our state-of-the-art quantum chip — blog.google.https://blog.google/technology/research/google-willow- quantum-chip/. [Accessed 21-08-2025]

    2025

  6. [6]

    [n. d.]. transpiler (latest version) | IBM Quantum Documentation — quantum.cloud.ibm.com.https://quantum.cloud.ibm.com/docs/en/ api/qiskit/transpiler. [Accessed 20-08-2025]

    2025

  7. [7]

    fake_provider (latest version) | IBM Quantum Documentation — quantum.cloud.ibm.com.https://quantum.cloud.ibm.com/docs/en/ api/qiskit-ibm-runtime/fake-provider

    2025. fake_provider (latest version) | IBM Quantum Documentation — quantum.cloud.ibm.com.https://quantum.cloud.ibm.com/docs/en/ api/qiskit-ibm-runtime/fake-provider. [Accessed 21-08-2025]

    2025

  8. [8]

    Islombek Abdikhakimov. 2024. Preparing for a Quantum Future: Strategies for Strengthening International Data Privacy in the Face of Evolving Technologies.International Journal of Law and Policy2, 5 (2024), 42–46

    2024

  9. [9]

    Frank Arute, Kunal Arya, Ryan Babbush, et al . 2019. Quantum supremacy using a programmable superconducting processor.Nature 574, 7779 (2019), 505–510

    2019

  10. [10]

    Zoran Bandic et al . 2023. Mapping Quantum Circuits to Modular Architectures with QUBO.arXiv preprint arXiv:2305.06687(May 2023). https://arxiv.org/abs/2305.06687

    Pith/arXiv arXiv 2023

  11. [11]

    Rami Barends, Julian Kelly, Anthony Megrant, Daniel Sank, Evan Jeffrey, Yu Chen, Yi Yin, Ben Chiaro, Josh Mutus, Charles Neill, et al

  12. [12]

    Yaser Baseri, Vikas Chouhan, and Abdelhakim Hafid. 2024. Navigating quantum security risks in networked environments: A comprehensive study of quantum-safe network protocols.Computers & Security142 (2024), 103883

    2024

  13. [13]

    Yudong Cao, Jonathan Romero, Jonathan P Olson, Matthias Degroote, Peter D Johnson, Mária Kieferová, Ian D Kivlichan, Tim Menke, Borja Peropadre, Nicolas P D Sawaya, Sukin Sim, Libor Veis, and Alán Aspuru-Guzik. 2019. Quantum Chemistry in the Age of Quantum Computing.Chemical Reviews119, 19 (2019), 10856–10915

    2019

  14. [14]

    Shuhong Dai, Nishant Saurabh, Qingle Wang, Jiawei Nian, Shuwen Kan, Ying Mao, and Long Cheng. 2025. Quantum Reinforcement Learning for QoS-Aware Real-Time Job Scheduling in Cloud Systems. IEEE Systems Journal(2025)

    2025

  15. [15]

    Zefan Du, Shuwen Kan, Samuel Stein, Zhiding Liang, Ang Li, and Ying Mao. 2025. Hardware-aware Compilation for Chip-to-Chip Coupler- Connected Modular Quantum Systems.arXiv preprint arXiv:2505.09036 (2025)

    Pith/arXiv arXiv 2025

  16. [16]

    Zefan Du, Yanni Li, Zijian Mo, Wenqi Wei, Juntao Chen, Rajkumar Buyya, and Ying Mao. 2024. Hardware-aware circuit cutting and distributed qubit mapping for connected quantum systems.arXiv preprint arXiv:2412.18458(2024)

    Pith/arXiv arXiv 2024

  17. [17]

    Zefan Du, Wenrui Zhang, Wenqi Wei, Juntao Chen, Tao Han, Zhiding Liang, and Ying Mao. 2024. Efficient Circuit Cutting and Scheduling in a Multi-Node Quantum System with Dynamic EPR Pairs.arXiv preprint arXiv:2412.18709(2024)

    Pith/arXiv arXiv 2024

  18. [18]

    Anthony D’Onofrio, Amir Hossain, Lesther Santana, Naseem Machlovi, Samuel Stein, Jinwei Liu, Ang Li, and Ying Mao. 2023. Dis- tributed quantum learning with co-management in a multi-tenant quantum system. In2023 IEEE International Conference on Big Data (BigData). IEEE, 221–228

    2023

  19. [19]

    Amr Elsharkawy, Xiao-Ting Michelle To, Philipp Seitz, Yanbin Chen, Yannick Stade, Manuel Geiger, Qunsheng Huang, Xiaorang Guo, Muhammad Arslan Ansari, Christian B Mendl, et al . 2025. Integra- tion of quantum accelerators with high performance computing—a review of quantum programming tools.ACM Transactions on Quantum Computing6, 3 (2025), 1–46

    2025

  20. [20]

    Edward Farhi, Jeffrey Goldstone, and Sam Gutmann. 2014. A quantum approximate optimization algorithm.arXiv preprint arXiv:1411.4028 (2014)

    Pith/arXiv arXiv 2014

  21. [21]

    Jay Gambetta and Ryan Mandelbaum. 2024. IBM Quantum delivers on performance challenge made two years ago.https://www.ibm.com/ quantum/blog/qdc-2024. Accessed: 2025-04-09. 12

    2024

  22. [22]

    Jay M Gambetta, Jerry M Chow, and Matthias Steffen. 2017. Building logical qubits in a superconducting quantum computing system.npj Quantum Information3, 1 (2017), 2

    2017

  23. [23]

    Google Quantum AI. 2023. Cirq.https://quantumai.google/cirq. Ver- sion 1.2.0

    2023

  24. [24]

    Greenberger, Michael A

    Daniel M. Greenberger, Michael A. Horne, and Anton Zeilinger. 2007. Going Beyond Bell’s Theorem. arXiv:0712.0921 [quant-ph]https: //arxiv.org/abs/0712.0921

    Pith/arXiv arXiv 2007

  25. [25]

    Mingyoung Jessica Jeng et al. 2025. Modular Compilation for Quantum Chiplet Architectures.arXiv preprint arXiv:2501.08478(January 2025). https://arxiv.org/abs/2501.08478

    Pith/arXiv arXiv 2025

  26. [26]

    Stein, Chenxu Liu, Wenqi Wei, Juntao Chen, Ang Li, and Ying Mao

    Shuwen Kan, Zefan Du, Miguel Palma, Samuel A. Stein, Chenxu Liu, Wenqi Wei, Juntao Chen, Ang Li, and Ying Mao. 2024. Scalable Circuit Cutting and Scheduling in a Resource-constrained and Distributed Quantum System. In2024 IEEE Quantum Week Conference (QCE)(Mon- tréal, QC, Canada). IEEE

    2024

  27. [27]

    Morten Kjaergaard, Mollie E Schwartz, Jochen Braumüller, Philip Krantz, Joel I-J Wang, Simon Gustavsson, and William D Oliver. 2020. Superconducting qubits: Current state of play.Annual Review of Condensed Matter Physics11 (2020), 369–395

    2020

  28. [28]

    Philip Krantz, Morten Kjaergaard, Fei Yan, Terry P Orlando, Simon Gustavsson, and William D Oliver. 2019. A quantum engineer’s guide to superconducting qubits.Applied Physics Reviews6, 2 (2019), 021318. https://doi.org/10.1063/1.5089550

    doi:10.1063/1.5089550 2019

  29. [29]

    Ryan L’Abbate, Anthony D’Onofrio, Samuel Stein, Samuel Yen-Chi Chen, Ang Li, Pin-Yu Chen, Juntao Chen, and Ying Mao. 2024. A quantum-classical collaborative training architecture based on quan- tum state fidelity.IEEE Transactions on Quantum Engineering5 (2024), 1–14

    2024

  30. [30]

    Guodong Li, Fangce Yu, Qingle Wang, Lin Liu, Ying Mao, and Long Cheng. 2025. Quantum neural network classifier with differential privacy.Physica Scripta100, 3 (2025), 035109

    2025

  31. [31]

    Chen-Yu Liu, En-Jui Kuo, Chu-Hsuan Abraham Lin, Sean Chen, Ja- son Gemsun Young, Yeong-Jar Chang, and Min-Hsiu Hsieh. 2024. Training classical neural networks by quantum machine learning. In2024 IEEE International Conference on Quantum Computing and Engineering (QCE), Vol. 2. IEEE, 34–38

    2024

  32. [32]

    Mazyar Mirrahimi, Zaki Leghtas, Victor V Albert, Steven Touzard, Robert J Schoelkopf, Liang Jiang, and Michel H Devoret. 2014. Dy- namically protected cat-qubits: A new paradigm for universal quan- tum computation.New Journal of Physics16, 4 (2014), 045014. https://doi.org/10.1088/1367-2630/16/4/045014

    doi:10.1088/1367-2630/16/4/045014 2014

  33. [33]

    Christopher Monroe and et al. 2014. Large-scale modular quantum- computer architecture with atomic memory and photonic intercon- nects.Physical Review A89, 2 (2014), 022317

    2014

  34. [34]

    Wenrui Mu, Ying Mao, Long Cheng, Qingle Wang, Weiwen Jiang, and Pin-Yu Chen. 2022. Iterative qubits management for quantum index searching in a hybrid system. In2022 IEEE International Performance, Computing, and Communications Conference (IPCCC). IEEE, 283–289

    2022

  35. [35]

    Danyal Namakshenas, Abbas Yazdinejad, Ali Dehghantanha, and Gau- tam Srivastava. 2024. Federated quantum-based privacy-preserving threat detection model for consumer internet of things.IEEE Transac- tions on Consumer Electronics70, 3 (2024), 5829–5838

    2024

  36. [36]

    Hartmut Neven. 2024. Meet Willow, our state-of-the-art quan- tum chip.https://blog.google/technology/research/google-willow- quantum-chip/. Accessed: 2025-04-09

    2024

  37. [37]

    Nickerson, Joseph F

    Naomi H. Nickerson, Joseph F. Fitzsimons, and Simon C. Benjamin

  38. [38]

    2010.Quantum Computation and Quantum Information

    Michael A Nielsen and Isaac L Chuang. 2010.Quantum Computation and Quantum Information. Cambridge University Press

    2010

  39. [39]

    Freely scalable quantum technologies using cells of 5-to-50 qubits with very lossy and noisy photonic links.Nature Communica- tions4 (2014), 1756

    2014

  40. [40]

    Zhiguo Qu, Lailei Zhang, and Prayag Tiwari. 2024. Quantum fuzzy federated learning for privacy protection in intelligent information processing.IEEE Transactions on Fuzzy Systems33, 1 (2024), 278–289

    2024

  41. [41]

    Norris et al

    Graham J. Norris et al. 2025. Performance Characterization of a Multi- Module Quantum Processor with Static Inter-Chip Couplers.arXiv preprint arXiv:2503.12603(March 2025).https://arxiv.org/abs/2503. 12603

    Pith/arXiv arXiv 2025

  42. [42]

    Sriram Raghavan, Mukesh Khare, and Jay Gambetta. 2025. The 2024 IBM Research Annual Letter.https://research.ibm.com/blog/research- annual-letter-2024. Accessed: 2025-04-09

    2025

  43. [43]

    Sahar Ben Rached et al . 2024. Benchmarking Emerging Cavity- Mediated Quantum Interconnect Technologies for Modular Quan- tum Computers.arXiv preprint arXiv:2407.15651(July 2024).https: //arxiv.org/abs/2407.15651

    Pith/arXiv arXiv 2024

  44. [44]

    Samuel A Stein, Betis Baheri, Daniel Chen, Ying Mao, Qiang Guan, Ang Li, Shuai Xu, and Caiwen Ding. 2022. Quclassi: A hybrid deep neural network architecture based on quantum state fidelity.Proceedings of Machine Learning and Systems4 (2022), 251–264

    2022

  45. [45]

    Samuel A Stein, Betis Baheri, Daniel Chen, Ying Mao, Qiang Guan, Ang Li, Bo Fang, and Shuai Xu. 2021. Qugan: A quantum state fidelity based generative adversarial network. In2021 IEEE international conference on quantum computing and engineering (QCE). IEEE, 71–81

    2021

  46. [46]

    Xanadu Quantum Technologies. 2025. Scaling and Networking a Modular Photonic Quantum Computer.PubMed(February 2025). https://pubmed.ncbi.nlm.nih.gov/39843755/

    arXiv 2025

  47. [47]

    Samuel A Stein, Ryan L’Abbate, Wenrui Mu, Yue Liu, Betis Baheri, Ying Mao, Guan Qiang, Ang Li, and Bo Fang. 2021. A hybrid system for learning classical data in quantum states. In2021 IEEE International Performance, Computing, and Communications Conference (IPCCC). IEEE, 1–7

    2021

  48. [48]

    Almudena Carrera Vazquez et al. 2024. Combining Quantum Proces- sors with Real-Time Classical Communication.Nature615 (November 2024), 715–720.https://doi.org/10.1038/s41586-024-08178-2

    doi:10.1038/s41586-024-08178-2 2024

  49. [49]

    Ubaid Ullah and Begonya Garcia-Zapirain. 2024. Quantum machine learning revolution in healthcare: a systematic review of emerging perspectives and applications.IEEE Access12 (2024), 11423–11450

    2024

  50. [50]

    Robert Wille, Lukas Burgholzer, Stefan Hillmich, and Nils Quetschlich

  51. [51]

    Vandana Rani Verma, Dinesh Kumar Nishad, Vishnu Sharma, Vinay Kumar Singh, Anshul Verma, and Dharti Raj Shah. 2025. Quan- tum machine learning for Lyapunov-stabilized computation offloading in next-generation MEC networks.Scientific Reports15, 1 (2025), 405

    2025

  52. [52]

    Adam Zewe. 2024. Modular, Scalable Hardware Architecture for a Quantum Computer.MIT News(May 2024).https: //news.mit.edu/2024/modular-scalable-hardware-architecture- quantum-computer-0529

    2024

  53. [53]

    Adam Zewe. 2025. Device Enables Direct Communication Among Multiple Quantum Processors.MIT News(March 2025). https://news.mit.edu/2025/device-enables-direct-communication- among-multiple-quantum-processors-0321 13

    2025

  54. [54]

    Conner, Joel Grebel, Yash J

    Xuntao Wu, Haoxiong Yan, Gustav Andersson, Alexander Anferov, Ming-Han Chou, Christopher R. Conner, Joel Grebel, Yash J. Joshi, Shiheng Li, Jacob M. Miller, Rhys G. Povey, Hong Qiao, and Andrew N. Cleland. 2024. Modular Quantum Processor with an All-to-All Re- configurable Router.Phys. Rev. X14 (Nov 2024), 041030. Issue 4. https://doi.org/10.1103/PhysRevX...

    doi:10.1103/physrevx.14.041030 2024

  55. [2014]

    Superconducting quantum circuits at the surface code threshold for fault tolerance.Nature508, 7497 (2014), 500–503.https://doi.org/ 10.1038/nature13171

    doi:10.1038/nature13171 2014

  56. [2023]

    https://github.com/cda-tum/mqt-qmap

    MQT QMAP: Optimal Qubit Mapping with Noise Adaptation. https://github.com/cda-tum/mqt-qmap

This paper was first reviewed by deepseek-v4-flash on August 4, 2026.