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REVIEW 2 major objections 6 minor 64 references

Connecting a qubit into a coupler lattice raises its surface dielectric loss by factors of 1.3–1.8, helping explain why processor qubits live shorter lives than isolated ones.

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2026-07-14 09:34 UTC pith:4ODRMQ5G

load-bearing objection Clean FEM ladder shows connectivity can raise surface-loss rate by ~1.3–1.8×; relative R_Γ is solid, absolute T1s are not. the 2 major comments →

arxiv 2607.10743 v1 pith:4ODRMQ5G submitted 2026-07-12 quant-ph

Connectivity-induced surface-loss penalty in superconducting qubit-coupler lattices

Xu-Yang Gu , Gui-Han Liang , Ming-Chuan Wang , Yongxi Xiao , Cheng-Lin Deng , Zheng-He Liu , Tian-Ming Li , Kai Xu
show 2 more authors
Zhongcheng Xiang Heng Fan
This is my paper
classification quant-ph
keywords superconducting qubitstransmonsurface participation ratiodielectric lossqubit-coupler latticeflip-chipconnectivity penaltyfinite-element simulation
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

Isolated superconducting transmon qubits now routinely reach energy-relaxation times of hundreds of microseconds, yet the same devices embedded in multiqubit processor lattices typically live far shorter lives. This paper uses finite-element simulation of flip-chip qubit–coupler geometries to show that the act of connecting a qubit to couplers itself increases the surface participation of the qubit-like mode, and therefore its surface dielectric loss. In the simulated square lattice, linking a qubit to two couplers multiplies the surface-loss rate by 1.3 and linking it to four multiplies it by 1.8 relative to an isolated baseline. The increase arises from three competing effects: extra edge fields created by the coupling claws, redistribution of the electric field over the larger metal network, and hybridization with coupler modes. Geometry sweeps then reveal that design choices that improve an isolated qubit—widening the qubit–ground gap or etching an opposite-chip hole—can actually enlarge the connectivity penalty, while claw geometry can raise or lower both qubit and coupler surface loss. The practical message is that surface-loss budgets for processor qubits must be evaluated inside the connected lattice, not on single-qubit test chips.

Core claim

Higher connectivity in a flip-chip qubit–coupler lattice increases the surface dielectric loss of the dressed qubit mode: connecting a qubit to two and four couplers multiplies the surface-loss rate by factors of 1.3 and 1.8 relative to the isolated single-qubit baseline, mainly through added claw-edge fields that are only partially offset by field redistribution and mode hybridization.

What carries the argument

The connectivity-induced surface-loss penalty R_Γ = Q_surf(1Q) / Q_surf(m), the ratio of surface-loss rates between the isolated qubit and the lattice-dressed qubit mode; it is extracted from finite-element surface-participation ratios (MA, MS, SA) via a two-step coarse-3D / fine-2D method.

Load-bearing premise

The quoted lifetime and penalty numbers rest on fixed, literature-typical interface loss tangents and on approximate edge-scaling factors that have not been measured for the exact devices being modeled.

What would settle it

Fabricate a controlled ladder of otherwise identical flip-chip devices whose only difference is the number of attached couplers (0, 2, 4), measure their qubit T1 under matched surface conditions, and test whether the observed lifetime ratios match the simulated R_Γ factors of 1.3 and 1.8.

Watch this falsifier — get emailed when new claim-graph text bears on it.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 6 minor

Summary. The manuscript uses finite-element surface-participation analysis to argue that embedding a transmon in a flip-chip qubit–coupler lattice systematically increases the surface dielectric loss of the qubit-like dressed mode relative to an isolated qubit. A controlled geometry ladder (1Q, 1QwP, 2Q1C, 1Q2C, 1Q4C, and a single-mode 1Q4C control) is used to separate three contributions—added claw-edge fields, field redistribution over the connected metal network, and hybridization with coupler modes—summarized in Eq. (2). In the simulated lattice, connecting a qubit to two and four couplers raises the surface-loss rate by factors R_Γ = 1.33 and 1.80 (Table I). Parameter sweeps over qubit–ground gap, opposite-chip holes, and claw geometry then show that some single-qubit loss-reduction strategies increase the connectivity penalty, and the authors extract design guidelines for low-loss lattices.

Significance. If the comparative R_Γ results hold, the paper supplies a concrete, geometry-based mechanism for a widely observed but poorly quantified gap between isolated-qubit T1 and typical lattice-processor T1. The controlled ladder cleanly isolates claw, redistribution, and hybridization effects; frequency-control checks (App. D) and top/bottom interface decompositions (App. E) address the most obvious confounds. Introducing R_Γ as an explicit connectivity-cost metric, and showing that nonlocal claw geometry can reshape qubit-mode participation, are practically useful for processor design. Absolute T_surf_1 values inherit the usual tan-δ and perimeter-scaling uncertainties, but the headline relative factors are comparatively robust because the same loss model is applied to every geometry. The work is simulation-only and does not claim a full accounting of the literature T1 gap; within that scope it is a solid, actionable contribution.

major comments (2)
  1. [Sec. IV / Table VII] Sec. IV and Table VII: the design principles recommend against large qubit–ground gaps and opposite-chip holes because they raise R_Γ, yet the same geometries substantially increase g_qc (e.g., ~63 MHz in O30 to ~95 MHz in Oh_80). The multi-objective trade-off among R_Γ, coupling strength, and coupler-mode T_surf_1 is only partially discussed (mainly for OIDC_80). For the guidelines to be actionable, the main text should present this trade-off more systematically—e.g., a compact summary of R_Γ versus g_qc (and coupler T_surf_1) across the design family—so readers can weigh connectivity loss against coupling requirements rather than optimizing R_Γ alone.
  2. [Sec. II / Table I] Sec. II, Eq. (1) and Table I: R_Γ is a ratio of participation-weighted sums under fixed tan δ_i. The connectivity-driven growth is carried almost entirely by MS and SA (Fig. 2(c), Table IV), so the reported factors 1.33 and 1.80 are first-order robust. Still, a short sensitivity check of R_Γ under plausible variations of the relative tan δ_MS/SA versus tan δ_MA (or under the F_MA uncertainty flagged in App. C) would make the central numerical claim more defensible, especially when the abstract and Fig. 1 frame the result as a contribution to the isolated-versus-lattice T1 discrepancy.
minor comments (6)
  1. [Fig. 2] Fig. 2 caption: “squre lattice” should be “square lattice.”
  2. [Title page] Author affiliations: “Lab ratory” appears to be a typographical error for “Laboratory.”
  3. [Sec. II / Table I] The label “1Q4C sinM” is slightly awkward; consider “1Q4C (single-mode)” or similar for readability in Table I and the text.
  4. [Abstract / Sec. V] Sec. V and App. F correctly note that SPR results are near the coupler idle (off) point. A one-sentence reminder in the abstract or introduction that the reported R_Γ characterizes the near-idle regime, not the full coupler-bias range during gates, would prevent over-reading of the absolute T_surf_1 numbers.
  5. [Fig. 1] Fig. 1 and Table III are useful; ensuring that “typical” versus “best” markers are unambiguous in the figure legend (not only the caption) would help readers scan the comparison.
  6. [App. C / Sec. II] App. C: the non-convergence of F_MA with (w,g) is acknowledged; a brief statement in the main text that MA is subdominant to MS/SA in the connectivity trend (so F_MA uncertainty does not drive R_Γ) would reassure non-specialist readers.

Circularity Check

0 steps flagged

No significant circularity: R_Γ and T_surf_1 are comparative FEM outputs under fixed literature tan δ and F_i; nothing is fitted then re-presented as a prediction.

full rationale

The central numerical claims (Table I: R_Γ = 1.33 for 1Q2C and 1.80 for 1Q4C) are ratios of surface-loss rates obtained from the same two-step FEM SPR pipeline (App. B–C, following external Ref. [7]) applied to controlled geometries that differ only by connectivity and design parameters. Loss tangents and perimeter scaling factors are held fixed across all models, so they cancel to first order in R_Γ; the reported factors are therefore genuine geometric differences in the extracted p_MS and p_SA, not identities or re-labeled fits. There is no parameter fitted to a data subset and then used to “predict” a related quantity, no uniqueness theorem imported from the authors’ prior work, and no ansatz smuggled via self-citation that forces the result. Self-citations (e.g., layout of Ref. [54], coupling-pad capacitances of Refs. [56,57]) merely supply the concrete flip-chip geometry being simulated; they do not underwrite the derivation of the connectivity penalty itself. Absolute T_surf_1 values inherit the usual literature uncertainty in tan δ, but that is a modeling assumption, not circularity. The paper is therefore self-contained against its own simulation benchmarks.

Axiom & Free-Parameter Ledger

4 free parameters · 3 axioms · 1 invented entities

The paper inherits the standard surface-loss model and two-step FEM method; its free parameters are the conventional loss tangents and edge-scaling factors. The only new construct is the comparative metric R_Γ. No new physical entities are postulated.

free parameters (4)
  • tan δ_MA = 2e-3
    Fixed at 2×10^{-3} (Sec. II) following typical Al-on-sapphire values; absolute T1 scales linearly with it.
  • tan δ_MS = tan δ_SA = 0.8e-3
    Fixed at 0.8×10^{-3} (Sec. II); dominates the loss budget.
  • F_MA, F_MS, F_SA = 90, 8, 9
    Perimeter scaling factors extracted from 2-D cross-section (App. C) and rounded to 90, 8, 9; enter every p_i,peri.
  • interface thickness t and ε_layer = 3 nm, 10
    Assumed t = 3 nm, ε = 10 for all three interfaces (App. C); standard but unmeasured for the modeled stack.
axioms (3)
  • domain assumption Surface dielectric loss is given by 1/Q_surf = Σ p_i tan δ_i with p_i obtained from the two-step FEM method of Wang et al. (2015).
    Invoked throughout Sec. II and Apps. B–C; absolute numbers inherit any systematic bias of that method.
  • domain assumption Josephson junctions may be replaced by lumped inductors and metal films by 2-D sheets without altering interface participations at the percent level relevant here.
    Stated in App. B; standard approximation whose error is not quantified for the claw-gap geometries.
  • domain assumption The chosen loss tangents are representative of aluminum-on-sapphire devices.
    Cited from Refs. [6,7]; comparative R_Γ is insensitive to overall scale but absolute T1 is not.
invented entities (1)
  • connectivity-induced surface-loss penalty R_Γ no independent evidence
    purpose: Scalar metric that normalizes the surface-loss rate of a dressed lattice mode to the isolated-qubit baseline.
    Defined in Sec. II; purely comparative, no new physics postulated.

pith-pipeline@v1.1.0-grok45 · 31276 in / 2684 out tokens · 35146 ms · 2026-07-14T09:34:48.917716+00:00 · methodology

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read the original abstract

Recent advances in design and fabrication have increased the energy-relaxation times of isolated superconducting transmon qubits to the hundreds-of-microseconds regime, with reported values exceeding 500 $\mu$s. However, the same progress has not automatically translated to multiqubit processors, where qubits are embedded in connected qubit-coupler lattices and often exhibit much shorter lifetimes than isolated qubits. To identify possible sources of this discrepancy, here we use finite-element simulation to investigate how surface participation ratios and the resulting surface dielectric loss change when a qubit is embedded in a flip-chip qubit-coupler lattice. Controlled comparisons show that higher connectivity can indeed lead to larger surface loss: in the simulated lattice, connecting a qubit to two and four couplers increases the surface loss by factors of 1.3 and 1.8, respectively. We attribute this change to the combined effects of added edge fields from coupling claws, field redistribution over the larger connected metal network, and hybridization with coupler modes. We further examine how this connectivity-induced surface-loss penalty depends on the geometric design parameters of both the qubit electrodes and the coupling claws, and derive guidelines for designing low-loss multiqubit processors.

Figures

Figures reproduced from arXiv: 2607.10743 by Cheng-Lin Deng, Gui-Han Liang, Heng Fan, Kai Xu, Ming-Chuan Wang, Tian-Ming Li, Xu-Yang Gu, Yongxi Xiao, Zheng-He Liu, Zhongcheng Xiang.

Figure 1
Figure 1. Figure 1: FIG. 1. Comparison between the reported energy-relaxation times of isolated-qubit chips and qubit-lattice processors. Filled [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. Surface-participation simulations of single-qubit and qubit-coupler lattice geometries. (a) Electric-field distributions [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Design-parameter dependence of connectivity-induced surface-loss penalty. (a) and (b) define the flip-chip layout and [PITH_FULL_IMAGE:figures/full_fig_p006_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Gap and opposite-chip-hole controls for the qubit designs. (a) Gap sweep, with qubit [PITH_FULL_IMAGE:figures/full_fig_p007_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. Coupling-claw controls around [PITH_FULL_IMAGE:figures/full_fig_p007_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. Simulation of scaling factors in a flip-chip device. Panels (a) and (b) show schematics of the 2D cross-section [PITH_FULL_IMAGE:figures/full_fig_p012_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. Frequency-control check for the opposite-chip-hole [PITH_FULL_IMAGE:figures/full_fig_p013_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. Top-chip fraction of the MA, MS, and SA partici [PITH_FULL_IMAGE:figures/full_fig_p014_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9. Detailed simulation diagnostics for the design investigated in the main text. The left column in each model row shows [PITH_FULL_IMAGE:figures/full_fig_p017_9.png] view at source ↗

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Reference graph

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