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SEQC: Stratify-Elaborate Quantum Compilation Towards Modular Hybrid Architectures

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arxiv 2501.08478 v5 pith:4TZ75L4G submitted 2025-01-14 quant-ph cs.ETcs.PL

classification quant-phcs.ETcs.PL
keywords quantumcompilationmodularqubitseqcarchitectureshybridaverage
verification ladder T0 review T1 audit T2 compute T3 formal
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abstract

As quantum computing technology matures, the pursuit of performance and scalability has led to the widespread adoption of modular quantum architectures. We expect that the next stage of technological evolution will integrate multiple qubit modalities into these systems, producing hybrid, modular quantum architectures. However, the complexity of hybrid, modular quantum devices, coupled with their growing sizes, presents an imminent scalability challenge for quantum compilation. Existing qubit allocation methods are often unable to contend with inter-module links, which do not necessarily support a universal basis gate set. Furthermore, these algorithms are typically not designed for qubit links of significantly varying latency or fidelity. In this work, we propose SEQC, a hierarchical parallelized compilation pipeline optimized for modular quantum systems, including several novel methods for qubit placement, qubit routing, and circuit optimization. SEQC attains a 9.3-32.3% average increase in circuit fidelity (49.99-63.36% max), depending on the chiplet size and topology. Additionally, owing to its ability to parallelize compilation, SEQC achieves 1.34-3.27$\times$ faster compilation on average (3.37-6.74$\times$ max) over a chiplet-unaware Qiskit baseline.

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Forward citations

Cited by 3 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score. Full citation record

  1. Optimizing Inter-chip Coupler Link Placement for Modular and Chiplet Quantum Systems

    quant-ph 2025-09 conditional novelty 6.0 of 10

    InterPlace selects inter-chip coupler placements in modular quantum systems via a multi-objective cost model, cutting SWAPs and inter-chip operations by up to 33.3% and boosting simulated fidelity by up to 53.0%.

  2. Improved Prefetching Techniques for Linked Data Structures

    cs.AR 2025-05 conditional novelty 6.0 of 10

    Linkey is a hybrid prefetcher that caches node layout hints from software to prefetch pointer-chasing data structures, reducing simulated cache misses by 13% geomean and improving IPC by 1.40% on a subset of custom be...

  3. Qubit Health Analytics and Clustering for HPC-Integrated Quantum Processors

    quant-ph 2025-08 conditional novelty 5.0 of 10

    Daily calibration data from a 20-qubit NISQ device cluster into stable and noisy qubit groups, and GHZ experiments confirm the stable group runs more reliable circuits.

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