From design to tape-out in SCL 180nm CMOS integrated circuit fabrication technology

Joydeep Basu

REVIEW 4 major objections 5 minor 17 references

From design to tape-out in SCL 180nm CMOS integrated circuit fabrication technology

T0 review · 4 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read One tutorial maps the complete route from schematic to tape-out at SCL's 180nm CMOS foundry.

desk verdict A genuinely useful tutorial for the SCL 180nm tape-out flow, with an overstated completeness claim; worthwhile for its niche and deserves refereeing. read the letter →

arxiv 1908.10674 v1 pith:5BRQN4NO submitted 2019-08-24 eess.SP

Joydeep Basu This is my paper · ORCID

classification eess.SP

keywords SCL180nmCMOStape-outanalogVLSIdesignCadenceVirtuosoCalibrelayoutverificationpost-layoutsimulationMultiProjectWafer

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper claims to assemble, in one place, all the information an analog VLSI designer needs to take a chip from a frozen schematic to a GDSII tape-out submission at the Semi-Conductor Laboratory's (SCL) 180nm CMOS foundry in Chandigarh, India. It documents the entire flow: schematic simulation in Cadence Virtuoso with the Spectre simulator, layout with design-rule, antenna, and layout-versus-schematic checks in Calibre, parasitic extraction and post-layout simulation, Monte Carlo analysis, assembly of the I/O ring from SCL's CIO150 pad library, and the closing tape-out steps of seal ring, silicon number, dummy metal fill, full-chip DRC, GDS generation, and CRC checksum. The practical point is that this workflow previously had to be reconstructed piecemeal, costing both academic designers and SCL liaison engineers considerable time, and the paper intends to close that gap so Indian academic and research groups can realistically use SCL's cost-effective Multi Project Wafer runs. If the guide works as written, a designer at any Indian institution with the right tool setup can produce a submission package SCL will accept.

What carries the argument

The machine that carries the argument is the standard academic verification toolchain — Cadence Virtuoso with Spectre for simulation and a foundry-calibrated Calibre deck for physical verification — wired to SCL's 180nm process design kit (the ts018_scl_prim library and the ts18sl_scl.lib model file). The load-bearing mechanism inside that machine is scale handling: schematics carry dimensions in micrometres and run with scale = 1e-6 in the simulator, while Calibre's parasitic extraction emits a netlist in absolute metres that must run with scale = 1; the CDF 'model' parameter, the copied 'spectre' view, and ADE-XL's MTS mode are the workaround that lets an extracted sub-circuit be instantiated like a symbol and co-simulated with schematic blocks. Around that core sit the procedural fixtures: the runset files drc.rsf, lvs.rsf, pex.rsf and antenna.rsf, the tsl18cio150.cdl pad netlist, SCL-supplied seal-ring and silicon-number GDS blocks, the DUMMYFILL Calibre deck driven by DUMMY.header, and the mosiscrc.c checksum utility that closes the loop on GDS integrity.

What would settle it

Run the paper's own demonstration project — an inverter core inside a CIO150 I/O ring — in the stated environment and follow every step. If the ring is not LVS clean, or the MTS co-simulation of the PEX netlist with a schematic block does not reproduce the all-schematic simulation results, the tutorial's claim of completeness fails; a sharper test is that reverting to the schematic view by unchecking MTS (as in Section 4.3) must exactly reproduce the schematic-only waveforms.

Watch

Extended reading notes

Core claim

The central claim is that the procedures collected here form a complete and sufficient route to tape-out in SCL's 180nm CMOS process, provided the standard tool environment is already in place. The contribution is not a new circuit technique but a documented, debugged sequence of operations, including several non-obvious workarounds: setting the Component Description Format (CDF) 'model' parameter and creating a 'spectre' view (a copy of a cell's symbol that makes the simulator use the extracted netlist instead of the schematic); using ADE-XL's Multi-Technology Simulation (MTS) to co-simulate extracted netlists alongside schematic-level blocks despite their conflicting scale settings (1e-6 for schematics, 1 for extracted netlists); editing the exported CDL file so Calibre LVS can compare the I/O ring against the pad definitions in tsl18cio150.cdl; and commenting out the '#define ANALOG' line in the LVS header when pad resistors trigger 'property w not found' errors. Each step is presented as it was exercised in the author's own environment, with the explicit caveat that environment and tool setup are deliberately left to a qualified lab administrator.

Load-bearing premise

The whole recipe presupposes that the designer already has a working SCL 180nm process design kit (ts018_scl_prim), the Calibre runset files, licensed Cadence and Calibre tools, and a lab administrator who has installed and configured them, because Section 2.1 explicitly leaves environment setup out.

Editorial extensions

If this is right

Indian academic and R&D groups can target SCL Multi Project Wafer runs without reconstructing the workflow from scratch, removing the information gap the paper identifies as the main source of lost time.
A designer who follows the guide ends with the full submission package SCL requires: GDSII, DRC and antenna results summaries, stream-out logs and layer lists, device lists, and the CRC checksum from mosiscrc.c.
The documented co-simulation method — CDF model parameter, spectre view, and MTS — gives a reusable recipe for any design that mixes extracted netlists with schematic blocks, not just SCL designs.
Because block-level DRC checks 356 rules while full-chip DRC checks 421, the guide lets designers budget verification effort and plan for dummy fill and seal ring before the final run.
The steps for the 1.8V CIO150 pad library carry over to the 3.3V CIO250 library, and the same flow works for digital cores, so the paper's reach extends beyond analog designs, as the author states.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

A testable extension would be to run the identical flow with newer tool releases: the appendix pins the versions (Virtuoso IC6.1.5, Calibre v2013.2, HSPICE J-2014.09), and the tutorial's viability on current Cadence and Calibre releases is an open question the paper does not address.
The need to hand-edit exported CDL files and comment out runset defines suggests the SCL runsets retain Tower-Semiconductor options; designers should expect to maintain small local patches to the runset headers as their designs grow.
The tutorial implicitly maps SCL's tape-out interface for the first time in the open literature, and that alone may lower the perceived risk of using an Indian foundry, so the guide's existence may be as valuable as its content.
If SCL's Multi Project Wafer program expands, this workflow could become the seed of a standard Indian academic tape-out curriculum, since it names every file and form a student needs in advance.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

This is a tutorial, not a research result, and it is honest about being one. What it does well is concrete: it walks a designer through the SCL 180nm tape-out flow from schematic to GDS with specific runset names, CDF edits, the I/O ring LVS hack, dummy fill, and the CRC step. That information has been scattered across SCL manuals, tool docs, and lab folklore; pulling it together is genuinely useful. The author clearly knows the flow, and the appendix's list of tool versions plus the acknowledgments to SCL engineers give me confidence the steps came from real tape-outs, not from imagination.

The soft spots are real but not disqualifying. The abstract promises 'all the requisite information,' but §2.1 explicitly leaves environment and tool setup to an experienced lab admin, and the steps depend on proprietary PDK files (ts018_scl_prim, drc.rsf, lvs.rsf, pex.rsf, DUMMY.header, tsl18cio150.cdl) that are referenced but not supplied or described well enough to reproduce independently. No test case, no validated output, no die photo. So the completeness claim is overstated; a reader with a different tool version or an updated PDK will have to adapt. That said, the appendix's hedge is appropriate: the author acknowledges the best-effort nature and that there may be better methods.

What the paper is not: it's not a scientific contribution, no new circuits, no measurements, no falsifiable predictions. The novelty score of 2 out of 10 is about right. But for a tutorial, novelty isn't the right yardstick. The value is in the details: the specific pad names in the I/O library, the LVS error workaround, the MTS co-simulation recipe, the dummy fill header editing. Those are the things that eat weeks of a student's time.

The citation pattern looks fine: it cites SCL and tool manuals, and the MOSIS checksum page. No self-citation issues.

Bottom line: if I were advising an Indian academic group about to submit to SCL, I'd hand them this paper and tell them to read it, then verify against their own lab setup. It deserves a serious referee — an experienced SCL tape-out engineer — to check for drift and version issues, but a desk reject would be wrong. I'd accept it for peer review as a tutorial contribution.

Referee Report

4 major / 5 minor

Summary. The paper is a tutorial for academic analog VLSI designers who wish to submit chip layouts to the SCL 180 nm CMOS foundry in Chandigarh. It walks through the entire design-to-tape-out flow: setting up a working directory and model libraries, schematic simulation in Cadence Virtuoso ADE, physical design with SCL layers, Calibre DRC/antenna/LVS, parasitic extraction and post-layout simulation (including a CDF-based 'spectre' view and MTS co-simulation), Monte Carlo analysis, construction of an I/O pad ring from SCL's CIO150/CIO250 libraries, and final tape-out steps (seal ring, silicon number, dummy fill, full-chip DRC, GDS export, and MOSIS CRC checksum). The abstract and introduction claim the paper provides all requisite information and guidance for preparing designs for SCL submission.

Significance. If the described flow is accurate, the tutorial addresses a real information gap for Indian academic groups using SCL MPW runs, and several documented workarounds—particularly the CDF 'spectre' view for PEX netlists, the MTS-based co-simulation of extracted blocks with schematic blocks, and the I/O ring CDL port-order fixes—are non-obvious and likely to save significant time. The paper is honest about its dependence on a pre-installed SCL PDK and gives exact EDA versions in the appendix. Its main limitations are that the completeness claim exceeds what the body delivers and that the flow is not independently validated by a worked example with run logs and a tape-out outcome. If the authors revise the scope claim and add a validation case, the paper would be a useful service piece for the IETE Journal of Education.

major comments (4)

[Abstract, §2.1] The abstract and introduction claim that the paper provides 'all the requisite information and guidance' needed to prepare chip designs for SCL fabrication, but §2.1 explicitly defers environment and tool setup to an experienced lab administrator and states that such details are not provided. Moreover, the steps in §§3–7 all presume the reader already has the proprietary SCL PDK (ts018_scl_prim), the runset files (drc.rsf, lvs.rsf, pex.rsf, antenna.rsf), the I/O libraries (CIO150/CIO250), and GDS templates that are referenced but not supplied or specified to the level of file versions and checksums. A reader who does not already have these components cannot execute the flow, so the completeness claim is not supported. Please either narrow the claim to 'a guide for designers with an installed and qualified SCL PDK environment' or add an appendix that itemizes every external file with its source, version, and a minimal smoke test.
[§3–§7 (overall validation)] The paper gives no evidence that the flow was executed end-to-end on a concrete design. There is no example with DRC/LVS/PEX run reports, no post-layout simulation output, and no statement of which designs successfully reached tape-out using these instructions. Because the central value of the paper is the reliability of this sequence, I ask for a small worked case study (for example, an inverter or comparator with an I/O ring) that includes the final GDS checksum and the DRC/antenna results-summary files mentioned in §7.4. This would let readers verify tool-version-specific behavior and would substantiate the claim that the steps are sufficient.
[§7.4, §7.3] §7.4 instructs the reader to edit a DRC.header file by uncommenting '#define CHIP' and to submit the resulting results-summary file to SCL, but DRC.header is never introduced earlier: §3.2 describes running DRC only in terms of loading drc.rsf, and the origin of DRC.header and of the results-summary file is not explained. Likewise, §7.3 tells the reader to run 'calibre -drc ./DUMMY.header' without explaining how this header relates to the Calibre runset format or what inputs it expects beyond the paths shown in Fig. 9. These omissions make the final tape-out steps impossible to execute from the paper alone and should be addressed with explicit file-location and generation instructions.
[Appendix, version sensitivity] The appendix lists exact EDA tool versions, but the text does not state which steps are sensitive to version changes. In particular, the CDF editing and MTS setup in §4.2–§4.3, the Calibre header edits in §6.4 and §7.4, and the runset file formats are likely to differ between tool releases. The authors should mark the tested versions on the relevant figures and commands and add a short 'version compatibility' note warning readers where newer releases may require different menu paths or runset syntax.

minor comments (5)

[§6.2.1, Fig. 6] The file name is given as tsl18cio150.cdl in the text but as ts018150.cdl in the figure caption; please make the names consistent and specify whether the file is part of the CIO150 distribution or the SCL PDK.
[§3.1] The grid snap instruction uses '0.005µm' and then says '0.005 (i.e., 5nm)'; please state the unit explicitly in the dialog entry (0.005 µm) to avoid ambiguity.
[§7.2] The instruction to 'edit individual characters by changing their property' is vague; please provide the property name or a screenshot showing the edited silicon number block.
[References [5], [6], [15], [16]] The references to internal SCL and Tower documents lack version identifiers and accession dates; since these documents are not publicly available, the authors should provide document numbers or contact information for obtaining them.
[Figures 2–4, 7] The figures are screen captures that appear difficult to read at print resolution, especially the smaller panels in Figs. 4 and 7; enlarging or redrawing the key panels would improve usability.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the paper is a procedural tutorial with no derived predictions, fitted parameters, or self-referential derivations.

full rationale

This is a tutorial paper, not a derivation. It reports procedural steps for using SCL's 180 nm PDK with Cadence and Calibre, citing external manuals and SCL-supplied runset, model, and GDS files. There is no quantity derived from another quantity, no parameter fitted to data, no uniqueness theorem invoked, and no ansatz whose justification reduces to a self-citation. The abstract's phrase 'all the requisite information and guidance' is immediately qualified in Section 2.1, which states that environment and tool setup 'is required to be done by a person experienced in setting up of such tools' and is not covered; this affects self-containedness, which is a completeness limitation, not circularity. Every load-bearing input, including drc.rsf, lvs.rsf, pex.rsf, ts018_scl_prim, CIO150/CIO250, and tsl18cio150.cdl, is an external foundry or tool artifact cited by the paper rather than defined in terms of the paper's conclusions. The paper also explicitly disclaims that its tool usage methods are necessarily best-case and states that any error or missing information is inadvertent. Because no step can be shown to reduce, by the paper's own equations or by self-citation, to its own inputs, the honest finding is no significant circularity.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

The paper introduces no new entities or fitted parameters; it relies on existing SCL PDK and EDA tools. The main assumptions are about the availability and correctness of proprietary components and the user's environment.

assumptions (3)

domain assumption SCL 180nm CMOS PDK (ts018_scl_prim), runset files (drc.rsf, lvs.rsf, pex.rsf), and dummy fill files are available and accurate as described.
The tutorial relies on these external components without validation; see Sections 2.1, 3.2, 7.3.
domain assumption The reader has access to licensed Cadence Virtuoso IC6.1.5, Mentor Calibre v2013.2, and a Linux environment with a qualified lab administrator.
Section 2.1 explicitly states tool setup is not covered and requires an experienced person.
domain assumption The described tool flows (e.g., Spectre, Calibre, MTS) behave as documented in their manuals, which are cited but not included.
The tutorial references tool manuals without providing them; correctness depends on those external documents.

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Cite this review

Pith. "Pith review of From design to tape-out in SCL 180nm CMOS integrated circuit fabrication technology." pith.science (2026). https://pith.science/paper/5BRQN4NO

@misc{pith2026190810674,
  author       = {Pith},
  title        = {Pith review of: From design to tape-out in SCL 180nm CMOS integrated circuit fabrication technology},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/5BRQN4NO}},
  note         = {Machine review of arXiv:1908.10674}
}

read the original abstract

Although India has achieved considerable capability in electronic chip design, but developing the infrastructure for capital-intensive semiconductor fabrication remains a challenge. The rising domestic and global demand for electronics products, the need of enhancing the country's high-technology talent pool, employment generation, and national security concerns dictates the Indian Government's heightened efforts in promoting electronics hardware manufacturing in the country. A recent milestone in this regard is the setting up of 180nm CMOS fabrication facility at SCL, Chandigarh. The Multi Project Wafer runs of this indigenous foundry promises to be a relatively cost-effective option for Indian academic and R&D institutions in realizing their designed VLSI circuits. Written from the perspective of an Analog VLSI designer, this tutorial paper strives to provide all the requisite information and guidance that might be required in order to prepare chip designs for submission to SCL for fabrication.

Figures

Figures reproduced from arXiv: 1908.10674 by the authors.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

17 extracted references · 17 canonical work pages

[1]

Human Resource and Skill Requirements in the Electronics and IT Hardware Sector (2013-17, 2017-22),

Report on “ Human Resource and Skill Requirements in the Electronics and IT Hardware Sector (2013-17, 2017-22),” National Skill Development Corporation (NSDC), India. Available at: http://meity.gov.in/esdm/hrd

work page 2013
[2]

Indian Electronics and IT Industry - An Overview,

R. Rastogi, “ Indian Electronics and IT Industry - An Overview,” IETE Technical Review , vol. 24 , pp. 163– 173, May–Jun. 2007

work page 2007
[3]

Innovation in the Indian Semiconductor Industry: The C hallenge of Sectoral Deepening,

W. W. Keller and L. W. Pauly, “Innovation in the Indian Semiconductor Industry: The C hallenge of Sectoral Deepening,” Business and Politics, vol. 11, no. 2, 2009

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[4]

of India

Website of the Ministry of Electronics & Information Technology (MeitY), Govt. of India . http://meity.gov.in

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[5]

http://www.scl.gov.in/cmos_fab_facility.html

Website of Semi-Conductor Laboratory , Chandigarh. http://www.scl.gov.in/cmos_fab_facility.html

work page
[6]

Name: DRS2_0018SL_SCL, SCL, Chandigarh

SPICE Models for TS18 Standard Logic Process , Doc. Name: DRS2_0018SL_SCL, SCL, Chandigarh. Figure 9. Example showing how to edit the DUMMY.header file. 10

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https://www.isro.gov.in/research-and- academia-interface

Website of Indian Space Research Organisation (ISRO). https://www.isro.gov.in/research-and- academia-interface

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https://phd.medialabasia.in

Website of Visvesvaraya PhD Scheme for Electronics & IT. https://phd.medialabasia.in

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[9]

of India

Website of Special Manpower Development Program , Ministry of Communication & Information Technology, Govt. of India. http://smdpc2sd.gov.in
[10]

Virtuoso Analog Design Environment L User Guide , version 6.1.5, Cadence Design Systems, Jun. 2013

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Calibre Interactive and Calibre RVE User’s Manual , version 2013.2, Mentor Graphics Corporation, 2013

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[12]

HSPICE Integration to Cadence Virtuoso Analog Design Environment User Guide, version E-2010.12, Synopsys, Dec. 2010

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Virtuoso Spectre Circuit Simulator Reference , v ersion 11.1, Cadence Design Systems, Sept. 2011

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[14]

Virtuoso Analog Design Environment XL User Guide , version 6.1.5, Cadence Design Systems, Mar. 2013

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[15]

1.0, 2003

TOWER 0.18 micron, 1.8 Volt Super Compact Core I/O Pad Library TSL18CIO150, Synopsys, Ver. 1.0, 2003

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[16]

Name: DR2_0018_SL, SCL, Chandigarh

Design Rules for TS18 Standard Logic Process for SCL , Doc. Name: DR2_0018_SL, SCL, Chandigarh
[17]

https://www.mosis.com/pages/ support/submit/term_chksum

Website of MOSIS. https://www.mosis.com/pages/ support/submit/term_chksum

Pith tools

Reviewed August 14, 2026 · model on record in the stance chip above.

[1] [1]

Human Resource and Skill Requirements in the Electronics and IT Hardware Sector (2013-17, 2017-22),

Report on “ Human Resource and Skill Requirements in the Electronics and IT Hardware Sector (2013-17, 2017-22),” National Skill Development Corporation (NSDC), India. Available at: http://meity.gov.in/esdm/hrd

work page 2013

[2] [2]

Indian Electronics and IT Industry - An Overview,

R. Rastogi, “ Indian Electronics and IT Industry - An Overview,” IETE Technical Review , vol. 24 , pp. 163– 173, May–Jun. 2007

work page 2007

[3] [3]

Innovation in the Indian Semiconductor Industry: The C hallenge of Sectoral Deepening,

W. W. Keller and L. W. Pauly, “Innovation in the Indian Semiconductor Industry: The C hallenge of Sectoral Deepening,” Business and Politics, vol. 11, no. 2, 2009

work page 2009

[4] [4]

of India

Website of the Ministry of Electronics & Information Technology (MeitY), Govt. of India . http://meity.gov.in

work page

[5] [5]

http://www.scl.gov.in/cmos_fab_facility.html

Website of Semi-Conductor Laboratory , Chandigarh. http://www.scl.gov.in/cmos_fab_facility.html

work page

[6] [6]

Name: DRS2_0018SL_SCL, SCL, Chandigarh

SPICE Models for TS18 Standard Logic Process , Doc. Name: DRS2_0018SL_SCL, SCL, Chandigarh. Figure 9. Example showing how to edit the DUMMY.header file. 10

work page

[7] [7]

https://www.isro.gov.in/research-and- academia-interface

Website of Indian Space Research Organisation (ISRO). https://www.isro.gov.in/research-and- academia-interface

work page

[8] [8]

https://phd.medialabasia.in

Website of Visvesvaraya PhD Scheme for Electronics & IT. https://phd.medialabasia.in

work page