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Toward a Global Regime for Compute Governance: Building the Pause Button

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arxiv 2506.20530 v1 pith:5P7RXDPP submitted 2025-06-25 cs.CY

Toward a Global Regime for Compute Governance: Building the Pause Button

classification cs.CY
keywords computeglobalmechanismstechnicalbuttoncapsdevelopmentframework
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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As AI capabilities rapidly advance, the risk of catastrophic harm from large-scale training runs is growing. Yet the compute infrastructure that enables such development remains largely unregulated. This paper proposes a concrete framework for a global "Compute Pause Button": a governance system designed to prevent dangerously powerful AI systems from being trained by restricting access to computational resources. We identify three key intervention points -- technical, traceability, and regulatory -- and organize them within a Governance--Enforcement--Verification (GEV) framework to ensure rules are clear, violations are detectable, and compliance is independently verifiable. Technical mechanisms include tamper-proof FLOP caps, model locking, and offline licensing. Traceability tools track chips, components, and users across the compute supply chain. Regulatory mechanisms establish constraints through export controls, production caps, and licensing schemes. Unlike post-deployment oversight, this approach targets the material foundations of advanced AI development. Drawing from analogues ranging from nuclear non-proliferation to pandemic-era vaccine coordination, we demonstrate how compute can serve as a practical lever for global cooperation. While technical and political challenges remain, we argue that credible mechanisms already exist, and that the time to build this architecture is now, before the window for effective intervention closes.

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Cited by 2 Pith papers

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  1. Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification

    cs.CR 2026-04 unverdicted novelty 5.0

    Proposes a feasibility taxonomy of 20 hardware-level AI compute governance mechanisms organized by monitoring, verification, and enforcement, with mappings to regulatory scenarios that highlight immaturity of treaty-v...

  2. LLM Harms: A Taxonomy and Discussion

    cs.CY 2025-12 unverdicted novelty 3.0

    This paper proposes a taxonomy of LLM harms in five categories and suggests mitigation strategies plus a dynamic auditing system for responsible development.