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REVIEW 3 major objections 5 minor 80 references

The Pangaea architecture claims that a quantum bus—an auxiliary gauge-code strip—extends lattice surgery into a three-dimensional fault-tolerant interconnect, enabling long-range and multi-qubit parity measurements across heterogeneous topo

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2026-08-04 18:48 UTC pith:5WPAYNQH

load-bearing objection Real architecture idea with believable simulations, but the O(dN) advantage rests on an unproven distance claim. the 3 major comments →

arxiv 2608.01887 v1 pith:5WPAYNQH submitted 2026-08-03 quant-ph

The Pangaea Architecture: Fault-Tolerant Heterogeneous Topological Codes via a Quantum Bus

Sheir Yarkoni , Chen Scheim , Daniel Hakshuri , Nadav Katz This is my paper
classification quant-ph MSC 81P7081P68 PACS 03.67.Pp
keywords quantum error correctionlattice surgerytopological codessurface codecolor codequantum busheterogeneous codesmagic state distillation
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper claims a quantum bus—an auxiliary gauge-code strip—can mediate fault-tolerant logical operations between remote, heterogeneous topological code patches while keeping nearest-neighbor physical connectivity. The bus is presented as a three-dimensional generalization of lattice surgery: products of local gauge-check outcomes reconstruct joint logical operators, so long-range and multi-qubit Pauli measurements are native. The main quantitative claim is that this costs O(d N_L) physical qubits for N_L distance-d logical qubits, compared with O(d^2 N_L) for planar lattice-surgery routing, giving up to a 10-fold qubit reduction at the 50-logical-qubit scale. Fault tolerance is supported by pseudo-threshold simulations for surface–surface and surface–color joint measurements and by a subsystem-code accounting of the merged bus. If correct, the bus resolves the routing bottleneck of planar architectures and enables code-agnostic modular quantum computing.

Core claim

The central discovery is that lattice surgery's mediating strip can be stretched into a shared bus orthogonal to the code patches, so that N_L logical qubits plug into slots along the bus and their boundary ancillas double as bus check qubits. During a joint measurement the merged system is a subsystem code with parameters [[n_merge, N_L−1, µ(d−1)/2, d]], where µ is the number of color-code patches; the dropped checks at color-code boundaries become gauge degrees of freedom, and the bus stores no logical information. Intermediate Pauli factors cancel row by row, leaving only the intended boundary logical operators dressed by a known bus stabilizer. The paper verifies fault tolerance with pse

What carries the argument

The quantum bus is an auxiliary gauge-code strip of width d and length ℓ=N_L−1, connecting N_L code patches; the scissors operator is the four-stage fault-tolerant protocol (pre-op, merge, split, post-op) that realizes joint parity measurements through the bus. The bus works by measuring local gauge checks whose row-by-row products cancel intermediate Pauli factors, leaving only the boundary logical operators, and by reusing patch boundary ancillas as bus checks so the extra qubit cost is dℓ rather than d^2ℓ. It also serves as a heterogeneous interface: fixing the bus's gauge degrees to match a patch's rough boundary lets surface and color codes share one measurement primitive, with dropped

Load-bearing premise

The load-bearing premise is that the merged code—logical patches plus bus—keeps distance-d protection for the joint measurement, including at heterogeneous surface–color interfaces; the paper supports this with a degree-of-freedom count rather than a proof that no lower-weight logical operator exists.

What would settle it

A circuit-level fault-path enumeration over the merged surface–color bus: if any fault chain of weight less than d flips the measured joint parity without triggering a detector—for example, for a color-code patch in a middle bus slot after the stabilizer-splitting correction—the distance-d assumption fails, and the pseudo-threshold trends would not persist to larger codes.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

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If this is right

  • Measurement-based CNOTs can be performed between non-adjacent logical qubits without moving or expanding the code patches.
  • At N_L=50 and code distances 9–13, Pangaea uses roughly 3.5× to 10× fewer physical qubits than planar surface-code lattice surgery at matched logical error rates.
  • Surface–color joint parity measurements are fault tolerant with pseudo-thresholds close to homogeneous surface–surface values (0.36% vs 0.43% at d=3; 1.25% vs 1.27% at d=7).
  • The native heterogeneous 15-to-1 magic-state distillation module uses roughly half the space-time volume of a conventional surface-code-only factory (66 vs 121 tile-time units).
  • Additional logical qubits can be added by extending the bus rather than redesigning the interaction region, making the architecture modular.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • If the merged-code distance truly stays d at every bus length, the bus would make inter-logical connectivity overhead nearly linear in distance, potentially shifting the breakeven point at which high-rate qLDPC codes become necessary—a comparison the paper does not make.
  • The O(dN) advantage is computed at the logical level under the assumption that three-dimensional inter-layer couplers are as clean as planar nearest-neighbor links; the paper lists flip-chip and through-silicon vias as candidates, but correlated noise across stacked layers could eat into the gain.
  • The same gauge-fixing construction may port to planar tile codes or other high-rate codes, but the anti-commutation fix for mid-bus patches would need to be re-derived for each new code family; the paper leaves that as future work.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper introduces Pangaea, a fault-tolerant quantum architecture in which a three-dimensional quantum bus—an auxiliary gauge-code strip—mediates joint logical parity measurements between remote surface-code and color-code patches, generalizing lattice surgery. It claims that multi-qubit interactions for N_L distance-d logical qubits require only O(d N_L) physical qubits, versus O(d^2 N_L) for traditional two-dimensional layouts, and reports a 10x qubit reduction at the 50-logical-qubit scale. The main numerical evidence consists of pseudo-threshold simulations for bus-mediated M_XX primitives for homogeneous surface-surface and heterogeneous surface-color layouts at d=3,5,7 and bus lengths up to 7. The paper also proposes a heterogeneous 15-to-1 magic-state distillation module and a native multi-qubit Pauli measurement primitive.

Significance. If the central distance-preservation claim can be established, Pangaea would be a significant architectural contribution: it offers a native heterogeneous code interface, long-range multi-qubit parity measurements, and an asymptotic qubit saving over planar lattice surgery. The paper's strengths include explicit circuit-level Stim simulations with a detailed and carefully documented detector model (Appendix C), pseudo-thresholds for both homogeneous and heterogeneous cases, and a coherent degree-of-freedom bookkeeping in Appendix E. The main load-bearing gap is that the distance of the merged bus-plus-patch code is asserted but not proven; the scaling and resource comparisons depend directly on this assumption. The paper also explicitly assumes the M_ZZ case by symmetry and extrapolates logical error rates beyond the simulated distances.

major comments (3)
  1. [III.A, Eq. (6), Appendix E] The merged code distance d in Eq. (6) is asserted, not proven. Appendix E counts only n, k, and r (rank/gauge degrees of freedom); it never computes the minimum weight of a logical operator of the merged code. This cannot rule out a sub-d logical operator localized at the dropped-check interface shown in Fig. 5(c), especially for heterogeneous surface-color boundaries. The verification criterion in Sec. III.B ('no undetected single-fault logical error') is checked only at d=3,5,7, not for all d. Since the O(dN_L) scaling and the 10x resource comparison at d=13 rely on distance-d protection of the merged code, this is load-bearing. Please provide a proof of distance, or an explicit minimum-weight-logical-operator computation for representative merged patches.
  2. [III.B, M_ZZ assumption] Only the M_XX primitive is simulated; the text states that 'the result also holds for M_ZZ under a simple exchange of observables.' The measurement-based CNOT (Sec. II.C) and the heterogeneous distillation module (Sec. IV) depend on Z-type bus interactions. The Z-bus has different boundary and commutation details (see the non-commuting weight-6 stabilizers in Appendix D), so the exchange symmetry is not self-evident. Add M_ZZ pseudo-threshold simulations, or else give a rigorous argument that the detector-error model and logical-operator weights are identical under Z<->X exchange.
  3. [III.C, Fig. 7(b)] The d>=9 logical-error rates in Fig. 7(b) are extrapolated from a fit of p_L = A(d) p_phys^{(d+1)/2} to d=3,5,7 simulated points. The 'up to 10x fewer qubits' claim at matched p_L is therefore a model-dependent projection, not a simulated result, and it inherits the unproven distance-d assumption from Eq. (6). The text labels these as order-of-magnitude estimates, but the abstract presents the 10x figure as an outcome. Re-label the claim as conditional on distance preservation and provide independent evidence (simulations at d=9, or a rigorous scaling argument) before asserting the advantage.
minor comments (5)
  1. [II.B] The statement that a length-\ell bus provides 'simultaneous protection of up to 2d+\ell in the complementary basis' is not derived. A short argument or citation would help.
  2. [III.B / Fig. 6] The caption should clarify that the dashed vertical lines are finite-distance crossing estimates from linear interpolation, not an asymptotic threshold fit; the text already says this but the figure alone is ambiguous.
  3. [Appendix C] The simulation setup is described in impressive detail, but no code or data repository is referenced. For reproducibility, please provide the Stim circuits and decoder configuration, or state a public repository.
  4. [IV] The 15-to-1 distillation resource estimate (A_P≈6, V_P=66) is not simulated; it assumes bus-mediated rotations have the same logical error rate and timescale as standard lattice surgery. State this explicitly and classify the comparison as an estimate.
  5. [Eq. (6)] In Eq. (6), the subsystem-code parameters should be defined explicitly (n, k, r, d). The symbol \mu is defined in the text, but a reader encountering Eq. (6) only may confuse the third parameter with distance. Consider using [[n,k,r,d]] notation with an explicit definition.

Circularity Check

0 steps flagged

No significant circularity identified: the central qubit-count scaling is derived by explicit counting, the fault-tolerance primitives are tested by independent simulations, and the d>=9 resource projection is transparently labeled as an extrapolation rather than a hidden fit.

full rationale

Walking the derivation chain, the main claims do not reduce to their inputs. The O(dN_L) bus overhead is derived in Appendix B by explicit counting: n_bus = (ell+1)(d+1)/2 + d ell = O(dN_L), compared with O(d^2 N_L) for the 2D ancilla region; there is no fitted parameter in this step. The fault-tolerance of the bus primitive is supported by independent Stim simulations at d=3,5,7 with MWPM and BPOSD decoders, with pseudo-thresholds obtained as finite-distance crossing estimates rather than as restatements of the desired conclusion. The heterogeneous merged-code parameters in Eq. (6) and Appendix E count degrees of freedom to establish k and r, but Appendix E does not compute the minimum-weight logical operator, so the distance label d in Eq. (6) is asserted rather than proved. That is a genuine support gap for the larger-distance resource claims, but it is not circularity: the paper does not define the merged code's distance in terms of the conclusion it draws from that distance. The 10x projection in Fig. 7(b) extrapolates the authors' own simulated p_L data to d>=9, and the paper explicitly states these points 'should be read as order-of-magnitude estimates, not as simulated results'; this is an openly labeled extrapolation, not a fitted parameter renamed as a prediction. There are no load-bearing self-citations: no result is justified by the present authors' prior work, and the cited lattice-surgery, subsystem-surgery, and gauge-fixing facts are external. Consequently, no load-bearing step is equivalent by construction to its inputs.

Axiom & Free-Parameter Ledger

2 free parameters · 4 axioms · 1 invented entities

The central claims rest on the untested distance-d of the merged heterogeneous code, the applicability of subsystem lattice surgery, and a fitted error-rate extrapolation. The quantum bus itself is an architectural proposal with internal simulation evidence only.

free parameters (2)
  • A(d) = not reported (fit to simulated p_L at d=3,5,7)
    The logical error rate model p_L = A(d) p_phys^((d+1)/2) is fitted to the authors' simulation data and extrapolated to d>=9 to produce the 10x qubit advantage claim in Sec III C and Fig 7(b).
  • p_phys = 1e-3
    Assumed physical error rate for the resource comparison in Sec III C. It is a chosen target input, not a fitted value, but the 10x claim depends on it.
axioms (4)
  • domain assumption Standard lattice surgery and subsystem lattice surgery framework apply to the bus geometry
    The protocol is built on the claim that the bus is a direct extension of lattice surgery (Sec II A, II B), relying on refs [11,23,28,78] for the fault-tolerant properties of merge/split.
  • domain assumption Color-code patches lose (d-1)/2 boundary checks during the merge
    Used in Appendix E to compute gauge degrees of freedom; cited from ref [28] without proof for the specific superdense color-code layout.
  • ad hoc to paper The merged bus-plus-patch code has distance d
    The central fault-tolerance claim assumes distance-d protection of the joint measurement (Sec II B, Sec III A). The degree-of-freedom counting in Appendix E does not bound logical operator weights.
  • ad hoc to paper The superdense color-code geometry supports a rough boundary compatible with the bus
    Sec III A states the boundary is defined to match the bus structure, but no explicit stabilizer map or proof of compatibility is provided beyond a figure.
invented entities (1)
  • Quantum bus no independent evidence
    purpose: Auxiliary gauge-code strip that mediates long-range and multi-qubit logical Pauli measurements between heterogeneous topological code patches
    The bus is a proposed architectural component. Its fault-tolerance is supported only by in-paper pseudo-threshold simulations, not by an externally falsifiable prediction.

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Cite this review

Pith. "Pith review of The Pangaea Architecture: Fault-Tolerant Heterogeneous Topological Codes via a Quantum Bus." pith.science (2026). https://pith.science/paper/5WPAYNQH

@misc{pith2026260801887,
  author       = {Pith},
  title        = {Pith review of: The Pangaea Architecture: Fault-Tolerant Heterogeneous Topological Codes via a Quantum Bus},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/5WPAYNQH}},
  note         = {Machine review of arXiv:2608.01887}
}
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read the original abstract

We introduce Pangaea, a fault-tolerant quantum architecture that uses a quantum bus to mediate logical operations between remote patches of two-dimensional topological codes. The bus is an auxiliary gauge-code strip whose measurements reconstruct joint logical operators while preserving nearest-neighbor physical connectivity. Enabling native heterogeneous topological codes and multi-qubit Pauli operations, the quantum bus can be interpreted as a three-dimensional generalization of lattice surgery. We require only $O(dN_L)$ physical qubits to implement multi-qubit interactions for $N_L$ distance-$d$ logical qubits, compared to $O(d^2N_L)$ of traditional two-dimensional architectures. At the 50-logical-qubit scale, Pangaea uses up to $10\times$ fewer physical qubits than planar surface-code architectures at matched logical error rates. We verify fault-tolerance of long-range measurement-based CNOT primitives for both surface--surface and surface--color joint parity measurements using pseudo-threshold simulations. We use this protocol to construct a native heterogeneous 15-to-1 magic-state distillation module using the quantum bus. These results establish Pangaea as a scalable architecture for three-dimensional fault-tolerant quantum computing that resolves the routing bottleneck of planar lattice surgery.

Figures

Figures reproduced from arXiv: 2608.01887 by Chen Scheim, Daniel Hakshuri, Nadav Katz, Sheir Yarkoni.

Figure 1
Figure 1. Figure 1: FIG. 1. Lattice surgery between two distance-3 rotated surface-code patches via a quantum bus, shown explicitly for an [PITH_FULL_IMAGE:figures/full_fig_p003_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. Three-dimensional layout of two orthogonal [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. Full measurement-based CNOT between non [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Circuit-level description of a measurement-based [PITH_FULL_IMAGE:figures/full_fig_p005_3.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. Bird’s-eye view of a single bus strip connecting surface-to-surface (left) and surface-to-color (right) patches. [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. Pseudo-threshold simulations for bus-mediated M [PITH_FULL_IMAGE:figures/full_fig_p008_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. Physical qubit count and iso-resource comparison [PITH_FULL_IMAGE:figures/full_fig_p009_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. Pangaea implementation of the 15-to-1 magic-state [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9. An illustration of a native three-qubit [PITH_FULL_IMAGE:figures/full_fig_p015_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10. A middle logical-qubit of distance [PITH_FULL_IMAGE:figures/full_fig_p016_10.png] view at source ↗

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This paper was first reviewed by deepseek-v4-flash on August 4, 2026.