Paper Citation Record · LEDGER

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction

As of 7 August 2026, this Paper Citation Record lists 45 of 45 outbound references and 0 inbound Pith citation observations for arXiv:2506.00857.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2506.00857 v1

Coverage vector

measured 45 of 45 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-07T12:01:38.134195Z

measured 45 of 45 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

45 of 45 outbound references displayed

verified exact3
verified fuzzy37
unresolved3
parse uncertain0
malformed identifier0
metadata mismatch2

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation d70580d9-1aac-4e18-afb1-a1b62fa7bbbb · outbound

This paper cites An overview of hardware security and trust: Threats, countermeasures, and design tools,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction An overview of hardware security and trust: Threats, countermeasures, and design tools,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.950609Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e8681912-2c13-4250-a903-4f86dcc1f24c · outbound

This paper cites IP protection and supply chain security through logic obfuscation: A systematic overview,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction IP protection and supply chain security through logic obfuscation: A systematic overview,

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.937899Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 0f834a96-513c-4952-8fad-93ac9c68716a · outbound

This paper cites A survey on ip watermarking techniques,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction A survey on ip watermarking techniques,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.925922Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 0cbbe62c-49b4-4c90-9345-3ec0373ad0e5 · outbound

This paper cites A survey on split manufacturing: Attacks, defenses, and challenges,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction A survey on split manufacturing: Attacks, defenses, and challenges,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.913974Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 814e4dd3-cf5f-44d6-8450-fedd58b68ff7 · outbound

This paper cites Benchmarking at the frontier of hardware security: Lessons from logic locking,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Benchmarking at the frontier of hardware security: Lessons from logic locking,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.902299Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation f80ef4c9-f54c-4ef8-bd2f-d9e4c0db45e2 · outbound

This paper cites Openfpga: An open-source framework for agile prototyping customizable fpgas,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Openfpga: An open-source framework for agile prototyping customizable fpgas,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.890561Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 2bb6cd06-8baa-4723-b346-307263b38a43 · outbound

This paper cites Fabulous: An embedded FPGA framework,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Fabulous: An embedded FPGA framework,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.877792Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 4c9dc51a-b14c-4558-962c-8ce6d488ef01 · outbound

This paper cites Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.865378Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ef5a5f49-1d5e-4ca7-b1df-8c4639db3bb5 · outbound

This paper cites Exploring efpga-based redaction for ip protection,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Exploring efpga-based redaction for ip protection,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.851948Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation b5514663-6e7c-4949-8e72-792c8ff55b22 · outbound

This paper cites Arnold: An efpga-augmented risc-v soc for flexible and low-power iot end nodes,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Arnold: An efpga-augmented risc-v soc for flexible and low-power iot end nodes,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.840505Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 825df033-18c7-4591-a38f-666787f6874d · outbound

This paper cites Decoy: Deflection-driven hls-based computation partitioning for obfuscating intellectual property,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Decoy: Deflection-driven hls-based computation partitioning for obfuscating intellectual property,

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.827914Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation db6717e6-cf27-4216-ac83-4775be092e71 · outbound

This paper cites Fpga architecture: Principles and progression,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Fpga architecture: Principles and progression,

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.816421Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 00d4482b-5496-4e1d-a03c-419ded2a2a2a · outbound

This paper cites The effect of lut and cluster size on deep-submicron fpga performance and density,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction The effect of lut and cluster size on deep-submicron fpga performance and density,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.806240Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 267ec8bf-89f9-41ca-976d-34d6d2e6d7d9 · outbound

This paper cites FABulous: An Embedded FPGA Framework,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction FABulous: An Embedded FPGA Framework,

Reference 15

Resolution: metadata mismatch; raw_fallback, observed 2026-08-07T12:01:39.647535Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation faa016cc-3a02-4547-b36a-06223500bd79 · outbound

This paper cites OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.794604Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 0a3d3167-f7c2-40ca-be9e-ff500743a754 · outbound

This paper cites OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.782441Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 5ec9efe6-0cb1-4bee-b498-d3f2696b59fd · outbound

This paper cites PRGA: An Open-Source FPGA Research and Prototyping Framework,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction PRGA: An Open-Source FPGA Research and Prototyping Framework,

Reference 19

Resolution: unresolved; no resolver link, observed 2026-08-07T12:01:35.764811Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e64a6e7d-9cfd-40b7-a463-6fa36c537ca8 · outbound

This paper cites Architecture Description and Packing for Logic Blocks with Hierarchy, Modes and Complex Interconnect,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Architecture Description and Packing for Logic Blocks with Hierarchy, Modes and Complex Interconnect,

Reference 20

Resolution: metadata mismatch; raw_fallback, observed 2026-08-07T12:01:39.205909Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e6e8a032-2afd-4615-817c-fc79f034db73 · outbound

This paper cites FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs,

Reference 21

Resolution: verified exact; raw_fallback, observed 2026-08-07T12:01:38.880912Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 51b9017a-7f75-4530-9b4e-4bd5db3357ea · outbound

This paper cites Not all fabrics are created equal: Exploring efpga parameters for ip redaction,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Not all fabrics are created equal: Exploring efpga parameters for ip redaction,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.764730Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 1aa67d20-1314-4cfe-be3f-420c72983015 · outbound

This paper cites Intel Xeon+FPGA Platform for the Data Center,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Intel Xeon+FPGA Platform for the Data Center,

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.753364Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation aba9351c-816d-4999-8972-8adadc23a0d0 · outbound

This paper cites Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes,

Reference 24

Resolution: verified exact; raw_fallback, observed 2026-08-07T12:01:38.583816Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation d57650c5-d146-45e7-adfe-4d373413eee9 · outbound

This paper cites An overview of hardware intellectual property protection,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction An overview of hardware intellectual property protection,

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.742857Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation b024e5d4-70c9-462c-a847-4f545321bacc · outbound

This paper cites From fpgas to obfuscated easics: Design and security trade-offs,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction From fpgas to obfuscated easics: Design and security trade-offs,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.730678Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation b3d527c2-b5e4-4df8-9aab-02c428a31a91 · outbound

This paper cites Keynote: A disquisition on logic locking,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Keynote: A disquisition on logic locking,

Reference 27

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.718971Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 88a2371e-9908-407b-8486-dc09ab1ba610 · outbound

This paper cites Evolution of logic locking,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Evolution of logic locking,

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.707839Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 6279c803-b887-4ad1-a1fd-9fc583f27994 · outbound

This paper cites Logic locking at the frontiers of machine learning: A survey on developments and opportunities,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Logic locking at the frontiers of machine learning: A survey on developments and opportunities,

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.696732Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 0b706206-8abe-425f-bd0e-73c9e866bc2b · outbound

This paper cites Logic locking for ip security: A comprehensive analysis on challenges, techniques, and trends,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Logic locking for ip security: A comprehensive analysis on challenges, techniques, and trends,

Reference 30

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.685284Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 978a8453-f3b8-418f-83e4-4ce8e16be380 · outbound

This paper cites Evaluating the security of logic encryption algorithms,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Evaluating the security of logic encryption algorithms,

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.673494Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 7b68cf28-e7ab-4333-b30b-2d69410eaa8c · outbound

This paper cites Omla: An oracle-less machine learning-based attack on logic locking,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Omla: An oracle-less machine learning-based attack on logic locking,

Reference 32

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.662928Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 89ac1252-25c9-4e4b-af52-723fbfdd8215 · outbound

This paper cites Unsail: Thwarting oracle-less machine learning attacks on logic locking,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Unsail: Thwarting oracle-less machine learning attacks on logic locking,

Reference 33

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.651402Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation fa0603bc-9460-4cb7-b7bb-eae817a83089 · outbound

This paper cites Challenging the security of logic locking schemes in the era of deep learning: A neuroevolutionary approach,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Challenging the security of logic locking schemes in the era of deep learning: A neuroevolutionary approach,

Reference 34

Resolution: verified exact; doi, observed 2026-08-07T12:01:38.271197Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 2ab595f8-dd18-4800-9e0e-d3641afcba94 · outbound

This paper cites Designing ml-resilient locking at register-transfer level,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Designing ml-resilient locking at register-transfer level,

Reference 35

Resolution: unresolved; no resolver link, observed 2026-08-07T12:01:37.121728Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 7b0b0475-57f1-45c0-a54b-18fe22bb8cb1 · outbound

This paper cites Top-down physical design of soft embedded fpga fabrics,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Top-down physical design of soft embedded fpga fabrics,

Reference 36

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.640913Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 211de837-3918-4253-889d-844f3d243557 · outbound

This paper cites Shell: Shrinking efpga fabrics for logic locking,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Shell: Shrinking efpga fabrics for logic locking,

Reference 37

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.631013Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 140f2ef7-1212-4af5-a5cd-ed49ab448cf3 · outbound

This paper cites Investigating the effect of different efpgas fabrics on logic locking through hw redaction,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Investigating the effect of different efpgas fabrics on logic locking through hw redaction,

Reference 38

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.620760Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 4a5dd148-4372-493c-a560-e5877e1cb2d1 · outbound

This paper cites Evaluating the security of efpga-based redaction algorithms,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Evaluating the security of efpga-based redaction algorithms,

Reference 39

Resolution: unresolved; no resolver link, observed 2026-08-07T12:01:37.455539Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 39478826-f175-43e9-8c08-cb1b676afab0 · outbound

This paper cites CycSAT: SAT-based attack on cyclic logic encryptions,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction CycSAT: SAT-based attack on cyclic logic encryptions,

Reference 40

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.610180Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 8ddd8958-59aa-4a5f-970c-9ce425b96730 · outbound

This paper cites Evaluating the robustness of large scale efpga-based hardware redaction,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Evaluating the robustness of large scale efpga-based hardware redaction,

Reference 41

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.599698Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ecaf5b35-9696-4610-9cfa-a9b4106d792d · outbound

This paper cites FuncTeller: How well does eFPGA hide functionality?.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction FuncTeller: How well does eFPGA hide functionality?

Reference 42

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.588472Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 6a9c820e-05dc-4d1b-98cb-94182388242d · outbound

This paper cites Mantis: Machine learning-based approximate modeling of redacted integrated circuits,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Mantis: Machine learning-based approximate modeling of redacted integrated circuits,

Reference 43

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.572357Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ec17b681-6a9f-48e9-83f7-8e467a4c2706 · outbound

This paper cites Thwarting all logic locking attacks: Dishonest oracle with truly random logic locking,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Thwarting all logic locking attacks: Dishonest oracle with truly random logic locking,

Reference 44

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.432187Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e365a596-fa8b-4391-9ede-940f18aba49e · outbound

This paper cites Pyverilog: A python-based hardware design processing toolkit for verilog hdl,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction Pyverilog: A python-based hardware design processing toolkit for verilog hdl,

Reference 45

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.200035Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 63c4021b-1573-4d6d-ae65-ab1545955911 · outbound

This paper cites IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits,

Reference 46

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:40.119200Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation f781f3df-1aef-4fc8-89b5-5a70e94aeaa1 · outbound

This paper cites ASSURE: RTL locking against an untrusted foundry,.

ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction ASSURE: RTL locking against an untrusted foundry,

Reference 47

Resolution: verified fuzzy; raw_fallback, observed 2026-08-07T12:01:39.900963Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Pith citing papers

No inbound Pith citation observations are available.