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arxiv: 2603.11075 · v2 · pith:7TCGL6OQnew · submitted 2026-03-10 · 💻 cs.AR · cs.AI

VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification

Runbang Hu , Bo Fang , Bingzhe Li , Yuede Ji This is my paper

Pith reviewed 2026-05-21 11:07 UTC · model grok-4.3

classification 💻 cs.AR cs.AI
keywords congestion predictionheterogeneous graphVLSI layoutEDA verificationchip designearly predictionrouting congestion
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The pith

VeriHGN builds an enhanced heterogeneous graph to unify circuit netlists with spatial grids for better early-stage congestion prediction in VLSI designs.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper proposes VeriHGN as a framework that models both logical circuit connections and physical layout spaces together in one graph structure. This unified representation aims to capture how design intent translates into physical placement more accurately than previous separate modeling approaches. If successful, it allows designers to spot potential routing congestion problems much earlier in the process, before committing to time-intensive detailed routing steps. Sympathetic readers would see value in shortening the overall chip design cycle and reducing costly iterations in electronic design automation workflows.

Core claim

VeriHGN is a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization.

What carries the argument

enhanced heterogeneous graph unifying circuit components and spatial grids into a single relational representation

If this is right

  • Consistent improvements in prediction accuracy over state-of-the-art methods on ISPD2015, CircuitNet-N14, and CircuitNet-N28 benchmarks.
  • Higher correlation metrics for congestion estimates.
  • Enables early-stage prediction that reduces the number of routing iterations needed.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • This unification approach might support iterative layout optimization by feeding predictions back into placement tools.
  • Similar relational graph structures could extend to related verification tasks such as timing or power analysis in the same designs.

Load-bearing premise

That constructing an enhanced heterogeneous graph from netlist and layout features without post-routing data will faithfully capture the key interactions between logical and physical aspects.

What would settle it

Applying VeriHGN to a new industrial VLSI design outside the tested benchmarks and observing no gains in prediction accuracy or correlation metrics compared to prior methods.

Figures

Figures reproduced from arXiv: 2603.11075 by Bingzhe Li, Bo Fang, Runbang Hu, Yuede Ji.

Figure 1
Figure 1. Figure 1: Example of routing congestion formation in a place￾ment–routing workflow. (a): multiple logic blocks are placed on the layout grid with interconnecting nets. (b): global rout￾ing paths overlap and compete for limited routing resources, creating localized routing congestion. (c): accumulated rout￾ing demand is visualized as a congestion map, where colors indicate congestion levels (low to high), and red reg… view at source ↗
Figure 2
Figure 2. Figure 2: Overview of VeriHGN graph construction. Starting from the original circuit design ( 1 ), we derive (i) a hierarchical grid representation ( 2 ) capturing multi-level spatial structure, (ii) a netlist graph ( 3 ) modeling circuit connectivity and (iii) a cell-to-grid relationship graph ( 4 ) that encodes the spatial assignment of cells to grid locations. These components are finally integrated into a unifie… view at source ↗
Figure 3
Figure 3. Figure 3: Relation-based message passing. Messages are prop￾agated along different relation types (cell–net, grid–net, geom–cell, and cell–grid) using relation-specific MLPs, en￾abling information exchange across circuit components and spatial grids. where (Δ𝑥𝑖𝑗, Δ𝑦𝑖𝑗) denote relative displacement, and 𝑑manh, 𝑑eucl are the Manhattan and Euclidean distances between cells. Hierarchical grid edges connect grid nodes ac… view at source ↗
Figure 5
Figure 5. Figure 5: illustrates the final prediction stage following the message passing process. Separate prediction heads are applied to the final cell embeddings to produce instance-level and region-level con￾gestion estimates. This dual supervision allows the model to learn ℎ𝑒 𝑐𝑒𝑙𝑙 ℎ𝑒 𝑔𝑒𝑜𝑚 ℎ𝑒 𝑔𝑟𝑖𝑑 ℎ𝑒 𝑛𝑒𝑡 [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Sensitivity of VeriHGN to key hyperparameters [PITH_FULL_IMAGE:figures/full_fig_p009_6.png] view at source ↗
read the original abstract

As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations. However, although prior methods incorporate both netlist connectivity and layout features, they often model the two in a loosely coupled manner and primarily produce numerical congestion estimates. We propose VeriHGN, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization. Experiments on industrial benchmarks, including ISPD2015, CircuitNet-N14, and CircuitNet-N28, demonstrate consistent improvements over state-of-the-art methods in prediction accuracy and correlation metrics.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The manuscript proposes VeriHGN, a verification framework that constructs an enhanced heterogeneous graph unifying netlist circuit components with spatial grid features from the layout. This relational representation is intended to enable more faithful modeling of interactions between logical design intent and physical realization for early-stage routing congestion prediction. Experiments on industrial benchmarks (ISPD2015, CircuitNet-N14, CircuitNet-N28) report consistent gains in accuracy and correlation metrics over prior state-of-the-art methods.

Significance. If the reported gains are shown to arise specifically from the cross-type relational edges rather than from general modeling capacity or feature choices, the work could meaningfully advance pre-routing verification in EDA flows and reduce costly routing iterations. The heterogeneous-graph unification of netlist and layout data is a timely direction given the increasing scale of VLSI designs. The use of industrial-scale benchmarks is a positive aspect, but the significance hinges on whether the central modeling claim is substantiated beyond aggregate performance numbers.

major comments (2)
  1. [§3.2] §3.2 (Heterogeneous Graph Construction): The central claim that the enhanced heterogeneous graph 'unifies circuit components and spatial grids into a single relational representation' enabling faithful logical-physical interaction modeling is load-bearing, yet the manuscript provides no ablation that removes or isolates the cross-domain edges (netlist-to-grid). Without this, it is impossible to determine whether the reported improvements on ISPD2015/CircuitNet-N14/N28 stem from the unification or from other architectural or feature-engineering decisions.
  2. [§5.1] §5.1 (Baseline Comparisons): The experimental results claim consistent outperformance over state-of-the-art methods, but the description does not clarify whether the baselines were re-run using identical pre-routing netlist-plus-layout inputs or retained their original (possibly post-routing) feature sets. This distinction is essential because the paper's premise is strictly pre-routing prediction; mismatched inputs would undermine the cross-method comparison.
minor comments (2)
  1. [Figure 2] Figure 2: The diagram of the heterogeneous graph would benefit from explicit labeling of node and edge types (e.g., 'netlist node', 'grid cell', 'connectivity edge', 'spatial proximity edge') to make the unification claim visually verifiable.
  2. [Table 3] Table 3: The correlation coefficient column lacks units or normalization details; reporting both Pearson and Spearman values would strengthen the metric comparison.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback. We address each major comment below, providing clarifications and committing to revisions where appropriate to strengthen the substantiation of our claims.

read point-by-point responses

  1. Referee: [§3.2] §3.2 (Heterogeneous Graph Construction): The central claim that the enhanced heterogeneous graph 'unifies circuit components and spatial grids into a single relational representation' enabling faithful logical-physical interaction modeling is load-bearing, yet the manuscript provides no ablation that removes or isolates the cross-domain edges (netlist-to-grid). Without this, it is impossible to determine whether the reported improvements on ISPD2015/CircuitNet-N14/N28 stem from the unification or from other architectural or feature-engineering decisions.

    Authors: We agree that an explicit ablation isolating the contribution of the cross-domain (netlist-to-grid) edges is necessary to substantiate the central modeling claim. In the revised manuscript we will add a new ablation experiment that removes these heterogeneous edges while retaining all other architectural components and features, and we will report the resulting drops in accuracy and correlation metrics on the ISPD2015, CircuitNet-N14, and CircuitNet-N28 benchmarks. revision: yes

  2. Referee: [§5.1] §5.1 (Baseline Comparisons): The experimental results claim consistent outperformance over state-of-the-art methods, but the description does not clarify whether the baselines were re-run using identical pre-routing netlist-plus-layout inputs or retained their original (possibly post-routing) feature sets. This distinction is essential because the paper's premise is strictly pre-routing prediction; mismatched inputs would undermine the cross-method comparison.

    Authors: All baselines were re-implemented and evaluated using the identical pre-routing netlist connectivity and layout-grid features employed by VeriHGN. We will revise the description in §5.1 to explicitly document the input feature sets used for each baseline, confirming that the comparison is performed under the same pre-routing setting. revision: yes

Circularity Check

0 steps flagged

No significant circularity; derivation chain is empirically grounded

full rationale

The paper introduces VeriHGN as a heterogeneous graph construction that unifies netlist connectivity with spatial grid features for pre-routing congestion prediction. All reported results consist of accuracy and correlation metrics measured on external industrial benchmarks (ISPD2015, CircuitNet-N14, CircuitNet-N28) against prior SOTA methods. No equation or modeling step is shown to reduce by construction to a fitted parameter renamed as a prediction, nor does any central claim rest on a self-citation chain whose validity is presupposed within the paper itself. The performance gains are presented as outcomes of experiments on held-out data rather than tautological re-statements of the input graph construction.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 0 invented entities

The abstract provides no explicit free parameters, axioms, or invented entities; the contribution is described at the level of a new modeling framework and empirical results.

pith-pipeline@v0.9.0 · 5695 in / 1132 out tokens · 55463 ms · 2026-05-21T11:07:40.911439+00:00 · methodology

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Reference graph

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