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REVIEW 3 major objections 4 minor 71 references

Controller-decoder system requirements derived by implementing Shor's algorithm with surface code

T0 review · 3 major / 4 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read A full end-to-end Shor-21 circuit shows that non-Clifford error-corrected computation is within reach if the decoding feedback loop stays within tens of microseconds.

desk verdict Concrete CDS requirements for a small non-Clifford circuit, but the >90% fidelity claim is conditional on unstated post-selection acceptance. read the letter →

arxiv 2412.00289 v4 pith:AOCFZYQT submitted 2024-11-29 quant-ph physics.app-ph

Yaniv Kurman , Lior Ella , Nir Halay , Oded Wertheim , Yonatan Cohen This is my paper · ORCID
classification quant-phphysics.app-ph MSC 81P6868Q12 PACS 03.67.Lx
keywords Shor'salgorithmsurfacecodesnon-Cliffordcircuitsquantumerrorcorrectionfeed-forwardlatencydecodingtaskscontroller-decodersystemmagic-stateinitialization
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper works out, end to end, what a classical control system must do to run the next milestone in quantum error correction: a non-Clifford circuit with real-time feedback. Using Shor's algorithm factoring 21 as a representative case, it compiles the logical circuit through a surface-code layout down to physical gates and simulates the whole thing. The result is a concrete specification: the controller-decoder loop must finish its decoding-dependent feed-forward within tens of microseconds, which calls for several decoders working in parallel with fast links to the controller. The same simulation indicates that roughly 1000 physical qubits at a 0.1% physical error rate, with surface-code distance 5, are enough to factor 21 with above 90% logical fidelity. This matters because it turns “non-Clifford circuits need fault tolerance” into numbers a hardware or control-system team can design against.

What carries the argument

The machinery is the full compilation stack from logical algorithm to physical pulse-level circuit: the logical Shor circuit is converted into a surface-code-compatible form, laid out as an explicit 18-surface lattice-surgery circuit, and then compiled to physical gates and simulated with an extended stabilizer-circuit simulator. The argument is carried by three quantitative tools: a binomial error budget that counts 14 non-fault-tolerant magic-state initializations and 296 fault-tolerant gates; a decomposition of the circuit into 13 inter-dependent decoding tasks whose space-time volumes set the classical processing load; and a delay-error formula $P_{\text{delay}}=N \cdot P_{\text{FT}} \cdot T_{\text{delay}}/T_{\text{round}}$ that converts feed-forward latency into added logical error. These tools turn a single example into system-level specifications for controller, decoder, and communication channel.

What would settle it

Simulate or run the actual non-Clifford circuit with real T gates and real-time feed-forward at $d=5$ and 0.1% physical error, and check whether the total logical error stays under 10%; a deviation from the predicted ~5% floor that grows with the number of feed-forward operations would show the substitution missed correlated errors. A second check: measure logical fidelity with the total controller-decoder latency set to tens of microseconds and then to, say, 100 microseconds; the delay-error formula predicts a specific added error, and data that contradict that scaling would falsify the latency budget.

Watch

Extended reading notes

Core claim

The central claim is that a non-Clifford QEC circuit of the scale of 15-to-20 non-Clifford gates can be executed successfully on near-term hardware, provided the classical controller-decoder system meets a set of well-defined real-time requirements. For the 5-logical-qubit Shor circuit, the compiled surface-level circuit contains 18 surfaces, 13 feed-forward gates, and 13 decoding tasks, with up to five decoding tasks active in parallel and dependencies between tasks that must be communicated. The end-to-end physical simulation, which substitutes S gates for T gates and omits feed-forward, shows logical fidelity above 90% at a physical error rate of 0.1% with distance $d=5$ (about 1000 physical qubits), while 0.3% error is insufficient. The error budget is dominated by the 14 non-fault-tolerant magic-state initializations, which cause logical error to saturate near 5% as distance grows; therefore the same framework implies that larger distances will not help until magic-state initialization fidelity improves. The authors state the results as general guidelines for any non-Clifford circuit with a few thousand physical qubits and roughly 15 non-Clifford gates, and in particular for 15-to-1 magic-state distillation.

Load-bearing premise

The claim that the real circuit reaches above 90% fidelity rests on the assumption that replacing the non-Clifford T gates with S gates and removing the decoding-dependent feed-forward operations leaves the circuit's error behavior essentially unchanged, so the binomial error budget computed from the substituted circuit applies to the actual non-Clifford circuit.

Editorial extensions

If this is right

  • A 1000-qubit superconducting processor with 0.1% physical error can execute a non-Clifford error-corrected circuit with about 15 non-Clifford gates at above 90% logical fidelity.
  • Controller-decoder systems must support real-time conditional gates, a local pre-decoding stage, and up to five parallel decoding tasks with inter-task communication; the total feed-forward latency budget is tens of microseconds.
  • Increasing code distance beyond $d=5$ gives no fidelity benefit at 0.1% physical error until the error in non-fault-tolerant magic-state initialization is reduced, so qubit scaling alone is not the bottleneck.
  • Magic-state distillation circuits with similar non-Clifford gate counts inherit the same latency and decoding-parallelism requirements.
  • For superconducting stabilizer rounds of about one microsecond, the full Shor factoring-21 run completes in under a millisecond, so the classical system, not the quantum circuit duration, sets the real-time challenge.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the T-to-S substitution hides correlated errors that real feed-forward logic would introduce, the 90% fidelity threshold could move; a natural extension is to run the same compiled circuit with a non-stabilizer simulator at small distance to quantify the gap.
  • The 13-task, five-parallel decoding workload derived here could serve as a standardized stress test for controller-decoder systems, complementing the paper's own benchmark by giving competitors a concrete circuit to run.
  • The microsecond latency budget scales with stabilizer-round time, so slower qubit platforms such as trapped ions would need different absolute budgets; the paper's numbers are specific to superconducting hardware.
  • Because non-fault-tolerant initialization dominates the error budget, hardware roadmaps that focus on raw qubit count may be less effective than roadmaps that improve magic-state injection fidelity; the paper's framework suggests prioritizing the latter.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 4 minor

Summary. The paper derives controller-decoder system (CDS) requirements for executing a non-Clifford circuit, using Shor's algorithm for factoring 21 as a concrete case. The authors compile a 5-logical-qubit circuit to a surface-code layout (18 surfaces, 13 decoding tasks, 40 timestamps) and then to a physical-level circuit, simulate it with stim, and estimate logical errors from a binomial budget of 14 non-fault-tolerant (nFT) magic-state initializations and 296 fault-tolerant (FT) gates. They conclude that a physical error rate of 0.1% and about 1000 physical qubits (distance 5) suffice for >90% logical fidelity, and that the closed-loop feed-forward latency must stay within tens of microseconds, achievable by parallelizing decoders and fast controller-decoder communication.

Significance. If the results hold, this is a valuable end-to-end case study that moves the discussion of QEC control requirements from abstract decoder benchmarks to a concrete compiled circuit. The paper provides explicit resource estimates (Table 2), an open-source simulation repository, and a clear decomposition of decoding tasks into parallel, interdependent units (Figure 5). The claimed tens-of-microseconds latency budget and the identification of nFT-initialization error as the dominant bottleneck are useful guidelines for near-term experimental demonstrations. However, the headline fidelity and 'successful execution' claims are conditional on (i) an unstated post-selection acceptance probability and (ii) a Clifford approximation that omits T gates and feed-forward, so the significance is currently bounded by these caveats.

major comments (3)
  1. [Section III, paragraph 2] The >90% logical fidelity claim is conditional on post-selection during nFT initialization, but the manuscript does not report the per-injection acceptance probability or the joint acceptance probability over the 14 nFT initializations. The text states that post-selection keeps only cases with all-'0' stabilizer measurements during the surface expansion, and Figure 4b shows 'with PS' error rates. For a single execution, the success probability is p_accept^14 × (1 − P_logical_cond), where p_accept is the per-injection acceptance rate. If p_accept = 0.99, the joint acceptance is about 0.87, so even with P_logical = 0.05 the overall success is about 0.83, below the promised 90%; if p_accept is lower, the success rate drops sharply. The abstract's statement that 0.1% error and 1000 qubits 'are sufficient for the successful execution of the circuit' is therefore not established unconditionally. The authors should report p_accept, the unconditional success probability, and the expected number of repetitions, which also affects the latency and resource estimates in Table 2 and Section V.
  2. [Abstract and Section III] The simulation omits two features of the actual non-Clifford circuit: decoding-dependent mid-circuit feed-forward and non-Clifford T gates, which are replaced by S gates and |S> initializations. The abstract and Section I claim that the paper simulates 'the complete fault-tolerant factorization circuit at the physical level,' which is an overstatement. The simulated circuit is a Clifford approximation, and the error budget in Figure 3c assumes 14 nFT gates and 296 FT gates, but the actual simulated circuit has different nFT operations (S injection instead of T injection) and no feed-forward. The authors should either revise the claim to 'approximate simulation' or provide a quantitative argument, e.g., by simulating the T-gate injection with a stabilizer-based approximate sub-circuit or by showing that the S-for-T substitution and removal of feed-forward do not change the logical error rate beyond the reported error bars.
  3. [Table 1 and Section I] There is an internal inconsistency in the number of feed-forward operations: Section I states '12 feed-forward operations and 13 decoding tasks,' while Table 1 lists 'Feed-forward gates 13.' If the discrepancy arises from counting the final measurement differently, that should be stated explicitly; otherwise the count should be corrected. This matters because the number of feed-forward operations directly determines the number of decoding tasks and the latency analysis in Section IV.
minor comments (4)
  1. [Table 1] Typo: 'Toal measurements' should be 'Total measurements.'
  2. [Section IV, paragraph 1] The text says 'Figure 4b shows these dependencies and the active time of each task,' but the dependencies appear in Figure 5b; Figure 4 is the simulation results figure. Please correct the reference.
  3. [Section IV, paragraph 4] The equation for the additional error due to decoding delay is garbled in the typeset text (P_delay = N⋅P_FT^T_delay/d⋅T_round is not rendered clearly). Please typeset the equation properly, e.g., P_delay = N · P_FT · T_delay / (d · T_round) or with the intended exponent, and define each variable in the text.
  4. [Section III, paragraph 3] The paper states that logic was verified through 3 out of 5 logical stabilizers; please explain why only 3 were verified and state the implication for the reported logical error estimate, since untracked stabilizers could in principle hide additional errors.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the controller-decoder requirements and fidelity thresholds are derived from explicit simulations with physical error rate and code distance as free inputs; the paper's only self-citation is background and not load-bearing.

full rationale

The derivation chain is self-contained. The CDS latency and parallelism requirements are obtained by compiling a concrete Shor-21 logical circuit to a surface-level circuit (Figure 2c, Table 1) and then to a physical-level stim simulation with p_phys and d as free parameters; the reported logical-error curves are simulation outputs, not fitted inputs. The binomial error budget (Figure 3c) is built from independently simulated single-surface FT errors and nFT magic-state initialization errors, and the full physical-level simulation (Section III) reproduces the same ~5% saturation rather than being tuned to match it. The latency-error formula P_delay = N * P_FT * T_delay/T_round is an explicit additive model, not a fit to the conclusion that tens of microseconds are acceptable. The only self-citation, Ref. [35] by the same group, is used for background ('preliminary holistic benchmarking approaches') and to note that prior benchmarks exist; the paper's own analysis does not rely on it for any load-bearing step. One non-circular caveat should be flagged: Section III states that the simulation 'does not include two features of the factorization circuit: decoding-dependent mid-circuit gate modification and non-Clifford gates,' and it substitutes S gates and |S> initializations for T gates and |T> initializations, while also applying post-selection (PS) during nFT initialization. The paper does not report the per-injection PS acceptance probability, so the >90% 'logical fidelity' claim is conditional on all 14 nFT injections passing PS; unconditional per-shot success could be lower. This is a completeness and interpretation concern about the headline claim, not a circularity of the derivation, because the fidelity estimate is still computed from an explicit error model rather than being defined in terms of the conclusion.

Assumptions & free parameters 4 free parameters · 4 assumptions · 0 invented entities

The central claims rest on standard surface-code physics plus several hardware and error-model assumptions. The main free inputs are the physical error rate, code distance, and stabilizer-round time, all scanned or assumed rather than fitted. No new entities are introduced.

free parameters (4)
  • physical_error_rate p_phys = scanned: 0.1%, 0.3%
    Chosen as representative near-term superconducting processor performance; not fitted, but the main fidelity conclusions depend on these values.
  • code_distance d = scanned: 3, 5, 7, 9
    Surface code distance is swept to find the minimum needed for >90% fidelity; central claim uses d=5 with p=0.1%.
  • stabilizer_round_time T_round = 1 microsecond
    Assumed typical for superconducting qubits; used to convert latency in rounds to microseconds and derive the tens-of-microseconds budget.
  • single_qubit_gate_error_ratio = p_phys/10
    Error model assumption: single-qubit gates have ten times lower error than two-qubit gates and measurements; not independently justified.
assumptions (4)
  • domain assumption Surface code threshold and logical error scaling P_log proportional to (p_phys/p_th)^((d+1)/2)
    Invoked in Eq. 1 and throughout the error budget; based on cited literature (Refs. 1, 22).
  • domain assumption Uniform depolarizing error model: two-qubit gates and measurement flips at rate p_phys, single-qubit gates at p_phys/10, no correlated errors
    Used for all simulations and error estimates; a strong simplification of real superconducting hardware.
  • domain assumption T-gate feed-forward can be delayed until the next non-commuting gate, and delayed feed-forward accumulates only as idling surface error
    Basis for computing P_delay in Section IV and for the tens-of-microseconds latency claim.
  • domain assumption Non-fault-tolerant magic-state initialization with hook injection and post-selection on '0' syndromes yields an error that does not decrease with code distance
    From Ref. 51; central to the error saturation result.

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Cite this review

Pith. "Pith review of Controller-decoder system requirements derived by implementing Shor's algorithm with surface code." pith.science (2026). https://pith.science/paper/AOCFZYQT

@misc{pith2026241200289,
  author       = {Pith},
  title        = {Pith review of: Controller-decoder system requirements derived by implementing Shor's algorithm with surface code},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/AOCFZYQT}},
  note         = {Machine review of arXiv:2412.00289}
}
read the original abstract

Quantum Error Correction (QEC) is regarded as the most promising path to quantum advantage. The success of QEC relies on achieving quantum gate fidelities below the error threshold of the QEC code, while accurately decoding errors through classical processing of the QEC stabilizer measurements. In this paper, we uncover the critical system-level requirements from a controller-decoder system (CDS) necessary to successfully execute the next milestone in QEC: a non-Clifford circuit. Using a representative non-Clifford circuit, of Shor factorization algorithm for the number 21, we convert the logical-level circuit to a QEC surface code circuit and finally to the physical level circuit. By taking into account realistic implementation aspects using typical superconducting qubit processor parameters, we reveal a broad range of core requirements from any CDS aimed at performing error corrected quantum computation. Our findings indicate that the controller-decoder closed-loop latency must remain within tens of microseconds, achievable by distributing decoding data into several decoders while ensuring fast communication between decoders and with the controller. By extending existing simulation techniques, we simulate the complete fault-tolerant factorization circuit at the physical level, demonstrating that near-term hardware performance in the scale of 0.1% physical error rates and 1000 qubits, are sufficient for a successful circuit execution. Overall, the requirements outlined here set the stage for near- and medium-term experimental realizations of non-Clifford QEC circuits.

Figures

Figures reproduced from arXiv: 2412.00289 by the authors.

Figure 1
Figure 1. Overview of non-Clifford circuits with QEC, their compilation, and [PITH_FULL_IMAGE:figures/full_fig_p005_1.png] view at source ↗
Figure 2
Figure 2. The steps to the surface-level factorization circuit. (a) [PITH_FULL_IMAGE:figures/full_fig_p008_2.png] view at source ↗
Figure 3
Figure 3. Error estimation for the factorization circuit. (a) Single FT error, e.g., the logical error in idling 𝑑 stabilizer rounds. (b) nFT preparations error. Increasing the code’s distance does not reduce the logical error. (c) The estimated error of the factorization circuit calculated (binomially) as the probability for an odd number of flips in 14 nFT gates and 296 FT gates. Inset: The estimated error of the factorizat… view at source ↗
Figures from the paper (3 more)
Figure 4
Figure 4. Figure 4: Simulation of the factorization circuit. (a) [PITH_FULL_IMAGE:figures/full_fig_p012_4.png]
Figure 5
Figure 5. Figure 5: Decoding aspects of shallow non-Clifford circuits. (a) [PITH_FULL_IMAGE:figures/full_fig_p016_5.png]
Figure 6
Figure 6. Figure 6: The controller-decoder system requirements for running non-Clifford circuits in QEC. The controller must be able to execute the optimized sequence, with low latency with the QPU, as well as local classical operations such classical branching and pre-decoding. The commu…

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Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.