Hardware architecture and routing-aware training for optimal memory usage: a case study

Jimmy Weber; Melika Payvand; Theo Ballet

REVIEW 4 major objections 5 minor 17 references

Hardware architecture and routing-aware training for optimal memory usage: a case study

T0 review · 4 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read This paper proposes a hardware-algorithm co-design method that trains spiking neural networks against a per-hop sparsity profile, making them fully mappable to the Mosaic architecture and cutting routing memory by 10x at equal SHD accuracy.

desk verdict A sensible, incremental extension of DeepR to per-hop sparsity profiles for neuromorphic routing, but the headline gains over the baseline need an ablation and the mappability claim needs direct verification. read the letter →

arxiv 2412.01575 v1 pith:AVXW6DDH submitted 2024-12-02 cs.ET

Jimmy Weber , Theo Ballet , Melika Payvand This is my paper · ORCID

classification cs.ET

keywords hardware-awaretrainingrouting-awaredynamicarchitecturesearchDeepRMosaicspikingneuralnetworksmemoryoptimizationHeidelbergDigits

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper tries to establish that routing memory on a neuromorphic chip can be optimized during neural-network training rather than only during hardware design. It extends the DeepR dynamic-pruning algorithm to enforce a per-hop sparsity profile, meaning a budget on the fraction of active connections at each routing distance, and uses that profile as a cheap proxy for the exact placement-and-routing cost on the Mosaic small-world architecture. On the Spiking Heidelberg Digits task, networks trained this way are fully mappable to the hardware and, compared with non-routing-aware training, gain about 5% accuracy at equal memory or match accuracy with an order of magnitude less memory. The paper also observes that test accuracy is nearly constant across seeds that share the same profile, suggesting the connectivity profile itself, not the exact wiring, dominates performance.

What carries the argument

The load-bearing object is the hop-distance sparsity profile $P(\theta) = \{p_d(\theta) \mid d \in \{0,\dots,d_{\max}\}\}$, defined as the fraction of active connections between neuron tiles whose routing distance is $d$ hops. The paper argues that this profile is a computationally cheap and reliable proxy for the exact Mosaic mapping function, because memory usage across networks with identical profiles has minimal variance. The DeepR algorithm supplies the mechanism: each epoch performs SGD on the loss with an $\ell^1$ penalty, prunes weak connections, and randomly re-assigns inactive connections so that the element-wise profile constraint $P(\theta) \leq \hat{P}$ is restored, turning a non-differentiable hardware constraint into a trainable sparsity budget.

What would settle it

Run the exact Mosaic placement-and-routing algorithm on many random networks that all satisfy the same per-hop sparsity profile but concentrate long-distance connections on different tiles. If any of them exceeds a routing tile's capacity, or if required memory varies widely across the set, then the sparsity profile is not a sufficient proxy and the reported mappability guarantee would not hold.

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Extended reading notes

Core claim

The central claim is that the routing-memory cost of mapping a network onto the Mosaic architecture is well approximated by a per-hop sparsity profile $P(\theta) = \{p_d(\theta)\}$, where $p_d(\theta)$ is the fraction of active connections between neuron tiles at hop distance $d$, and that this profile can be enforced during training. Extending DeepR so that pruning and random re-assignment keep $P(\theta) \leq \hat{P}$ elementwise yields networks that satisfy the routing constraints of the hardware. The paper reports that, on SHD, this routing-aware training reaches about 5% higher accuracy than non-routing-aware training at the same memory count, and that at matched accuracy (68.5%) it requires about ten times fewer memory elements. The supporting observation is that the standard deviation of memory usage across networks with identical $P$ is minimal, which is what makes the profile trustworthy as a proxy.

Load-bearing premise

The load-bearing premise is that the routing memory a network needs is determined almost entirely by how many active connections it has at each routing distance; if two networks with the same distance profile can need very different amounts of memory, a network accepted by the proxy might still not fit on the chip.

Editorial extensions

If this is right

Routing constraints on mesh-like neuromorphic hardware can be imposed during training through pruning and re-assignment, avoiding costly evolutionary search or a differentiable mapping function.
At a fixed memory count, routing-aware training improves SHD test accuracy by about 5 percentage points over L1-regularized non-routing-aware training.
At matched accuracy, the routing-aware network uses roughly ten times fewer routing-memory elements, which could allow larger networks on the same chip.
Because accuracy varies little across seeds with the same profile, the profile can be treated as a design variable, giving a memory-accuracy trade-off curve before committing to a particular chip configuration.
The near-constant accuracy across identical profiles suggests the exact connectivity matrix is less important than its distance statistics, so training could target profiles rather than individual connections.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

A testable extension is to compute hop-distance profiles for other network-on-chip topologies, such as mesh or hierarchical routing; if the proxy logic transfers, routing-aware training becomes a general recipe instead of a Mosaic-specific fix.
The profile-determines-accuracy observation points toward reverse co-design: choose a routing architecture whose feasible profiles match the natural connectivity statistics of a task, then train against that profile.
The same pruning-and-reassignment mechanism could be combined with learned placement, since the proxy decouples training from the exact placement step; the paper does not explore this direction.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

You should know two things about this one. First, the per-hop sparsity profile P(θ) is a new and genuinely useful idea: it turns the non-differentiable routing constraint into a per-distance sparsity target that DeepR can enforce during training. That is a clean, simple contribution, and the paper does it honestly. Second, the headline numbers are not yet backed up by the experiments as written. The comparison baseline is a non-routing-aware network trained with an L1 regularizer, not DeepR with a global sparsity constraint. So the reported 5% accuracy gain and 10x memory reduction could just as easily come from DeepR's rewiring dynamics as from the routing-awareness. That is a confound the authors need to address with a proper control. The paper's strengths are real. Adapting DeepR's prune-and-reassign loop to element-wise per-hop constraints is straightforward and the pseudocode is clear. The SHD results show low accuracy variance across seeds for a fixed profile, which supports the claim that the profile, rather than the exact connectivity, drives performance. That is an interesting observation with implications for hardware design. The use of an actual neuromorphic architecture (Mosaic) as a case study keeps the work grounded. The soft spots are mostly about verification. Figure 2d asserts that memory usage variance across networks with identical P is minimal, but no variance data or error bars are shown. That is load-bearing because the whole method treats P as a sufficient proxy. The abstract says the resulting network is fully mappable, but the paper never shows a direct routing/mapping check on trained networks; mappability is inferred from the profile. Also, the abstract says "same number of parameters" while the body says "same memory count" — those are different claims, since memory count includes routing memory, and the discrepancy should be fixed. None of this is fatal. The central derivation is correct, the idea is genuinely new, and the flaws are addressable with a few experiments: a DeepR-global-sparsity control, proxy variance measurements, and a direct mappability check. I would send this to peer review. It is a solid case study that will be useful to anyone building hardware-aware training for neuromorphic chips, provided the authors tighten the comparisons.

Referee Report

4 major / 5 minor

Summary. The paper addresses the problem of optimizing on-chip routing memory when deploying spiking neural networks on the Mosaic neuromorphic architecture. The authors extend the DeepR training algorithm so that, instead of enforcing only a global connection sparsity, it enforces a per-hop sparsity profile P(θ), which they propose as a computationally efficient proxy for the memory and routability constraints of the Mosaic routing fabric. They evaluate the method on the Spiking Heidelberg Digits (SHD) classification benchmark, sweeping over target profiles and comparing against a non-routing-aware baseline from prior work. The reported results claim that the routing-aware trained network is fully mappable to the hardware, achieves 5% higher accuracy at the same memory count, and achieves iso-accuracy with about 10x less memory compared to the non-routing-aware baseline.

Significance. The problem is genuinely important: on-chip routing memory is a scarce resource in neuromorphic processors, and connecting training-time constraints to hardware mappability is a useful direction. The central idea of replacing an expensive mapping check with a per-hop sparsity profile is plausible and, if properly validated, would be a practical contribution. The paper also has positive reproducibility features: it reports 30-seed runs for each profile and a parameter sweep over profiles. However, the current empirical validation is not yet convincing because the baseline comparison does not isolate the routing-aware mechanism, and the proxy sufficiency claim is supported only by a single figure without quantitative detail. The contribution is therefore promising but needs stronger evidence before the central claims can be accepted.

major comments (4)

[§IV, Fig. 3b; Abstract] The main quantitative claims ('5% more accuracy using the same number of parameters' and 'iso-accuracy with 10x less memory usage') are made against a non-routing-aware baseline taken from reference [10], which uses an L1-regularized training objective. This comparison does not isolate the effect of routing-aware per-hop constraints, because the routing-aware method also replaces the global-sparsity DeepR mechanism with a different training algorithm. A proper control would be DeepR with a global sparsity constraint matched to the same total memory or parameter budget, with the same network size, dataset, and training setup. Without such a control, the reported gains could be due to DeepR itself rather than to the per-hop routing constraint, and the central claim that routing-aware training is responsible for the improvement is not established.
[§III, Fig. 2d] The entire method rests on the claim that the per-hop sparsity profile P(θ) is a sufficient proxy for routing memory, i.e., that networks with identical P have near-identical memory footprints. The only support is Fig. 2d, which shows a plot but no description of how the networks were sampled, how many networks were used, what architecture sizes were covered, or what 'minimal' standard deviation means quantitatively. The paper should report the distribution of memory counts for identical profiles, including worst-case deviations, across multiple architecture sizes and profile values, and should specify the exact metric used to judge sufficiency. Without this, the proxy may fail for profiles not tested, which would invalidate the mappability and memory-savings claims.
[§III, 'Routing in Mosaic' and 'Approximating the Routing constraints'] The paper does not specify how the routing memory is actually computed: how the shared-path routing is implemented, how occupancy rates in Fig. 2c are derived from a connectivity matrix, how the required NT and RT crossbar sizes are determined, and what condition defines 'fully mappable'. Since the memory count is a central quantitative output and the proxy is supposed to approximate this mapping, the mapping procedure must be described precisely enough to be reproduced and checked. As written, the reader cannot verify the memory counts or the claim that the trained network is fully mappable.
[§III, Algorithm 2; §IV] Algorithm 2 is underspecified in a way that affects reproducibility. In particular, the initialization step 'Initialize network weights θ such that P(θ) = P_hat' is nontrivial for arbitrary target profiles, and the pruning and reassignment steps f and g must preserve per-hop sparsity constraints simultaneously, not just a global count. The paper should describe how connections are pruned and reassigned while maintaining the element-wise conditions P(θ) ≤ P_hat and P(θ) = P_hat, and how this interacts with the L1 penalty and threshold selection. Additionally, the parameter sweep in Fig. 3a only varies p1 and p3 while setting all other hop sparsities to zero; the choice of this restricted family and its coverage of the feasible profile space should be justified.

minor comments (5)

[Abstract; §IV] The abstract says '5% more accuracy using the same number of parameters,' but Section IV compares memory count, not parameter count; the wording should be aligned with the actual comparison.
[Fig. 3b] The horizontal axis is labeled 'Memory count ×10^6' but the unit (memory elements, bytes, or bits) is not defined, and there are no error bars on either method; adding confidence intervals or standard deviations would strengthen the comparison.
[Eq. (1)] The definition of p_d(θ) uses notation 'S(θ_{i,j})|_{H(NT_i,NT_j)=d}' that is not fully defined; in particular, the meaning of θ_{i,j} as a submatrix or block and how S is applied to that block should be stated explicitly.
[Fig. 2d caption] The caption states 'RT and NT sizes refer to input size of a square crossbar array,' but the relationship between crossbar input size and memory count is not explained; a brief definition in the text would clarify the memory metric.
[§III, 'DeepR' background] The global sparsity S(θ) = |θ|_0 / N^2 and the per-hop profile P(θ) = {p_d(θ)} are both called 'sparsity'; to avoid confusion, the text should explicitly state that P is a vector of per-hop sparsities and show how it relates to the global sparsity.

Circularity Check

0 steps flagged · score 1.0 of 10

No significant circularity: memory is imposed as an input constraint via the sparsity profile, and accuracy is the independently measured outcome.

full rationale

The paper's derivation chain is not circular. It defines the per-hop sparsity profile P(θ) = {p_d(θ)} as a descriptive statistic of the connectivity matrix, trains networks under a target profile P̂ via DeepR-style pruning and reassignment (Algorithm 2), and then reports (i) measured test accuracy on SHD and (ii) memory counts produced by the Mosaic routing simulator. The memory count is an input/constraint variable in this loop, not a fitted output: choosing P̂ fixes the architecture and therefore the memory count, while accuracy remains an independent empirical outcome. The only self-referential element is the proxy validation in Section III ('the standard deviation of memory resource usage across networks with identical P values is minimal'), but this is an empirical check within the same routing simulator, not an assumption of the target result; if the proxy were insufficient, the 'fully mappable' claim would fail, which is a correctness risk rather than circularity. The self-citation to Mosaic [10] supplies the hardware case study and the non-routing-aware baseline; it is prior published work by an overlapping author, but the central claims are not justified by that citation alone, and DeepR [15] and SHD [17] are external. No prediction reduces to its inputs by construction.

Assumptions & free parameters 2 free parameters · 3 assumptions · 0 invented entities

The central claim rests on two structural assumptions: the fidelity of the routing model and the sufficiency of the sparsity profile. The numeric comparison also relies on matching prior baseline conditions, which the paper does not demonstrate.

free parameters (2)

target sparsity profile P_hat (per-hop sparsity targets) = For the sweep, p1 in {0.5, 0.7, 1.0} and p3 in {0.05, 0.1, 0.15, 0.2, 0.25, 0.3} approximately from Fig.
These targets are chosen by hand in a parameter sweep and determine both the memory footprint and achievable accuracy. They are not fitted to the test set, but selection over the sweep introduces a multiple-comparison consideration.
DeepR hyperparameters (L1 penalty lambda, pruning threshold, reassignment rule, learning rate, network size) = not reported
The training procedure is specified only by pseudo-code; the concrete values that produce the reported curves are omitted, leaving the central result under-specified.

assumptions (3)

domain assumption The Mosaic architecture's 1-turn routing with shared paths correctly models the hardware's memory requirements (Section III, Fig. 2a-b).
All memory counts depend on this routing model; the paper does not verify the model against measured hardware.
ad hoc to paper The per-hop sparsity profile P(θ) is a sufficient statistic for routing memory: networks with identical P have near-identical memory footprints (Section III, Fig. 2d).
This is the core proxy assumption. The claimed minimal variance is not quantitatively demonstrated in the figure or text.
domain assumption The SHD dataset and LIF neuron model are used as in prior work, and the baseline accuracy from [17] is comparable under the paper's training setup (Section IV).
The comparison assumes that differences in network size and training procedure between the paper and [17] do not affect the reported trade-off.

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Cite this review

Pith. "Pith review of Hardware architecture and routing-aware training for optimal memory usage: a case study." pith.science (2026). https://pith.science/paper/AVXW6DDH

@misc{pith2026241201575,
  author       = {Pith},
  title        = {Pith review of: Hardware architecture and routing-aware training for optimal memory usage: a case study},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/AVXW6DDH}},
  note         = {Machine review of arXiv:2412.01575}
}

read the original abstract

Efficient deployment of neural networks on resource-constrained hardware demands optimal use of on-chip memory. In event-based processors, this is particularly critical for routing architectures, where substantial memory is dedicated to managing network connectivity. While prior work has focused on optimizing event routing during hardware design, optimizing memory utilization for routing during network training remains underexplored. Key challenges include: (i) integrating routing into the loss function, which often introduces non-differentiability, and (ii) computational expense in evaluating network mappability to hardware. We propose a hardware-algorithm co-design approach to train routing-aware neural networks. To address challenge (i), we extend the DeepR training algorithm, leveraging dynamic pruning and random re-assignment to optimize memory use. For challenge (ii), we introduce a proxy-based approximation of the mapping function to incorporate placement and routing constraints efficiently. We demonstrate our approach by optimizing a network for the Spiking Heidelberg Digits (SHD) dataset using a small-world connectivity-based hardware architecture as a case study. The resulting network, trained with our routing-aware methodology, is fully mappable to the hardware, achieving 5% more accuracy using the same number of parameters, and iso-accuracy with 10x less memory usage, compared to non-routing-aware training methods. This work highlights the critical role of co-optimizing algorithms and hardware to enable efficient and scalable solutions for constrained environments.

Figures

Figures reproduced from arXiv: 2412.01575 by the authors.

**Figure 2.** Routing information on the Mosaic architecture. a) We use the 1-turn algorithm for routing spikes, where the routing path from the source to destination [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** Test accuracy of the routing-aware training on the SHD dataset. a) [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

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Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.

[1] [10]

Mosaic: in-memory com- puting and routing for small-world spike-based neuromorphic systems

Thomas Dalgaty, Filippo Moro, Yi ˘git Demira˘g, Alessio De Pra, Giacomo Indiveri, Elisa Vianello, and Melika Payvand. Mosaic: in-memory com- puting and routing for small-world spike-based neuromorphic systems. Nature Communications, 15(1):142, 2024

work page 2024

[2] [1]

Loihi: A neuromorphic many-core processor with on-chip learning

Mike Davies, Narayan Srinivasa, Tsung-Han Lin, Gautham Chinya, Yongqiang Cao, Sri Harsha Choday, Georgios Dimou, Prasad Joshi, Nabil Imam, Shweta Jain, et al. Loihi: A neuromorphic many-core processor with on-chip learning. IEEE Micro, 38(1):82–99, 2018

work page 2018

[3] [2]

Schemmel, D

J. Schemmel, D. Bruderle, A. Grubl, M. Hock, K. Meier, and S. Millner. A wafer-scale neuromorphic hardware system for large-scale neural modeling. In Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on , pages 1947–1950. IEEE, 2010

work page 2010

[4] [3]

Spiking neural network integrated circuits: A review of trends and future directions

Arindam Basu, Lei Deng, Charlotte Frenkel, and Xueyong Zhang. Spiking neural network integrated circuits: A review of trends and future directions. In 2022 IEEE Custom Integrated Circuits Conference (CICC), pages 1–8. IEEE, 2022

work page 2022

[5] [4]

A scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors (dynaps)

Saber Moradi, Ning Qiao, Fabio Stefanini, and Giacomo Indiveri. A scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors (dynaps). IEEE transactions on biomedical circuits and systems , 12(1):106–122, 2017

work page 2017

[6] [5]

Spinnaker: A 1-w 18-core system-on-chip for massively- parallel neural network simulation

Eustace Painkras, Luis A Plana, Jim Garside, Steve Temple, Francesco Galluppi, Cameron Patterson, David R Lester, Andrew D Brown, and Steve B Furber. Spinnaker: A 1-w 18-core system-on-chip for massively- parallel neural network simulation. IEEE Journal of Solid-State Circuits, 48(8):1943–1953, 2013

work page 1943

[7] [6]

A million spiking-neuron integrated circuit with a scalable communication network and interface

Paul A Merolla, John V Arthur, Rodrigo Alvarez-Icaza, Andrew S Cas- sidy, Jun Sawada, Filipp Akopyan, Bryan L Jackson, Nabil Imam, Chen Guo, Yutaka Nakamura, et al. A million spiking-neuron integrated circuit with a scalable communication network and interface. 345(6197):668– 673, 2014

work page 2014

[8] [7]

Neu- rogrid: A mixed-analog-digital multichip system for large-scale neural simulations

Ben Varkey Benjamin, Peiran Gao, Emmett McQuinn, Swadesh Choud- hary, Anand R Chandrasekaran, Jean-Marie Bussat, Rodrigo Alvarez- Icaza, John V Arthur, Paul A Merolla, and Kwabena Boahen. Neu- rogrid: A mixed-analog-digital multichip system for large-scale neural simulations. Proceedings of the IEEE , 102(5):699–716, 2014

work page 2014