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REVIEW 4 major objections 5 minor 31 references

Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning

T0 review · 4 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read An RL agent augmented by a pre-trained relational graph network can floorplan industrial analog circuits faster and with less area than established metaheuristics and, in many cases, than manual engineers.

desk verdict Solid RL/GNN analog floorplanner with real industrial tests, but the abstract's headline area and time reductions cherry-pick the layouts that improved. read the letter →

arxiv 2411.15212 v1 pith:AXP2BS3H submitted 2024-11-20 cs.LG cs.AIcs.SYeess.SY

Davide Basso , Luca Bortolussi , Mirjana Videnovic-Misic , Husni Habal This is my paper · ORCID
classification cs.LGcs.AIcs.SYeess.SY
keywords analogICfloorplanningreinforcementlearningrelationalgraphconvolutionalnetworksphysicaldesigntransferprocedurallayoutgenerationhalf-perimeterwirelength
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to show that analog IC floorplanning, normally a manual, expert-driven step with many layout-dependent constraints, can be automated by an RL agent that reads circuit structure through a pre-trained relational graph convolutional network. The authors claim that pre-training the graph encoder on rewards from metaheuristic floorplans gives the agent transferable knowledge, so one policy can place blocks for several different analog circuits, including ones never seen in training. If true, this matters because analog layout is a bottleneck in chip design: the paper reports a 67.3% reduction in overall layout time and an 8.3% mean area reduction against manual layout on industrial circuits.

What carries the argument

The load-bearing object is the pre-trained R-GCN encoder: a relational graph convolutional network that consumes a heterogeneous graph of the circuit, where nodes are functional blocks or devices with features like area and a one-hot functional-type code, and edges are connectivity, alignment or symmetry relations. It is trained (after removing its fully-connected heads) on 21,600 floorplans produced by SA, GA, and PSO to predict their reward; the resulting embeddings are then fed to the RL agent alongside CNN-encoded masks (current grid, proxy wirelength increase, empty-space increase, and shape-specific placement masks). The paper's contribution is the claim that this reward-aligned graph representation is what lets the same RL policy transfer across distinct circuit topologies and constraints.

What would settle it

Take a circuit whose functional blocks (or their combinations) do not appear in the R-GCN pre-training set, run the zero-shot agent on it, and compare against a version of the same agent whose R-GCN encoder was randomly initialized instead of pre-trained; if the pre-trained encoder does not improve reward, area, or HPWL, or if the zero-shot floorplan violates symmetry or overlap constraints, the central transfer claim is unsupported.

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Extended reading notes

Core claim

The central claim, in the authors' own terms, is that a hybrid R-GCN and RL system produces better analog floorplans than established metaheuristics and prior RL methods. The R-GCN is pre-trained to predict a placement reward for a circuit graph; its frozen encoder then supplies node and graph embeddings to a PPO agent that places functional blocks on a 32x32 grid, using action masks to enforce symmetry, alignment and non-overlap. With hybrid curriculum training on five circuits, the agent is claimed to generalize zero-shot to three unseen circuits, and to beat SA, GA, PSO and earlier RL baselines on reward, HPWL, dead space or runtime after a short fine-tuning. Integrated with the ANAGEN procedural generator and OARSMT global routing, the method reportedly yields complete DRC/LVS-clean layouts of the same quality as manual design in hours instead of days.

Load-bearing premise

The whole transfer story rests on the assumption that the R-GCN encoder, pre-trained on floorplans generated by metaheuristics for a specific set of analog circuit families, learns a representation of circuit structure that transfers to arbitrary new circuits; if the training set or the one-hot functional encoding misses what matters for a novel circuit, the zero-shot and few-shot gains disappear.

Editorial extensions

If this is right

  • One policy, once trained on a few circuits, can be re-used across an analog design library; per-circuit optimization time drops from hours of metaheuristic search to seconds of inference.
  • Because the agent outputs routing-ready floorplans without congestion estimation, the downstream global router can be simpler and the whole layout pipeline shorter.
  • The method's action masking makes constraint satisfaction (symmetry, alignment, non-overlap) a property of the policy, reducing the need for post-generation checking and repair.
  • In combination with ANAGEN, an engineer can go from netlist to DRC/LVS-clean layout of a simple block in a fraction of the manual time, making early design iterations cheaper.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The architecture decouples the expensive part (pre-training the graph encoder on 21,600 metaheuristic floorplans) from the per-circuit cost (seconds of RL inference), so the economics improve as the encoder is reused across more designs, but only if the pre-training distribution stays representative.
  • Since the R-GCN is trained on reward labels from metaheuristics, the same scaffolding could be pointed at different objectives such as routability, current density, or thermal gradients by swapping the reward oracle, yielding transferable encoders for other physical-design decisions.
  • A cheaper curriculum or a smaller pre-training set might give the same transfer, but the paper does not ablate that; benchmarking the sample complexity of the encoder pre-training would tell an industrial team where to spend compute.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 5 minor

Summary. The paper proposes a floorplanning method for analog ICs that combines a relational graph convolutional network (R-GCN) encoder with a reinforcement learning (RL) agent. The R-GCN is pre-trained to predict floorplan rewards and then used as a graph-embedding module; a CNN processes grid masks; a masked PPO agent selects shapes and grid positions for circuit blocks. The method is evaluated on six industrial circuits against SA, GA, PSO, and two prior RL-based methods, with zero-shot and few-shot fine-tuning. The authors also integrate the floorplanner into the ANAGEN procedural layout generator and compare three completed layouts against manual layouts, reporting a 67.3% layout-time reduction and an 8.3% mean area reduction.

Significance. If substantiated, the work would demonstrate a practical RL-based analog floorplanning system with transfer across circuit topologies, tested on industrial designs. The paper includes a substantial training setup (21,600 pre-training floorplans, 12.7 hours of RL training) and a clear MDP formulation with action masking. However, the central quantitative claims in the abstract are not reproducible from the reported tables, the baseline comparison may favor the proposed method through asymmetric congestion-aware spacing, and the contribution of the R-GCN is not isolated via ablation. These issues prevent the results from being taken at face value.

major comments (4)
  1. [V-C (Table II) and Abstract] The abstract claims an 8.3% mean area reduction compared to manual layout, but Table II reports area changes of -14.1%, +52.1%, and -2.43% for OTA, Bias-1, and Driver, respectively. The mean across all three circuits is +11.9%, i.e., an area increase, not a reduction. The -8.3% value corresponds to averaging only OTA and Driver, excluding Bias-1; the exclusion is mentioned in Section V-C but not in the abstract. Similarly, the claimed 67.3% overall layout-time reduction is not derivable from Table II under any clearly stated aggregation rule: including the manual improvement time for the Driver circuit yields an automated total that exceeds the manual layout time. The authors must state the exact aggregation and the Bias-1 caveat in the abstract, or revise the claims to match the data.
  2. [V-B (Table I)] The statement "For a fair comparison, congestion-aware device spacing is applied to all other approaches" creates an asymmetry: the proposed method's floorplans are measured without this spacing, while all baselines have it. Since Table I reports floorplan metrics (dead space, HPWL) before routing, this inflates the baselines' dead space and biases the comparison in favor of the proposed method. To support the fairness claim, the authors should either apply the same congestion-aware spacing to the proposed method in Table I, or demonstrate that the proposed floorplans are routable without extra spacing for all six evaluated circuits, not only for the three in Table II.
  3. [IV-C, IV-D] The paper attributes the generalization ability of the approach to the R-GCN encoder, but no ablation is provided in which the RL agent is trained without the R-GCN (e.g., using only the CNN masks and grid features). The comparison with the RL method from [13] is not an adequate control because that prior work uses a different sequence-pair representation and does not share the same architecture. Without such an ablation, the specific contribution of the R-GCN to the reported rewards and transferability is not established. Additionally, no prediction accuracy of the pre-trained R-GCN reward model is reported, so it is unclear whether the encoder actually learns meaningful circuit features.
  4. [V-B (Table I)] The text claims the method "surpasses established floorplanning techniques in terms of speed, area and half-perimeter wire length" for the six circuits, but Table I does not report area; it reports dead space, HPWL, and reward. The reward is the training objective of the proposed agent (Eq. 5), so comparing rewards alone is not an independent evaluation. Area is reported only for the three circuits in Table II, which cannot support a six-circuit area claim. Please report area for all evaluated circuits in Table I or qualify the claim to dead space and HPWL.
minor comments (5)
  1. [Abstract and V-C] The abstract states "Applied to 6 industrial circuits..." but the 67.3% time and 8.3% area reductions appear to refer only to the three circuits in Table II. Clarify that the manual-layout comparison is on a subset of three circuits.
  2. [IV-C] The composition of the 21,600 pre-training floorplans is not described (e.g., number of circuits per type, distribution of constrained vs. unconstrained cases, and how rewards were computed). This information is needed to assess the source of the R-GCN's transferability.
  3. [V-B (Table I)] The terms "1-shot", "100-shot", and "1000-shot" are not defined; specify whether they denote the number of fine-tuning episodes, gradient steps, or something else.
  4. [IV-D5] The hybrid curriculum learning schedule is described only by the probabilities pcircuit and pconstraint; the order in which circuits of increasing complexity are introduced and the criterion for "growing complexity" should be stated.
  5. [V-C (Table II)] The caption and text should note that the manual Bias layout was not created with ANAGEN, as stated in the body, so that the area comparison for Bias-1 is not interpreted as a like-for-like comparison.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: the R-GCN encoder and RL policy are trained on distinct objectives, and the transfer claims are tested on held-out circuits.

full rationale

The paper's derivation chain is not circular. The R-GCN is pre-trained to predict reward values for floorplans produced by SA/GA/PSO metaheuristics (Section IV-C), but this supervised model is used only as an encoder; the RL agent is trained on true environment rewards defined in Eqs. (4) and (5), not on the R-GCN's reward predictions. The RL policy therefore optimizes the actual metrics (dead space, HPWL, aspect ratio) that are later reported, which is standard objective alignment rather than a fitted-input-called-prediction pattern. The transferability claim is supported by zero-shot and few-shot evaluations on circuits not used during RL training (Table I, grey rows), so the central generalization result is not forced by construction. The paper does rely on the authors' prior work [13] for the base floorplanning pipeline, block-shape generation, and baselines, but that prior work supplies an external comparison and the present contribution, the R-GCN+RL combination with masking and transfer learning, has independent algorithmic content. The abstract's 8.3% area reduction figure appears inconsistent with Table II, where including Bias-1 gives a mean area increase, but numerical inconsistency is a correctness/validity concern, not a circularity of derivation. No step reduces to its own input by definition or by author-imposed uniqueness, and no load-bearing claim is justified solely by a self-citation. Accordingly, the circularity score is 0.

Assumptions & free parameters 5 free parameters · 5 assumptions · 0 invented entities

The method introduces no new physical entities. It does depend on several hand-chosen parameters (Rmax, reward weights, grid size, curriculum probabilities) and on domain assumptions about the sufficiency of graph encodings and proxy metrics. The most consequential free parameter is HPWLmin, which is computed per circuit via metaheuristics and enters the reward definition.

free parameters (5)
  • Rmax = 11
    Empirically derived maximum aspect ratio used to set grid dimensions W = H = sqrt(sum(A_i)/Rmax) (Section IV-D1). It controls grid scale and discretization; a wrong value would distort placements.
  • Reward weights alpha, beta, gamma = 1, 5, 5
    Set empirically 'through extensive experimentation' (Section IV-D4) to balance area, HPWL, and aspect ratio error in the final reward. These choices define what 'optimal' means.
  • HPWLmin per circuit = not disclosed per circuit
    Minimum HPWL estimated through a metaheuristic-based simulation and used to normalize HPWL in the end-of-episode reward (Section IV-D4). Each new circuit would need a metaheuristic run to compute this value.
  • HCL probabilities pcircuit, pconstraint = 0.5, 0.3
    Sampling probabilities for new circuits and constraints during curriculum training (Section V-A). These affect generalization but are hyperparameters.
  • Grid resolution = 32 x 32
    Discretization of the layout canvas chosen to balance action space size and accuracy (Section IV-D1). Not fitted, but a design choice that affects all results.
assumptions (5)
  • domain assumption A circuit can be represented as a graph of functional blocks with connectivity, alignment, and symmetry edges, and node features including a 28-dimensional one-hot encoding of block type.
    Section IV-C: this representation is the input to the R-GCN; if it misses important constraints, the embeddings cannot guide the RL agent.
  • domain assumption HPWL and dead space are sufficient proxies for routing quality and area during optimization.
    The reward is a weighted sum of area, HPWL, and aspect ratio error (Section IV-D4); no parasitic or DRC information enters the reward.
  • domain assumption The 21,600 metaheuristic-optimized floorplans used to pre-train the R-GCN are representative of good floorplans across the target circuit families.
    Section IV-C: the R-GCN learns reward predictions from these labels; biased or non-representative training data would produce misleading embeddings.
  • domain assumption An RL agent trained on 3 OTAs and 2 bias circuits (5 circuits total) with hybrid curriculum learning transfers to unseen circuit topologies such as RS latch, driver, and larger bias.
    Section IV-D5 and V-B: this transfer is the central generalization claim, but the training set is small and a subset of the test set.
  • ad hoc to paper Adding congestion-aware device spacing only to baseline methods produces a fair comparison.
    Section V-B: the baselines are penalized with extra spacing while the proposed method is not, which advantages the proposed method in dead space and HPWL metrics.

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Cite this review

Pith. "Pith review of Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning." pith.science (2026). https://pith.science/paper/AXP2BS3H

@misc{pith2026241115212,
  author       = {Pith},
  title        = {Pith review of: Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/AXP2BS3H}},
  note         = {Machine review of arXiv:2411.15212}
}
abstract

Analog integrated circuit (IC) floorplanning is typically a manual process with the placement of components (devices and modules) planned by a layout engineer. This process is further complicated by the interdependence of floorplanning and routing steps, numerous electric and layout-dependent constraints, as well as the high level of customization expected in analog design. This paper presents a novel automatic floorplanning algorithm based on reinforcement learning. It is augmented by a relational graph convolutional neural network model for encoding circuit features and positional constraints. The combination of these two machine learning methods enables knowledge transfer across different circuit designs with distinct topologies and constraints, increasing the \emph{generalization ability} of the solution. Applied to $6$ industrial circuits, our approach surpassed established floorplanning techniques in terms of speed, area and half-perimeter wire length. When integrated into a \emph{procedural generator} for layout completion, overall layout time was reduced by $67.3\%$ with a $8.3\%$ mean area reduction compared to manual layout.

Figures

Figures reproduced from arXiv: 2411.15212 by the authors.

Figure 1
Figure 1. Overview of the automatic layout pipeline. [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 3
Figure 3. R-GCN architecture for circuit reward prediction. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Overview of the RL model, enriched with CNN based feature extractor and policy network. [PITH_FULL_IMAGE:figures/full_fig_p004_4.png] view at source ↗
Figures from the paper (3 more)
Figure 5
Figure 5. Figure 5: Dead space (left) and wire (right) masks. Darker areas highlight higher [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]
Figure 6
Figure 6. Figure 6: Episode Reward Mean and Approximate Kullback-Leibler divergence [PITH_FULL_IMAGE:figures/full_fig_p005_6.png]
Figure 7
Figure 7. Figure 7: (a) RL-generated placement and OARSMT global routing, (b) post [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]

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