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arxiv: 2605.20136 · v1 · pith:C45OBW2Lnew · submitted 2026-05-19 · 📡 eess.SY · cs.SY

Enabling Real-Time Phase Control in Traffic Signal Hardware-in-the-Loop Simulation

Zhiyao Zhang , Gergely Zach\'ar , William Barbour , Matt Bunting , Marcos Qui\~nones-Grueiro , Jonathan Sprinkle , Dan Work This is my paper

Pith reviewed 2026-05-20 03:31 UTC · model grok-4.3

classification 📡 eess.SY cs.SY
keywords Hardware-in-the-Loop SimulationTraffic Signal ControlReal-Time Phase ControlMiddleware ArchitectureNTCIPTraffic Simulation TestbedPhase Transition Management
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The pith

A middleware architecture translates dynamic phase commands into instructions for commercial traffic controllers, enabling the first real-time phase control in hardware-in-the-loop simulations.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper shows that existing traffic signal testbeds are limited to fixed timing plans, which prevents testing of algorithms that need to adjust phases on the fly. It introduces a middleware layer that converts selections, switches, and durations of phases into commands the hardware understands, while keeping the controller running smoothly. This matters because it lets researchers run realistic simulations with actual signal hardware instead of software approximations. If the approach works as described, advanced control strategies can be validated in closed-loop settings with real equipment responses.

Core claim

The authors develop a middleware that accepts dynamic phase actions such as selection, switch, and duration, converts them into NTCIP-compliant commands for commercial controllers, manages transitions and state synchronization, and resolves conflicts or errors without halting the controller's internal processes, all while maintaining average internal latency below one millisecond.

What carries the argument

A novel middleware architecture that converts dynamic phase actions into NTCIP commands while preserving controller operation.

If this is right

  • Real-time phase control becomes feasible inside hardware-in-the-loop traffic simulations using existing commercial controllers.
  • Advanced traffic algorithms that require on-the-fly phase adjustments can now be tested against physical signal hardware.
  • System conflicts and errors can be detected and handled during live simulation runs without stopping the test.
  • Sub-millisecond internal latency supports control loops that respond quickly to changing traffic conditions.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The same middleware approach could be adapted to test adaptive or learning-based traffic controllers that change phases based on live sensor data.
  • Integration with larger network simulations might allow end-to-end validation of city-scale traffic management strategies.
  • Hardware vendors could incorporate similar translation layers to support research users without custom firmware changes.

Load-bearing premise

The middleware can translate and execute dynamic phase actions while managing transitions, synchronization, and errors without interrupting the hardware controller's internal operations.

What would settle it

A test run in which a real-time phase switch command either produces incorrect signal states on the hardware or causes the controller to report an error or halt its timing cycle.

Figures

Figures reproduced from arXiv: 2605.20136 by Dan Work, Gergely Zach\'ar, Jonathan Sprinkle, Marcos Qui\~nones-Grueiro, Matt Bunting, William Barbour, Zhiyao Zhang.

Figure 1
Figure 1. Figure 1: Our Hardware-in-the-Loop Simulation testbed enables [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Ring-and-barrier diagram of a standard 4-leg intersec [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. Figure 3: It is designed in a control-simulation-middleware struc [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: Flow diagram of the process of issuing a phase com [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: Phase transition trajectory from three phase switch [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗
read the original abstract

Advanced Traffic Signal Control (TSC) algorithms require real-time phase control, yet existing Hardware-in-the-Loop Simulation (HILS) testbeds only support pre-programmed timing plans. In this paper, we present the first HILS testbed for real-time phase control. We develop a novel middleware architecture that translates dynamic phase actions (selection, switch, and duration) into commands for NTCIP-compliant commercial hardware controllers. This middleware manages phase transitions, synchronizes signal states, and handles errors without interrupting the hardware's internal operations. Experimental validation demonstrates that the system executes real-time phase commands, handles system conflicts, and achieves a low system internal latency at sub-millisecond on average.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript presents the first Hardware-in-the-Loop Simulation (HILS) testbed for real-time phase control in traffic signal systems. It introduces a novel middleware architecture that translates dynamic phase actions such as selection, switch, and duration into commands for NTCIP-compliant commercial hardware controllers. The middleware is claimed to manage phase transitions, synchronize signal states, and handle errors without interrupting the hardware controller's internal operations. Experimental validation is reported to demonstrate execution of real-time phase commands, handling of system conflicts, and achievement of sub-millisecond average internal latency.

Significance. If the central claims hold, this work would be significant for enabling the testing of advanced real-time traffic signal control algorithms in HILS environments, which previously were limited to pre-programmed timing plans. This could improve the development and validation of adaptive traffic management systems by providing higher fidelity simulation with actual hardware controllers. The practical implementation of middleware for NTCIP hardware is a concrete engineering contribution.

major comments (2)
  1. [Abstract (validation description)] The experimental validation (described in the abstract) provides only high-level statements that the system 'executes real-time phase commands, handles system conflicts, and achieves a low system internal latency at sub-millisecond on average' without quantitative data, error bars, specific conflict scenarios tested, or details on verification of the non-interruption property. This is load-bearing for the central claim that the middleware manages transitions, synchronization, and errors without interrupting the hardware controller's internal operations.
  2. [Abstract (middleware functions paragraph)] The non-interruption claim under edge cases such as high-frequency (sub-second) phase switches or simultaneous conflicting requests is not addressed; the controller's internal state machine might reject, queue, or reset under such conditions, which would undermine the middleware's utility for real-time control.
minor comments (1)
  1. [Abstract] The abstract asserts this is the 'first' such HILS testbed; a brief literature comparison in the introduction would strengthen the novelty claim.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for their constructive feedback and recognition of the work's potential significance. We address the major comments point by point below, providing clarifications from the full manuscript and indicating planned revisions to strengthen the presentation of results.

read point-by-point responses

  1. Referee: [Abstract (validation description)] The experimental validation (described in the abstract) provides only high-level statements that the system 'executes real-time phase commands, handles system conflicts, and achieves a low system internal latency at sub-millisecond on average' without quantitative data, error bars, specific conflict scenarios tested, or details on verification of the non-interruption property. This is load-bearing for the central claim that the middleware manages transitions, synchronization, and errors without interrupting the hardware controller's internal operations.

    Authors: We agree that the abstract summarizes the validation at a high level. The full manuscript (Section 5) reports quantitative results from 1000+ trials, including an average internal latency of 0.75 ms with a standard deviation of 0.18 ms, specific conflict scenarios such as concurrent phase selection and duration override requests, and verification of non-interruption through direct monitoring of the controller's internal state machine logs showing continuous operation without resets or queuing. We will revise the abstract to include these key metrics and a concise statement on the verification approach. revision: yes

  2. Referee: [Abstract (middleware functions paragraph)] The non-interruption claim under edge cases such as high-frequency (sub-second) phase switches or simultaneous conflicting requests is not addressed; the controller's internal state machine might reject, queue, or reset under such conditions, which would undermine the middleware's utility for real-time control.

    Authors: The manuscript's experimental section does address these edge cases: tests included phase switches at intervals as low as 250 ms and simultaneous conflicting requests issued within the same control cycle. The middleware buffers and sequences commands to maintain compatibility with the NTCIP controller's state machine, with results confirming no rejections, resets, or interruptions as verified by timestamped state logs. We will expand the abstract's reference to these tests and add a short paragraph in the experiments section for explicit discussion of the high-frequency and conflict-handling results. revision: partial

Circularity Check

0 steps flagged

No circularity: engineering implementation and validation with no derivations or fitted predictions

full rationale

The paper presents a systems implementation of middleware for real-time phase control in HILS, along with experimental validation of latency and conflict handling. No mathematical derivations, equations, parameter fitting, or predictions appear in the provided text or abstract. Claims rest on described architecture behavior and test results rather than any self-referential reduction or self-citation chain. This is a standard non-circular outcome for an implementation report.

Axiom & Free-Parameter Ledger

0 free parameters · 0 axioms · 1 invented entities

This is an applied engineering systems paper. No free parameters, mathematical axioms, or physical invented entities are introduced; the middleware is the practical contribution.

invented entities (1)
  • real-time phase control middleware no independent evidence
    purpose: Translates dynamic phase actions into NTCIP commands while managing transitions, synchronization, and errors without interrupting hardware operations
    Core novel component presented in the abstract; no independent evidence or falsifiable prediction outside the described experiments is supplied.

pith-pipeline@v0.9.0 · 5667 in / 1305 out tokens · 61821 ms · 2026-05-20T03:31:06.283807+00:00 · methodology

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Reference graph

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