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A framework of partial error correction for intermediate-scale quantum computers
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As quantum computing hardware steadily increases in qubit count and quality, one important question is how to allocate these resources to mitigate the effects of hardware noise. In a transitional era between noisy small-scale and fully fault-tolerant systems, we envisage a scenario in which we are only able to error-correct a fraction of the qubits required to perform an interesting computation. In this work, we develop concrete constructions of logical operations on a joint system of a collection of noisy and a collection of error-corrected logical qubits. Within this setting and under Pauli noise assumptions, we provide analytic evidence that brick-layered circuits display on average slower concentration to the ``useless'' uniform distribution with increasing circuit depth compared to fully noisy circuits. We corroborate these findings by numerical demonstration of slower decoherence with an increasing fraction of error-corrected qubits under depolarizing noise acting at the circuit level. We find that this advantage only manifests when the number of error-corrected qubits passes a specified threshold which depends on the number of couplings between error-corrected and noisy registers.
Forward citations
Cited by 2 Pith papers
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Hybrid physical/logical zero-noise extrapolation with limited logical executions
Mixing a single low-noise logical circuit with several physical folded circuits in ZNE cuts the runtime needed for fixed estimator variance by orders of magnitude when the logical error-suppression factor γ≲0.1.
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Quantum Compiler Design for Qubit Mapping and Routing: A Cross-Architectural Survey of Superconducting, Trapped-Ion, and Neutral Atom Systems
A cross-architectural survey that categorizes qubit mapping and routing compilers for superconducting, trapped-ion, and neutral atom quantum hardware.
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