Paper Citation Record · LEDGER

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization

As of 18 August 2026, this Paper Citation Record lists 31 of 31 outbound references and 9 inbound Pith citation observations for arXiv:2507.19570.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2507.19570 v1

Coverage vector

measured 31 of 31 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-06T14:21:43.888518Z

measured 40 of 40 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-17T06:30:58.91139+00:00

measured 9 of 9 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-07T00:59:48.249015Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-04T15:09:55.503862Z

Reference resolution

31 of 31 outbound references displayed

verified exact1
verified fuzzy20
unresolved10
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation cb9b0820-4eea-48da-956b-43b4d3c80e6e · outbound

This paper cites Flowtune: End-to-end automatic logic optimization exploration via domain-specific multi-armed bandit,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Flowtune: End-to-end automatic logic optimization exploration via domain-specific multi-armed bandit,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.267543Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation f749b127-b675-49f7-a3f1-85268b8fde32 · outbound

This paper cites Optimization of physically-aware synthesis for digital implementation flow,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Optimization of physically-aware synthesis for digital implementation flow,

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.258849Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 89e58cfa-518f-48d7-9dbe-874b8a1aca56 · outbound

This paper cites Rtlcoder: Fully open-source and efficient llm-assisted rtl code generation technique,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Rtlcoder: Fully open-source and efficient llm-assisted rtl code generation technique,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.251213Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 091964fe-1193-43fb-bf69-36fe22dbbf82 · outbound

This paper cites Chipgpt: How far are we from natural language hardware design,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Chipgpt: How far are we from natural language hardware design,

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-06T14:21:43.828139Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3caae3b0-ccc8-403d-b988-5ef4e0ccfdc4 · outbound

This paper cites Chip-chat: Challenges and opportunities in conversational hardware design,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Chip-chat: Challenges and opportunities in conversational hardware design,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.243436Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 06f9e474-3a5b-4ceb-af77-42e2b2743f7c · outbound

This paper cites LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-06T14:21:43.832956Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 7443940a-dd5f-489d-a407-cb2a41f0e2d6 · outbound

This paper cites Verilogeval: Evaluating large language models for verilog code generation,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Verilogeval: Evaluating large language models for verilog code generation,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.235650Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 4acb3727-4321-4a14-9ca3-ee836cc68ea5 · outbound

This paper cites VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-06T14:21:43.837734Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3337552a-ed6c-4cca-b8d6-7701cf1a9304 · outbound

This paper cites Rtlfixer: Automatically fixing RTL syntax errors with large language model,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Rtlfixer: Automatically fixing RTL syntax errors with large language model,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.227517Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 02ae5b9a-8a76-4464-9b3e-8d666e5a89ae · outbound

This paper cites Rtlrewriter: Methodologies for large models aided rtl code optimization,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Rtlrewriter: Methodologies for large models aided rtl code optimization,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.218477Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 9ae3fce4-ca39-4acc-a1be-c425c97e4f9d · outbound

This paper cites Symrtlo: Enhancing rtl code optimization with llms and neuron-inspired symbolic reasoning,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Symrtlo: Enhancing rtl code optimization with llms and neuron-inspired symbolic reasoning,

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-06T14:21:43.844526Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 080b4bb0-8274-4c8b-a57b-151e6778a486 · outbound

This paper cites ChipNeMo: Domain-Adapted LLMs for Chip Design.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 12

Resolution: unresolved; no resolver link, observed 2026-08-06T14:21:43.846626Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c287344c-f3e2-4546-b6b2-8897b5e37a49 · outbound

This paper cites ChatEDA: A Large Language Model Powered Autonomous Agent for EDA.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization ChatEDA: A Large Language Model Powered Autonomous Agent for EDA

Reference 13

Resolution: unresolved; no resolver link, observed 2026-08-06T14:21:43.848990Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 7de6b9ba-cfba-4711-b819-9d10f81bc38e · outbound

This paper cites Chip-chat: Challenges and opportunities in conversational hardware design,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Chip-chat: Challenges and opportunities in conversational hardware design,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.210794Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 27baf4c5-612f-4791-80e7-c69afe934ff3 · outbound

This paper cites Openroad: Toward a self-driving, open-source digital layout implementation tool chain,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Openroad: Toward a self-driving, open-source digital layout implementation tool chain,

Reference 15

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.202256Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 2979e61b-9270-4ec8-8ab2-4c694cde46bd · outbound

This paper cites Building openlane: A 130nm openroad-based tapeout- proven flow : Invited paper,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Building openlane: A 130nm openroad-based tapeout- proven flow : Invited paper,

Reference 16

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.193846Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 6df5812f-0231-46ed-8f7c-b4163ae25ff7 · outbound

This paper cites Optimization of physically-aware synthesis for digital implementation flow,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Optimization of physically-aware synthesis for digital implementation flow,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.185996Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 6612f801-f821-40c0-b637-1ef868a130ad · outbound

This paper cites Optimization of physically-aware synthesis for digital implemen- tation flow,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Optimization of physically-aware synthesis for digital implemen- tation flow,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.177424Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation ad4f67c7-4b67-4640-9f61-9a75084f34d4 · outbound

This paper cites Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement

Reference 19

Resolution: verified exact; local_arxiv, observed 2026-08-06T14:21:43.931880Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 23bec60a-e0aa-42b7-a3dd-e996ade77034 · outbound

This paper cites High-level synthesis design space explo- ration: Past, present, and future,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization High-level synthesis design space explo- ration: Past, present, and future,

Reference 20

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.169368Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 88496a16-ca16-49e2-9b6b-347049949a10 · outbound

This paper cites Efficient system design space exploration using machine learning techniques,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Efficient system design space exploration using machine learning techniques,

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.161040Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation b6196884-e4d8-4e93-a911-77455063bbda · outbound

This paper cites Design-space exploration - an overview,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Design-space exploration - an overview,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.151765Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation e9a1be99-22dd-43cf-afa2-aa050777e1c2 · outbound

This paper cites A survey of research in large language models for electronic design automation,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization A survey of research in large language models for electronic design automation,

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-06T14:21:43.871205Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6cfb3748-2011-4a42-b236-8e9169255e2e · outbound

This paper cites Verigen: A large language model for verilog code generation,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Verigen: A large language model for verilog code generation,

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.143145Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation c2a706e9-7c6e-4233-98c2-de7ca502a432 · outbound

This paper cites Benchmarking Large Language Models for Automated Verilog RTL Code Generation.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Benchmarking Large Language Models for Automated Verilog RTL Code Generation

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-06T14:21:43.875275Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 7c48bf39-da7c-4401-ad28-206de2e409dc · outbound

This paper cites Model context protocol specification,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Model context protocol specification,

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.133390Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation d2069ba2-ec2a-4e74-a4b1-9595cf8d68b8 · outbound

This paper cites Model Context Protocol (MCP): Landscape, Security Threats, and Future Research Directions.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Model Context Protocol (MCP): Landscape, Security Threats, and Future Research Directions

Reference 27

Resolution: unresolved; no resolver link, observed 2026-08-06T14:21:43.879784Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 861f4c3f-ffc7-4ef9-86e8-63d0b0241242 · outbound

This paper cites Yosys-a free verilog synthesis suite,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Yosys-a free verilog synthesis suite,

Reference 28

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.124610Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 3214cbd0-4e96-4b23-87bc-3d048b8f0462 · outbound

This paper cites ABC: An academic industrial-strength verification tool,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization ABC: An academic industrial-strength verification tool,

Reference 29

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.115738Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 69ce288e-d546-4b94-94b5-cc3be38a1849 · outbound

This paper cites an unresolved cited work.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization Unresolved cited work

Reference 30

Resolution: unresolved; raw_fallback, observed 2026-08-06T14:21:44.105655Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 41e8f84d-7752-42fe-b1d8-c11ef59214c4 · outbound

This paper cites OpenCores,.

MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization OpenCores,

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T14:21:44.097383Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Pith citing papers

Observation 9ddff8cd-0f7a-45b5-a33a-973f4d07f105 · inbound

Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing cites this paper.

Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization

Reference 17

Resolution: verified exact; arxiv_id, observed 2026-05-11T04:50:57.291415Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation d40befdd-ccce-48b5-bf31-bc6b5a92d88b · inbound

Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing cites this paper.

Reference 17

Resolution: verified exact; arxiv_id, observed 2026-05-25T06:55:26.247481Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 60edebd3-545a-4b96-a64d-4d4074c138cb · inbound

Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing cites this paper.

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-02T14:44:29.672890Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 548b4a74-1273-48e8-b142-5ed70d74bdb0 · inbound

CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research cites this paper.

CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization

Reference 108

Resolution: verified exact; arxiv_id, observed 2026-07-04T15:09:55.505705Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 28f3708b-7f9a-4a0d-bf67-42bd1a169e02 · inbound

CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research cites this paper.

Reference 109

Resolution: verified exact; arxiv_id, observed 2026-06-30T12:44:39.775143Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.

Observation 2ac37fee-1c04-4d7c-9278-3dc6b8224d4c · inbound

CHIA: An open-source framework for principled, agentic AI-driven hardware/software co-design research cites this paper.

Reference 104

Resolution: unresolved; no resolver link, observed 2026-08-02T10:03:40.496062Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 1c3b6424-e878-4c06-8570-6a7f61eca195 · inbound

PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation cites this paper.

PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-04T20:50:45.030511Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 514f6ee2-b575-406a-8af6-bdda9c860eed · inbound

PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation cites this paper.

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-07T00:13:00.325526Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 13f2a0b4-1bd0-4eaa-aba7-fbc84eb917ea · inbound

PICopilot: An LLM-based Agentic Framework for Assisting Photonic Integrated Circuit Design via Script Generation cites this paper.

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-07T00:59:48.249015Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.