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REVIEW 4 major objections 8 minor 39 references

PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies

T0 review · 4 major / 8 minor · reviewed 2026-08-09 · deepseek-v4-flash

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Pith's one-line read A placement-based interconnect generator cuts cache-coherency latency by up to 62% versus a 2D mesh.

desk verdict Solid, reproducible co-optimization tool for 2.5D chiplet interconnects, with real but not fatal evaluation caveats around trace-derived cost weights and baseline fairness. read the letter →

arxiv 2502.01449 v2 pith:CW5CI7HV submitted 2025-02-03 cs.AR

Patrick Iff , Benigna Bruggmann , Maciej Besta , Luca Benini , Torsten Hoefler This is my paper · ORCID
classification cs.AR
keywords 2.5Dintegrationchipletinter-chipletinterconnecttopologysynthesisplacementoptimizationcachecoherencylatencyreductionheterogeneous
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

PlaceIT is a design method for 2.5D stacked chips that treats where chiplets sit and how they are wired as one problem instead of two. For every candidate placement, it invents a new interconnect topology by linking chiplets that are physically close, which suits silicon bridges and passive interposers whose die-to-die links cannot run far. The paper claims this co-optimization lowers the latency of L1-to-L2 and L2-to-memory traffic, the dominant cache-coherency flows, by up to 28% and 62% against a 2D mesh baseline, and reduces average packet latency by up to 18% on application traces. If true, architects can build lower-latency cache-coherent 2.5D chips without changing the packaging technology.

What carries the argument

The mechanism that carries the argument is the placement-based topology inference step: for each placement, a graph is built whose vertices are PHYs, with internal edges inside relay-capable chiplets and candidate edges between PHYs of different chiplets that are close enough; a minimum spanning tree guarantees connectivity, and additional short edges are added to exploit unused PHYs. This step makes the topology a deterministic function of the placement, so the optimizer can explore placement space while implicitly exploring topology space. The cost function combines area with latency and throughput proxies for four traffic classes, weighted according to the observed mix of cache-coherency traffic, and is minimized by best-random, genetic, or simulated-annealing search.

What would settle it

Take one architecture from the paper, sample thousands of random placements, and compare each placement's cost-function score against its measured average packet latency under a held-out application trace; if the score does not predict the ordering of measured latencies, then the proxy that steers PlaceIT can mis-rank designs and the reported gains are specific to the simulated traces.

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Extended reading notes

Core claim

The central claim is that the interconnect topology of a 2.5D chip should be generated from the chiplet placement rather than chosen before placement. PlaceIT infers a placement-based topology by building a graph of PHY ports, connecting nearby chiplets within a maximum link length using a minimum spanning tree and then adding extra short links to use otherwise idle ports; latency and throughput proxies for compute-to-compute, compute-to-memory, compute-to-IO, and memory-to-IO traffic are fed back into a search over placements. The paper demonstrates that this joint optimization produces configurations with lower cost and lower simulated packet latency than a perimeter-memory 2D mesh for both homogeneous and heterogeneous chiplet shapes, with the largest gains on the compute-to-memory and memory-to-IO flows that dominate cache-coherency traffic.

Load-bearing premise

The cheap cost function used to steer the search, with weights drawn from one family of cache-coherency traces, correctly predicts which designs will have low latency under cycle-accurate simulation.

Editorial extensions

If this is right

  • Designers of 2.5D chips with passive interposers or silicon bridges can co-optimize placement and topology instead of fixing a mesh, because the method respects short link-length limits.
  • Cache-coherent systems can expect the largest latency gains on traffic between compute and memory and between memory and IO, not on compute-to-compute traffic.
  • Heterogeneously shaped chiplets with arbitrary PHY counts and positions can be handled by optimizing the order and rotations in which a placement algorithm packs them.
  • Because the cost function is user-defined, the same framework can target different traffic mixes, such as ML inference or graph analytics, rather than only cache coherency.
  • The open-source implementation allows other teams to reproduce the 2D-mesh comparisons and add new optimization algorithms or placement representations.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • If the cost proxy proves reliable beyond the trace family used in the paper, the same co-optimization loop could be applied to active interposers with package-level routing, where link-length constraints are weaker.
  • The topology inference could be reused as a generic construction for any degree-constrained, distance-limited network, such as optical or wireless die-to-die links with different maximum-length budgets.
  • A stronger test than the paper's baseline comparison would pit PlaceIT against a method that selects among several hand-designed topologies for the same placement; the gap would isolate the value of generating new topologies.
  • The cost weights are a tunable knob: shifting weight toward compute-to-compute traffic should close the observed latency gap on that flow, at the cost of memory traffic.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

4 major / 8 minor

Summary. The paper presents PlaceIT, a methodology for jointly optimizing chiplet placement and inter-chiplet interconnect (ICI) topology in 2.5D integrated systems. For each candidate placement, the method infers a placement-based ICI topology by connecting proximate chiplets, estimates latency and throughput using the RapidChiplet toolchain, and returns a weighted cost to an optimization algorithm (best random, genetic algorithm, or simulated annealing). The methodology supports both homogeneous and heterogeneous chiplet shapes. The authors evaluate PlaceIT on 32- and 64-core architectures against a 2D mesh baseline using BookSim2 cycle-accurate simulation with synthetic traffic and Netrace application traces, reporting latency reductions of up to 28% for synthetic L1-to-L2 traffic, 62% for L2-to-memory traffic, and up to 18% average packet latency reduction on traces. The implementation is released as open source.

Significance. If the reported results are robust, PlaceIT makes a valuable contribution: it is, to my knowledge, the first work to jointly co-optimize chiplet placement and ICI topology for heterogeneously shaped chiplets on passive interposers, silicon bridges, and organic substrates, where link lengths are severely limited. The open-source implementation, modular design, and use of an established cycle-accurate simulator are clear strengths, as is the explicit comparison against a standard 2D mesh baseline. However, the current evaluation has load-bearing issues—most notably the use of the same trace family for both cost-function weight tuning and evaluation, and a potentially unfair baseline configuration—that make the headline latency reductions conditional rather than established.

major comments (4)
  1. [§IV-B and §VII-A] The cost function weights are derived from the same Netrace v1.0 trace collection used in the evaluation. Section IV-B states that the weights (2 for C2M/M2I, 0.1 for C2C/C2I) were set by analyzing traffic mixes in Netrace traces, and Section VII-A evaluates the resulting topologies on traces from that same collection. This means the trace-level latency reductions are not an independent test of generality; they demonstrate tuning on the test distribution. To support the claimed average packet latency reductions, the authors should either hold out a separate set of traces for evaluation after tuning on a distinct set, or explicitly frame the results as workload-specific tuning and temper the general claim in the abstract.
  2. [§VII, PlaceIT configuration] The comparison in the 'PlaceIT configuration' may be unfair. In the 'baseline configuration', memory- and IO-chiplets have a single PHY and cannot relay, while in the 'PlaceIT configuration' all chiplets have four PHYs and relay capability. The baseline 2D mesh, with memory/IO chiplets on the perimeter, cannot exploit the additional PHYs and relay capability because its topology is fixed and the extra PHYs face unused directions. PlaceIT's optimizer, in contrast, can use these resources to create additional links and relay paths. The statement that total memory/IO bandwidth is unchanged does not equalize topological resources. The baseline should also be allowed to use the extra PHYs and relay in a meaningful way (for example, by adding links from perimeter chiplets) so that the comparison isolates the benefit of co-optimization from the benefit of additional PHY/relay resources.
  3. [§VII-D] The paper concedes that 'either our performance estimate or our cost function does not fully reflect the performance on real traces' and that best random sometimes outperforms the genetic algorithm on partial traces. This admission directly undermines the assumed link between the optimization objective and the final BookSim2 latency metric. The authors should quantify the degree of mis-ranking, for instance by reporting the correlation between the cost function values and simulated latencies across a set of designs, and explain why the reported average reductions remain meaningful despite this mis-ranking.
  4. [§VII-A and §VII-D] Only the blackscholes trace is simulated in full; all other traces are truncated to the first 1,000,000 cycles of each region. The partial-trace results in Fig. 16 are reported only as averages (92% and 82% of baseline latency), without per-trace breakdowns, confidence intervals, or a clear statement of how many traces actually improve. Given that the paper itself notes instances where best random beats the genetic algorithm, the claim that PlaceIT reduces average packet latency 'in almost all traces' requires supporting per-trace data, including a discussion of whether the truncated regions are representative of the full application behavior.
minor comments (8)
  1. [Abstract] The sentence 'It also achieve an average packet latency reduction' should read 'It also achieves an average packet latency reduction'.
  2. [§IV-B] The phrase 'throughput this paper' appears to be a typo for 'throughout this paper'.
  3. [Table III] The Mutation Mode entry 'neighbors-one' does not match the terminology defined in §V-A ('neighbor-one'); the typo should be corrected.
  4. [Table IV] The distance type 'Eucledian' should be spelled 'Euclidean'.
  5. [Table V] The word 'Alforithm' in the table header should be 'Algorithm'.
  6. [§VII-A] The phrase 'the only one to terminated within 24 hours' should be 'the only one to terminate within 24 hours'.
  7. [Fig. 8 caption] The word 'dissallowing' should be 'disallowing'.
  8. [§VII] The sentence 'the total memory- and IO-bandwidth stays unchanged' is ambiguous; it should clarify whether the baseline in the PlaceIT configuration also has four PHYs and relay capability, and if so, how those resources are used.

Circularity Check

0 steps flagged · score 0.0 of 10

No significant circularity: PlaceIT's reported latency reductions are measured by an independent cycle-accurate simulator, not derived from its cost function or from self-citations.

full rationale

PlaceIT's derivation chain separates the optimization objective from the evaluation metric. The cost function (Section IV-B) uses RapidChiplet latency and throughput proxies weighted by traffic fractions observed in Netrace traces, while the reported latency reductions (Sections VII-B to VII-D) come from cycle-accurate BookSim2 simulations of the resulting topologies on synthetic traffic and Netrace traces. The evaluation is therefore a measured outcome, not a term-by-term consequence of the cost function; the paper's own Section VII-D admission that 'either our performance estimate or our cost function does not fully reflect the performance on real traces' shows the proxy can mis-rank designs, which is evidence against the claim that the result is forced by construction. The use of the same Netrace collection to set cost-function weights and to evaluate is a legitimate in-sample evaluation concern, and the RapidChiplet citations are to the authors' own open-source toolchain, but neither makes the headline latency numbers equivalent to the inputs. Consequently, no circular step meeting the required standard is present.

Assumptions & free parameters 4 free parameters · 5 assumptions · 0 invented entities

The central claim rests on several hand-set parameters (cost weights, max link length, PHY latencies) and on domain assumptions about the fidelity of RapidChiplet and BookSim2. No new physical entities are postulated. The cost weights are tuned to the same trace collection used for evaluation, which is the most significant circularity.

free parameters (4)
  • Cost function weights = 2 for area/C2M/M2I, 0.1 for C2C/C2I
    Weights are chosen by hand after analyzing Netrace v1.0 traffic mixes (Section V-B), tuning the optimization objective to the same trace family used in evaluation.
  • Maximum link length = 3 mm
    Used for heterogeneous placements (Table IV); directly determines which PHYs can be connected, shaping the inferred topology.
  • PHY/link/relay latencies = LP=12, LL=1, LR=10 cycles
    Set in Tables III and IV; these values feed the RapidChiplet latency proxy used for optimization and for BookSim2 matching.
  • Number of PHYs in PlaceIT configuration = 4 PHYs and relay capability for all chiplets
    In the PlaceIT configuration (Section VII), all chiplets are given four PHYs and relay capability, while the paper claims total memory/IO bandwidth remains unchanged; this parameter affects the fairness of the baseline comparison.
assumptions (5)
  • domain assumption RapidChiplet provides latency and throughput proxies accurate enough to guide optimization.
    Section IV-A: the cost function and the evaluation rely on RapidChiplet estimates; the authors' own trace results show this proxy can mis-rank designs.
  • domain assumption BookSim2 with packet sizes of 1 and 9 flits models realistic NoC behavior for 2.5D chiplet ICIs.
    Section VII-A: all simulation results depend on this cycle-accurate simulator and its configuration.
  • domain assumption The 2D mesh baseline with memory and IO chiplets on the perimeter is representative of state-of-the-art 2.5D designs.
    Section VII: all comparisons use this baseline; no direct comparison to prior placement/topology optimization tools is performed because they are not open-source or do not scale.
  • domain assumption Netrace traces contain cache coherency traffic representative of general multi-chiplet workloads.
    Used both to set cost function weights (Section V-B) and to evaluate the final designs (Sections VII-C and VII-D).
  • standard math An MST over candidate edges yields a sensible base topology for the inferred ICI.
    Section VI-A: this algorithmic choice is a standard way to connect all vertices at minimum total edge weight, though it is not physically guaranteed to be the best topology.

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Cite this review

Pith. "Pith review of PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies." pith.science (2026). https://pith.science/paper/CW5CI7HV

@misc{pith2026250201449,
  author       = {Pith},
  title        = {Pith review of: PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/CW5CI7HV}},
  note         = {Machine review of arXiv:2502.01449}
}
read the original abstract

2.5D integration technology is gaining traction as it copes with the exponentially growing design cost of modern integrated circuits. A crucial part of a 2.5D stacked chip is a low-latency and high-throughput inter-chiplet interconnect (ICI). Two major factors affecting the latency and throughput are the topology of links between chiplets and the chiplet placement. In this work, we present PlaceIT, a novel methodology to jointly optimize the ICI topology and the chiplet placement. While state-of-the-art methods optimize the chiplet placement for a predetermined ICI topology, or they select one topology out of a set of candidates, we generate a completely new topology for each placement. Our process of inferring placement-based ICI topologies connects chiplets that are in close proximity to each other, making it particularly attractive for chips with silicon bridges or passive silicon interposers with severely limited link lengths. We provide an open-source implementation of our method that optimizes the placement of homogeneously or heterogeneously shaped chiplets and the ICI topology connecting them for a user-defined mix of four different traffic types. We evaluate our methodology using synthetic traffic and traces, and we compare our results to a 2D mesh baseline. PlaceIT reduces the latency of synthetic L1-to-L2 and L2-to-memory traffic, the two most important types for cache coherency traffic, by up to 28% and 62%, respectively. It also achieve an average packet latency reduction of up to 18% on traffic traces. PlaceIT enables the construction of 2.5D stacked chips with low-latency ICIs.

Figures

Figures reproduced from arXiv: 2502.01449 by the authors.

Figure 1
Figure 1. (§II-A) 2.5D integration technologies (side view). We show a core-to-core link (red) and an off-chip link (purple). based ICI topology by connecting chiplets that are in close proximity in that specific placement. We then compute the latency and throughput of this combination of placement and topology for different traffic types. These latencies and throughputs together with the total chip area are used to compute a… view at source ↗
Figure 2
Figure 2. (§III) Placement and topology co-optimization. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 3
Figure 3. (§IV) Overview of the PlaceIT architecture. [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗
Figures from the paper (12 more)
Figure 4
Figure 4. Figure 4: (§IV-B) Correlation of cost value with its components. [PITH_FULL_IMAGE:figures/full_fig_p005_4.png]
Figure 5
Figure 5. Figure 5: (§V-A) Homogeneous placement representation. [PITH_FULL_IMAGE:figures/full_fig_p005_5.png]
Figure 6
Figure 6. Figure 6: (§V-B) Results for homogeneously shaped chiplets. [PITH_FULL_IMAGE:figures/full_fig_p006_6.png]
Figure 8
Figure 8. Figure 8: (§VI-A) Prevent multiple (order, rotations)-pairs [PITH_FULL_IMAGE:figures/full_fig_p006_8.png]
Figure 9
Figure 9. Figure 9: (§VI-A) Inferring the placement-based ICI topology [PITH_FULL_IMAGE:figures/full_fig_p007_9.png]
Figure 11
Figure 11. Figure 11: (§VI-B) Chiplet dimensions and PHY locations. [PITH_FULL_IMAGE:figures/full_fig_p007_11.png]
Figure 12
Figure 12. Figure 12: (§VI-B) Results for heterogeneous chiplet shapes. [PITH_FULL_IMAGE:figures/full_fig_p008_12.png]
Figure 13
Figure 13. Figure 13: (§VII) Baseline architecture and optimized architecture found by PlaceIT (for the [PITH_FULL_IMAGE:figures/full_fig_p009_13.png]
Figure 14
Figure 14. Figure 14: (§VII-B) Results on synthetic traffic using the [PITH_FULL_IMAGE:figures/full_fig_p009_14.png]
Figure 16
Figure 16. Figure 16: (§VII-D) Results for the partial trace regions: [PITH_FULL_IMAGE:figures/full_fig_p010_16.png]
Figure 17
Figure 17. Figure 17: (§VII-C) speedup over baseline in average [PITH_FULL_IMAGE:figures/full_fig_p010_17.png]
Figure 18
Figure 18. Figure 18: (§VII-C) speedup over baseline in average [PITH_FULL_IMAGE:figures/full_fig_p010_18.png]

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Reference graph

Works this paper leans on

39 extracted references · 38 canonical work pages

  1. [1]

    Bunch of Wires (BoW) PHY Specification,

    E. Alon, M. Hempel, K. Poulton, S. Ardalan, and B. Vinnakota, “Bunch of Wires (BoW) PHY Specification,” https://opencomputeproject.github. io/ODSA-BoW/bow specification.html

    work page

  2. [2]

    Bunch of wires: An open die-to-die interface,

    S. Ardalan, H. Cirit, R. Farjad, M. Kuemerle, K. Poulton, S. Subrama- nian, and B. Vinnakota, “Bunch of wires: An open die-to-die interface,” in 2020 IEEE Symposium on High-Performance Interconnects (HOTI) . IEEE, 2020, pp. 9–16

    work page 2020

  3. [3]

    Reliability evaluation of a cowos-enabled 3d ic package,

    B. Banijamali, C.-C. Chiu, C.-C. Hsieh, T.-S. Lin, C. Hu, S.-Y . Hou, S. Ramalingam, S.-P. Jeng, L. Madden, and D. C. Yu, “Reliability evaluation of a cowos-enabled 3d ic package,” in 2013 IEEE 63rd Electronic Components and Technology Conference . IEEE, 2013, pp. 35–40

    work page 2013

  4. [4]

    Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling,

    S. Bharadwaj, J. Yin, B. Beckmann, and T. Krishna, “Kite: A family of heterogeneous interposer topologies enabled via accurate interconnect modeling,” in 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE, 2020, pp. 1–6

    work page 2020

  5. [5]

    The parsec benchmark suite: Characterization and architectural implications,

    C. Bienia, S. Kumar, J. P. Singh, and K. Li, “The parsec benchmark suite: Characterization and architectural implications,” in Proceedings of the 17th international conference on Parallel architectures and compilation techniques, 2008, pp. 72–81

    2008

  6. [6]

    High-speed perfor- mance of silicon bridge die-to-die interconnects,

    H. Braunisch, A. Aleksov, S. Lotz, and J. Swan, “High-speed perfor- mance of silicon bridge die-to-die interconnects,” in 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems. IEEE, 2011, pp. 95–98

    work page 2011

  7. [7]

    Chiplet placement for 2.5 d ic with sequence pair based tree and thermal consideration,

    H.-W. Chiou, J.-H. Jiang, Y .-T. Chang, Y .-M. Lee, and C.-W. Pan, “Chiplet placement for 2.5 d ic with sequence pair based tree and thermal consideration,” in Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023, pp. 7–12

    work page 2023

  8. [8]

    Cross-layer co-optimization of network design and chiplet placement in 2.5-d systems,

    A. Coskun, F. Eris, A. Joshi, A. B. Kahng, Y . Ma, A. Narayan, and V . Srinivas, “Cross-layer co-optimization of network design and chiplet placement in 2.5-d systems,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 39, no. 12, pp. 5183– 5196, 2020

    work page 2020

Show all 39 references
  1. [9]

    A cross-layer methodology for design and optimization of networks in 2.5 d systems,

    A. Coskun, F. Eris, A. Joshi, A. B. Kahng, Y . Ma, and V . Srinivas, “A cross-layer methodology for design and optimization of networks in 2.5 d systems,” in 2018 IEEE/ACM International Conference on Computer- Aided Design (ICCAD) . IEEE, 2018, pp. 1–8

    2018

  2. [10]

    Active interposer technology for chiplet- based advanced 3d system architectures,

    P. Coudrain, J. Charbonnier, A. Garnier, P. Vivet, R. Velard, A. Vinci, F. Ponthenier, A. Farcy, R. Segaud, P. Chausse, L. Arnaud, D. Lat- tard, E. Guthmuller, G. Romano, A. Gueugnot, F. Berger, J. Beltritti, T. Mourier, M. Gottardi, S. Minoret, C. Ribiere, G. Romero, P.-E. Ph...

    2019

  3. [11]

    Leveraging thermally-aware chiplet organization in 2.5 d systems to reclaim dark silicon,

    F. Eris, A. Joshi, A. B. Kahng, Y . Ma, S. Mojumder, and T. Zhang, “Leveraging thermally-aware chiplet organization in 2.5 d systems to reclaim dark silicon,” in 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) . IEEE, 2018, pp. 1441–1446

    2018

  4. [12]

    Dataflow- architecture co-design for 2.5 d dnn accelerators using wireless network- on-package,

    R. Guirado, H. Kwon, S. Abadal, E. Alarc ´on, and T. Krishna, “Dataflow- architecture co-design for 2.5 d dnn accelerators using wireless network- on-package,” in 2021 26th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2021, pp. 806–812

    2021

  5. [13]

    Netraces v1.0 (A collection of network traces with dependency information)

    J. Hestness, B. Grot, and S. W. Keckler, “Netraces v1.0 (A collection of network traces with dependency information).” https://www.cs.utexas. edu/∼netrace/

  6. [14]

    Netrace: dependency-driven trace-based network-on-chip simu- lation,

    ——, “Netrace: dependency-driven trace-based network-on-chip simu- lation,” in Proceedings of the Third International Workshop on Network on Chip Architectures, 2010, pp. 31–36

    2010

  7. [15]

    Netrace: Dependency-tracking traces for efficient network-on-chip experimentation,

    J. Hestness and S. W. Keckler, “Netrace: Dependency-tracking traces for efficient network-on-chip experimentation,” The University of Texas at Austin, Dept. of Computer Science, Tech. Rep , 2011

    2011

  8. [16]

    Multiple chip planning for chip-interposer codesign,

    Y .-K. Ho and Y .-W. Chang, “Multiple chip planning for chip-interposer codesign,” in Proceedings of the 50th Annual Design Automation Con- ference, 2013, pp. 1–6

    2013

  9. [17]

    Hecaton: Training and finetuning large language models with scalable chiplet systems,

    Z. Huang, S. Fan, C. Tang, X. Lin, S. Deng, and Y . Liu, “Hecaton: Training and finetuning large language models with scalable chiplet systems,” arXiv preprint arXiv:2407.05784 , 2024

    2024 arXiv

  10. [18]

    Hexamesh: Scaling to hundreds of chiplets with an optimized chiplet arrangement,

    P. Iff, M. Besta, M. Cavalcante, T. Fischer, L. Benini, and T. Hoefler, “Hexamesh: Scaling to hundreds of chiplets with an optimized chiplet arrangement,” arXiv preprint arXiv:2211.13989 , 2022

    2022 arXiv

  11. [19]

    Rapidchiplet: A toolchain for rapid design space exploration of chiplet architectures,

    P. Iff, B. Bruggmann, M. Besta, L. Benini, and T. Hoefler, “Rapidchiplet: A toolchain for rapid design space exploration of chiplet architectures,” 2023

    2023

  12. [20]

    A detailed and flexible cycle-accurate network-on-chip simulator,

    N. Jiang, D. U. Becker, G. Michelogiannakis, J. Balfour, B. Towles, D. E. Shaw, J. Kim, and W. J. Dally, “A detailed and flexible cycle-accurate network-on-chip simulator,” in 2013 IEEE international symposium on performance analysis of systems and software (ISPASS) . IEEE, 20...

    2013

  13. [21]

    Enabling interposer-based disintegration of multi-core processors,

    A. Kannan, N. E. Jerger, and G. H. Loh, “Enabling interposer-based disintegration of multi-core processors,” in Proceedings of the 48th international symposium on Microarchitecture , 2015, pp. 546–558

    2015

  14. [22]

    Silicon vs. organic interposer: Ppa and reliability tradeoffs in heterogeneous 2.5 d chiplet integration,

    J. Kim, V . C. K. Chekuri, N. M. Rahman, M. A. Dolatsara, H. Torun, M. Swaminathan, S. Mukhopadhyay, and S. K. Lim, “Silicon vs. organic interposer: Ppa and reliability tradeoffs in heterogeneous 2.5 d chiplet integration,” in 2020 IEEE 38th International Conference on Compute...

    2020

  15. [23]

    Cifher: A chiplet-based fhe accelerator with a resizable structure,

    S. Kim, J. Kim, J. Choi, and J. Ho Ahn, “Cifher: A chiplet-based fhe accelerator with a resizable structure,” arXiv preprint arXiv:2308.04890, 2023

    2023 arXiv

  16. [24]

    Chiplet heterogeneous integration,

    J. H. Lau and J. H. Lau, “Chiplet heterogeneous integration,” Semicon- ductor Advanced Packaging, pp. 413–439, 2021

    2021

  17. [25]

    Multi- die integration using advanced packaging technologies,

    H.-J. Lee, R. Mahajan, F. Sheikh, R. Nagisetty, and M. Deo, “Multi- die integration using advanced packaging technologies,” in 2020 IEEE Custom Integrated Circuits Conference (CICC) . IEEE, 2020, pp. 1–7

    2020

  18. [26]

    Chiplet heteroge- neous integration technology-status and challenges,

    T. Li, J. Hou, J. Yan, R. Liu, H. Yang, and Z. Sun, “Chiplet heteroge- neous integration technology-status and challenges,” Electronics, vol. 9, no. 4, p. 670, 2020

    2020

  19. [27]

    Floorplanning and signal assignment for silicon interposer-based 3d ics,

    W.-H. Liu, M.-S. Chang, and T.-C. Wang, “Floorplanning and signal assignment for silicon interposer-based 3d ics,” in Proceedings of the 51st Annual Design Automation Conference , 2014, pp. 1–6

    2014

  20. [28]

    Tap-2.5 d: A thermally-aware chiplet placement methodology for 2.5 d systems,

    Y . Ma, L. Delshadtehrani, C. Demirkiran, J. L. Abellan, and A. Joshi, “Tap-2.5 d: A thermally-aware chiplet placement methodology for 2.5 d systems,” in 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) . IEEE, 2021, pp. 1246–1251

    2021

  21. [29]

    Embed- ded multi-die interconnect bridge (emib)–a high density, high bandwidth packaging interconnect,

    R. Mahajan, R. Sankman, N. Patel, D.-W. Kim, K. Aygun, Z. Qian, Y . Mekonnen, I. Salama, S. Sharan, D. Iyengar, and D. Mallik, “Embed- ded multi-die interconnect bridge (emib)–a high density, high bandwidth packaging interconnect,” in 2016 IEEE 66th Electronic Components and T...

    2016

  22. [30]

    The saga of minimum spanning trees,

    M. Mare ˇs, “The saga of minimum spanning trees,” Computer Science Review, vol. 2, no. 3, pp. 165–221, 2008

    2008

  23. [31]

    Pioneering chiplet technology and design for the amd epyc™ and ryzen™ processor families: Industrial product,

    S. Naffziger, N. Beck, T. Burd, K. Lepak, G. H. Loh, M. Subramony, and S. White, “Pioneering chiplet technology and design for the amd epyc™ and ryzen™ processor families: Industrial product,” in 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)...

    2021

  24. [32]

    Optimal die placement for interposer-based 3d ics,

    S. Osmolovskyi, J. Knechtel, I. L. Markov, and J. Lienig, “Optimal die placement for interposer-based 3d ics,” in 2018 23rd Asia and South Pacific design automation conference (ASP-DAC) . IEEE, 2018, pp. 513–520

    2018

  25. [33]

    Automatic die placement and flexible i/o assignment in 2.5 d ic design,

    D. P. Seemuth, A. Davoodi, and K. Morrow, “Automatic die placement and flexible i/o assignment in 2.5 d ic design,” in Sixteenth International Symposium on Quality Electronic Design . IEEE, 2015, pp. 524–527

    2015

  26. [34]

    Cluscross: a new topology for sili- con interposer-based network-on-chip,

    H. Shabani and X. Guo, “Cluscross: a new topology for sili- con interposer-based network-on-chip,” in Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip , 2019, pp. 1–8

    2019

  27. [35]

    Simba: scaling deep-learning inference with chiplet-based architecture,

    Y . S. Shao, J. Cemons, R. Venkatesan, B. Zimmer, M. Fojtik, N. Jiang, B. Keller, A. Klinefelter, N. Pinckney, P. Raina, S. G. Tell, Y . Zhang, W. J. Dally, J. Emer, C. Gray, B. Khailany, and S. W. Keckler, “Simba: scaling deep-learning inference with chiplet-based architectur...

    2021

  28. [36]

    Direct bonded heterogeneous integration (dbhi) si bridge,

    K. Sikka, R. Bonam, Y . Liu, P. Andry, D. Parekh, A. Jain, M. Bergen- dahl, R. Divakaruni, M. Cournoyer, P. Gagnon, C. Dufort, I. de Sousa, H. Zhang, E. Cropp, T. Wassick, H. Mori, and S. Kohara, “Direct bonded heterogeneous integration (dbhi) si bridge,” in2021 IEEE 71st Elec...

    2021

  29. [37]

    Dojo: The microarchitecture of tesla’s exa-scale computer,

    E. Talpes, D. Williams, and D. D. Sarma, “Dojo: The microarchitecture of tesla’s exa-scale computer,” in 2022 IEEE Hot Chips 34 Symposium (HCS). IEEE Computer Society, 2022, pp. 1–28

    2022

  30. [38]

    Universal Chiplet Interconnect Express (UCIe) Specification,

    The UCIe Consortium, “Universal Chiplet Interconnect Express (UCIe) Specification,” https://www.uciexpress.org/specification

  31. [39]

    IntAct: A 96-core processor with six chiplets 3D-stacked on an active interposer with distributed interconnects and integrated power management,

    P. Vivet, E. Guthmuller, Y . Thonnart, G. Pillonnet, Senior, C. Fuguet, I. Miro-Panades, G. Moritz, J. Durupt, C. Bernard, D. Varreau, J. Pontes, S. Thuries, D. Coriat, M. Harr, D. Dutoit, D. Lattard, L. Arnaud, J. Char- bonnier, P. Coudrain, A. Garnier, F. Berger, A. Gueugnot...

    2020

Pith tools

Reviewed August 9, 2026 · model on record in the stance chip above.