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REVIEW 2 major objections 4 minor 27 references

ILP over circuit gauge operators produces fault-tolerant state-prep circuits at or below prior gate counts for all 12 codes tested, and a [[24,10,4]] Steane gadget with ~1.4e-5 per-qubit logical error rate on H2.

Reviewed by Pith at T0; open to challenge. T0 means a machine referee read the full paper against a public rubric. the ladder, T0–T4 →

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2026-08-01 04:32 UTC pith:DBD6L2NE

load-bearing objection Genuine ILP-based advance in flag circuit synthesis with SOTA-beating gate counts, but the FT guarantee is not fully proven — needs a rigorous fault-injection check. the 2 major comments →

arxiv 2607.22498 v1 pith:DBD6L2NE submitted 2026-07-24 quant-ph

Automated Flag-based Fault-Tolerant State Preparation using Integer Linear Programming

Ben Criger , Aaron Hankin , Justin J. Burau , Abigail R. Perry This is my paper
classification quant-ph PACS 03.67.Pp03.67.Lx
keywords fault-tolerant state preparationinteger linear programmingcircuit gauge operatorsflag-based error detectionSteane error correctionpost-selectionquantum error correctiontrapped-ion quantum computer
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

This paper aims to show that fault-tolerant state-preparation circuits, essential for initializing logical qubits and for Steane/Knill error-correction gadgets, can be constructed automatically by solving an integer linear program over circuit gauge operators. The ILP selects a set of low-weight gauge operators whose measurement, implemented as flag subcircuits, detects every dangerous combination of up to t faults. Comparisons across 12 codes show the resulting circuits match or beat the gate counts of the two leading automated methods. A hardware demonstration on Quantinuum's H2 machine with a Steane gadget for the [[24,10,4]] code yields a block logical error rate of about 1.4e-4, about 1.4e-5 per logical qubit. If correct, this makes automated design of fault-tolerant state preparation practical for medium-size codes and points towards a general optimization-based approach to fault-tolerant circuit design.

Core claim

The paper's central claim is that flag-based fault-tolerant state preparation reduces to weighted set cover over circuit gauge operators: each flag subcircuit measures a gauge operator, and the set of faults it detects is exactly those whose 'spackle' (spacetime support) anticommutes with that operator. Choosing which gauge operators to measure so that all dangerous fault sets are covered is a weighted set cover problem, solved here with integer linear programming. The authors show that this ILP construction produces circuits with gate counts equal to or lower than the state of the art for all 12 codes considered, detecting up to three faults, and that a Steane error-correction gadget for th

What carries the argument

The central object is the circuit gauge operator: a Pauli operator supported on spacetime locations of a circuit that is equivalent to the identity when inserted into the circuit. Flag subcircuits are shown to measure such operators, detecting exactly those fault sets whose spackle (the spacetime support of the propagated faults) anticommutes with the gauge operator. The task of promoting a circuit to tolerate t faults becomes weighted set cover: choose low-weight gauge operators (cost = weight + 1, corresponding to controlled-Pauli gates plus one measurement) whose anticommuting spackle sets cover all dangerous fault sets. The set-cover instance is solved by an integer linear program, with

Load-bearing premise

The paper's fault-tolerance guarantee assumes Algorithm 1 finds every gauge operator needed to cover dangerous spackle sets, and that the final-stage proof, which analyzes faults after two-qubit gates, also covers ancilla preparation and measurement faults; neither is proven.

What would settle it

Run full state-vector simulation with a depolarizing noise model on one ILP-derived circuit (e.g., [[24,10,4]] or [[7,1,3]]) and enumerate all single-fault and pair-fault sets; if any fault set produces an output error of weight greater than t without triggering a flag, the fault-tolerance claim is falsified. Alternatively, exhaustively enumerate all gauge operators for a small code and check whether Algorithm 1 misses a gauge that is required to cover a dangerous spackle, which would falsify the completeness of the heuristic.

Watch this falsifier. Get emailed when new claim-graph text bears on it.

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If this is right

  • For every one of the 12 codes tested, the ILP-derived circuits match or beat the gate counts of the two prior automated methods, with the largest reductions on high-rate codes (e.g., 89 vs 170 operations for the [[24,10,4]] 2BGA code).
  • The method automates construction of flag circuits that detect up to three faults, scaling to codes of distance up to 7 with block sizes up to 42 qubits.
  • The [[24,10,4]] Steane gadget produced one logical error in 7,117 accepted shots (block error ~1.4e-4, per-qubit ~1.4e-5), with only ~1.6% of shots post-selected, demonstrating fault-tolerant preparation below typical physical two-qubit gate error rates.
  • Because the ILP formulation is based on the circuit gauge operator formalism, it provides a unified explanation of flag circuits and can be applied to other fault-tolerant subroutines beyond state preparation.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • The cost function used in the ILP (weight + 1) ignores the fact that each added flag subcircuit introduces new fault locations; a more accurate cost would likely lead to even smaller circuits, as the authors themselves suggest.
  • The same gauge-operator covering approach could be extended to promote non-fault-tolerant circuits for logical operations (e.g., fold-transversal gates), although this requires embedding a decoder in the exit criterion.
  • The hardware result is a single code and a single device; the claim that gate-count reduction translates into lower logical error rates would be strengthened by applying the ILP pipeline to several codes and comparing on multiple machines.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit.

Referee Report

2 major / 4 minor

Summary. The paper proposes an automated method for constructing flag-based fault-tolerant stabilizer state preparation circuits. The construction is framed as a weighted set-cover problem over circuit gauge operators, solved with integer linear programming (ILP). The authors describe a heuristic algorithm (Algorithm 1) that generates low-weight gauge operators, then select a set of gauge measurements whose detection syndromes cover all dangerous fault combinations. They apply the method to 12 CSS codes and report gate counts that match or beat prior state-of-the-art circuits, with improvements most pronounced for high-rate codes. They also implement a Steane error-correction gadget for the [[24,10,4]] two-block group algebra code and run it on Quantinuum H2, reporting a logical block error rate of about 1.4e-4 based on one logical error in 7117 accepted shots.

Significance. If the fault-tolerance guarantees can be rigorously established, this would be a solid and useful contribution. The ILP/gauge-operator formulation is a natural extension of earlier SAT-based and flag-at-origin methods, and the reported constant-factor gate-count improvements are valuable for near-term QEC subroutines. The paper also contains a rare hardware demonstration of an optimized logical gadget. The explicit circuits in the appendices and reproducible gate-count comparisons are assets. However, the central correctness claim depends on a fault-tolerance proof that is not yet complete, and on a heuristic gauge-generation step whose completeness is not certified. The contribution is conditionally significant pending those points.

major comments (2)
  1. [Section III, Table I] The proof that a bare-ancilla weight-3 gauge measurement 'does not produce high-weight faults not seen in the original circuit C' examines only Pauli generators occurring after each two-qubit gate (Table I). It does not analyze faults in the |+> ancilla preparation or in the final X-basis measurement. A Z fault on the ancilla immediately after preparation propagates through the controlled gates into the data as PQR (the measured gauge operator), and a measurement fault can convert a legitimate non-trivial flag syndrome into a false negative. Neither of these single-fault channels is covered by Table I or the surrounding argument. Since this proof is the only formal justification that the promotion procedure preserves fault tolerance, the FT claim for all 12 circuits in Table II is not established. Please either extend the proof/table to all fault locations or provide exhaustive fault-inj
  2. [Section II.A; Eq. (5)] The ILP set-cover constraints in Eq. (5) are only over the gauge set G produced by Algorithm 1, which the paper states is 'not guaranteed to be as large as possible.' If a dangerous spackle is not covered by any generated gauge, the ILP is infeasible; but if the dangerous-spackle set S itself is under-generated, or the reduction by 'equivalent to an operator of weight ≤ t' is done incorrectly, the ILP can return a circuit that satisfies the constraints yet is not fault-tolerant. No certificate or exhaustive simulation is provided for the distance-5, -6, and -7 circuits in Table II. The completeness of S and of the generated gauge set is a load-bearing assumption for the paper's headline claim. Please add an explicit verification step or a proof of completeness for the generated gauge set.
minor comments (4)
  1. [Section IV A / Table III] The hardware estimate 'one logical error in 7117 accepted shots implies a logical error rate of 1/7117 ~ 1.4e-4' is a point estimate from a single Bernoulli observation. With one event, the 95% confidence interval spans roughly an order of magnitude. Please report an interval (e.g., Wilson) and the calibration conditions, since the hardware claim is presented without uncertainty.
  2. [Abstract / throughout] There are several typographical and formatting issues: '104 shots' should be '10^4 shots'; 'theJ7,1,3KSteane code' is missing bracket delimiters; and some exponent notation is garbled. The manuscript would benefit from a careful proofreading pass.
  3. [Table I / Section III] The notation in Table I (e.g., 'IP', 'IP⊥', 'Q1R5', syndrome columns) is not explained in sufficient detail. Without a definition of the location labels and the convention for propagating generators, the reader cannot independently verify the table. An explicit derivation for one row would greatly improve accessibility.
  4. [Table II] The comparison to state-of-the-art gate counts relies on several external sources, including one private communication [19]. For reproducibility, please state the precise version and settings of the prior methods, and clarify whether all SOTA values use the same fault-tolerance definition (number of detected faults, post-selection criteria, and error model).

Circularity Check

0 steps flagged

No significant circularity: ILP outcomes are benchmarked against external SOTA and the gauge-operator formalism is external; no step reduces to its own input by construction.

full rationale

The derivation chain is: (1) choose a non-fault-tolerant initial circuit, either by hand or via the separately published beam-search generator [16]; (2) express flag measurements as circuit-gauge-operator measurements using the formalism of Bacon et al. [11]; (3) enumerate dangerous spackle sets and solve weighted set cover as the integer linear program in Eq. (5); (4) prove by Table I that final-stage weight-3 flag faults are equivalent to faults in the original circuit; (5) compare gate counts against external SOTA references in Table II and measure the [[24,10,4]] gadget on Quantinuum H2. The ILP objective c_g = weight(g)+1 is a fixed cost model, not fitted to targets, and fault tolerance is enforced as a set-cover constraint, not predicted from a fitted parameter. The only author-overlapping input is the initial-circuit generator [16], but it is used transparently as a subroutine and its own non-FT gate counts are separately tabulated against SOTA in Table II, so the improvement claim does not reduce to a self-citation. The admitted heuristic incompleteness of Algorithm 1 ('not guaranteed to be as large as possible') and the restricted fault analysis in Sec. III are correctness risks rather than circularity, since the paper's own per-circuit verification statements ('All single faults are detected...') are checkable claims independent of the ILP formulation.

Axiom & Free-Parameter Ledger

3 free parameters · 4 axioms · 0 invented entities

The central claim depends on the spackle formalism [11] and a standard fault model; the paper adds hand-chosen constraints (max gauge weight 3, output weight <=1) and a heuristic gauge-generation algorithm whose completeness is unproven. No new physical entities are introduced.

free parameters (3)
  • maxWeight (gauge operator weight cap) = 3 (final promotion; larger for intermediate steps)
    Hand-chosen; restricts the ILP to low-weight gauges so the Section III fault-tolerance argument applies; affects circuit quality.
  • output weight limit = 1
    Hand-chosen; required by the proof that final-stage flags do not introduce new high-weight errors.
  • ILP cost coefficients = c_g = weight(g)+1
    Modeling choice approximating hardware error rates; acknowledged in footnote [15] to be suboptimal for dissimilar SPAM/2Q rates.
axioms (4)
  • domain assumption Circuit gauge operator formalism and spackle characterization (Bacon et al. [11])
    Eqs. (3)-(4) rely on [11] for the spackle concept and the claim that flag measurement detects fault sets whose spackles anticommute with the gauge operator.
  • domain assumption Fault model: single faults at each location after preparation, two-qubit gate, and measurement
    Used to enumerate spackles S in Section III; standard for FT circuit analysis.
  • ad hoc to paper Bare-ancilla weight-3 gauge measurement with output weight <=1 introduces no new first-order errors
    Section III proof covers faults after two-qubit gates only; prep/measurement faults are not explicitly analyzed, so this functions as an assumption for the final-stage guarantee.
  • ad hoc to paper Algorithm 1 generates all gauge operators necessary for promotion
    Unproven completeness; the ILP can only cover spackles covered by generated gauges.

reviewed 2026-08-01 · how reviews work

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Cite this review

Pith. "Pith review of Automated Flag-based Fault-Tolerant State Preparation using Integer Linear Programming." pith.science (2026). https://pith.science/paper/DBD6L2NE

@misc{pith2026260722498,
  author       = {Pith},
  title        = {Pith review of: Automated Flag-based Fault-Tolerant State Preparation using Integer Linear Programming},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/DBD6L2NE}},
  note         = {Machine review of arXiv:2607.22498}
}
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read the original abstract

Post-selected stabilizer state preparation is a necessary subroutine in fault-tolerant quantum computation, both for initialization of logical qubits, and for logical-ancilla-based error correction gadgets (e.g. Steane and Knill). Therefore, reducing the number of gates needed to prepare a stabilizer state fault-tolerantly can simultaneously reduce time-to-solution and increase reliability. For small, low-distance codes such as the [[7, 1, 3]] Steane code, circuits with low gate counts can be found by inspection. This becomes impractical for larger codes, necessitating automation. There are two state-of-the-art methods for automated fault-tolerant state preparation, SAT-based stabilizer measurement and flag-at-origin. In this work, we optimize state preparation circuits using the circuit gauge operator formalism to express the construction of flag circuits as an integer linear program. This allows the construction of circuits with equal or lower gate count than the state of the art, while detecting up to three errors. We use this technique to derive a Steane error correction gadget for the [[24, 10, 4]] two-block group algebra code, and test it on Quantinuum's System Model H2 quantum computer with 10,000 shots, resulting in a logical block error rate ~0.00014 (~0.000014 per logical qubit), with ~1.6% of the shots post-selected due to weight-two errors.

Figures

Figures reproduced from arXiv: 2607.22498 by Aaron Hankin, Abigail R. Perry, Ben Criger, Justin J. Burau.

Figure 1
Figure 1. Figure 1: FIG. 1. From [7]; a circuit for fault-tolerant [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 3
Figure 3. Figure 3: FIG. 3. Elements of a generating set for the gauge group of a [PITH_FULL_IMAGE:figures/full_fig_p002_3.png] view at source ↗
Figure 4
Figure 4. Figure 4: FIG. 4. A circuit incorporating a flag measurement, com [PITH_FULL_IMAGE:figures/full_fig_p002_4.png] view at source ↗
Figure 2
Figure 2. Figure 2: FIG. 2. A subcircuit measuring [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 5
Figure 5. Figure 5: FIG. 5. Example of gauge-operator-to-flag-circuit mapping. [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: FIG. 6. Bare-ancilla measurement of a weight-3 circuit gauge [PITH_FULL_IMAGE:figures/full_fig_p004_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: FIG. 7. Steane error correction cycle rendered robust to leak [PITH_FULL_IMAGE:figures/full_fig_p005_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: FIG. 8. State preparation circuit for the [PITH_FULL_IMAGE:figures/full_fig_p010_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: FIG. 9. State preparation circuit for the [PITH_FULL_IMAGE:figures/full_fig_p010_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: FIG. 10. State preparation circuit for the [PITH_FULL_IMAGE:figures/full_fig_p011_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: FIG. 11. State preparation circuit for the [PITH_FULL_IMAGE:figures/full_fig_p011_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: FIG. 12. State preparation circuit for the [PITH_FULL_IMAGE:figures/full_fig_p012_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: FIG. 13. State preparation circuit for the [PITH_FULL_IMAGE:figures/full_fig_p012_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: FIG. 14. State preparation circuit for the [PITH_FULL_IMAGE:figures/full_fig_p013_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: FIG. 15. State preparation circuits for the [PITH_FULL_IMAGE:figures/full_fig_p014_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: FIG. 16. State preparation circuit for the [PITH_FULL_IMAGE:figures/full_fig_p015_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: FIG. 17. State preparation circuit for the [PITH_FULL_IMAGE:figures/full_fig_p016_17.png] view at source ↗
Figure 18
Figure 18. Figure 18: FIG. 18. State preparation circuit for the [PITH_FULL_IMAGE:figures/full_fig_p017_18.png] view at source ↗
Figure 19
Figure 19. Figure 19: FIG. 19. State preparation circuit for the [PITH_FULL_IMAGE:figures/full_fig_p018_19.png] view at source ↗

discussion (0)

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Reference graph

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This paper was first reviewed by deepseek-v4-flash on August 1, 2026.