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arxiv: 2504.18430 · v1 · pith:DKIUI7X2new · submitted 2025-04-25 · 💻 cs.SE

Efficiency, Expressivity, and Extensibility in a Close-to-Metal NPU Programming Interface

Erika Hunhoff , Joseph Melber , Kristof Denolf , Andra Bisca , Samuel Bayliss , Stephen Neuendorffer , Jeff Fifield , Jack Lo
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Pranathi Vasireddy Phil James-Roxby Eric Keller
This is my paper
classification 💻 cs.SE
keywords efficiencyinterfaceprogrammingfeaturesironclose-to-metalexpressivityextensibility
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Accelerators such as neural processing units (NPUs) deliver an enticing balance of performance and efficiency compared to general purpose compute architectures. However, effectively leveraging accelerator capabilities is not always simple: low-level programming toolkits may require substantial developer effort while high-level programming toolkits may abstract critical optimization features. This work aims to increase efficiency of designers using IRON, a toolkit for close-to-metal NPU performance engineers. We provide an updated programmer interface to IRON containing new and refined programming constructs. The new interface includes extensible features for placement and data transformation. These contributions are evaluated in terms of 1) efficiency, with analysis showing ~26% average reduction in lines of code and decreases in Halstead metrics for a variety of designs; 2) expressivity, demonstrating the new interface supports the wide range of features and patterns already supported by IRON; and 3) extensibility, illustrating the new tooling for placement and tiling can be extended to accommodate common use-cases.

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Cited by 2 Pith papers

Reviewed papers in the Pith corpus that reference this work. Sorted by Pith novelty score.

  1. TileFuse: A Fused Mixed-Precision Kernel Library for Efficient Quantized LLM Inference on AMD NPUs

    cs.DC 2026-06 unverdicted novelty 6.0

    TileFuse introduces fused kernels and data layouts for W4A16/W8A16 on AMD XDNA2 NPUs, reporting up to 2.0x lower LLM prefilling latency and 64.6% lower energy versus baselines.

  2. TileFuse: A Fused Mixed-Precision Kernel Library for Efficient Quantized LLM Inference on AMD NPUs

    cs.DC 2026-06 unverdicted novelty 4.0

    TileFuse introduces a fused kernel library enabling AWQ W4A16/W8A16 quantized LLM inference on AMD NPUs, reporting up to 2.0x lower prefilling latency and 64.6% lower energy on Ryzen AI laptops.