Paper Citation Record · LEDGER

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

As of 7 August 2026, this Paper Citation Record lists 47 of 47 outbound references and 6 inbound Pith citation observations for arXiv:2507.16200.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2507.16200 v1

Coverage vector

measured 47 of 47 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-06T15:19:55.293263Z

measured 53 of 53 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-07T06:34:17.273281+00:00

measured 6 of 6 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-02T07:12:17.009828Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-21T06:54:01.159000Z

Reference resolution

47 of 47 outbound references displayed

verified exact2
verified fuzzy18
unresolved27
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 217b35be-7ec9-4165-9379-2bc8e60f44af · outbound

This paper cites For better or worse, benchmarks shape a field,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs For better or worse, benchmarks shape a field,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:57.682062Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ed612326-f117-484a-ba1b-881e910aefac · outbound

This paper cites GPT-4 Technical Report.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs GPT-4 Technical Report

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:52.089595Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f498e9d2-442d-4d49-b3b7-b86199dfd14f · outbound

This paper cites ChipNeMo: Domain-Adapted LLMs for Chip Design.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:52.190982Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 84c0b0b9-c2a6-4899-9341-9ccb86a0d787 · outbound

This paper cites RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution

Reference 4

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:52.253221Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8b535f76-efe3-42bc-9363-9b88b2a1966e · outbound

This paper cites BetterV: Controlled Verilog Generation with Discriminative Guidance.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs BetterV: Controlled Verilog Generation with Discriminative Guidance

Reference 5

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:52.329639Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 2bfb09c1-36c3-425a-80c4-61964f959cc9 · outbound

This paper cites MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:52.391272Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 892fc982-7977-4821-90dc-29c55e5fc431 · outbound

This paper cites CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:52.497138Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 10c52c32-caab-4bfe-a8f0-524dfcfd82ca · outbound

This paper cites Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework

Reference 8

Resolution: verified exact; local_arxiv, observed 2026-08-06T15:19:55.859908Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 536449ab-59c9-49f3-bb65-ba1989259657 · outbound

This paper cites AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:52.617478Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation fbc4af32-f4e2-4353-91f4-2aab8d6f620a · outbound

This paper cites CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:52.696047Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5ec9cfe7-e44a-4c7b-960d-e82e807e978a · outbound

This paper cites AIvril: AI-Driven RTL Generation With Verification In-The-Loop.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs AIvril: AI-Driven RTL Generation With Verification In-The-Loop

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:52.803326Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 54c08f54-0618-4645-9b44-5f5316ac8170 · outbound

This paper cites Chipgpt: How far are we from natural language hardware design,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Chipgpt: How far are we from natural language hardware design,

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:57.671200Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 0917de2a-99c8-4b73-b86a-1594f0931044 · outbound

This paper cites Chip-chat: Chal- lenges and opportunities in conversational hardware design,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Chip-chat: Chal- lenges and opportunities in conversational hardware design,

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:57.658153Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation ad6362d0-0e6e-438e-baef-b3c23f524025 · outbound

This paper cites RTLRewriter: Methodologies for Large Models aided RTL Code Optimization.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs RTLRewriter: Methodologies for Large Models aided RTL Code Optimization

Reference 14

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:53.025192Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b6a75014-a137-4de7-943b-a74f75678c88 · outbound

This paper cites The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:53.116262Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f5f15599-5dfd-4a14-b191-493a1f51d95d · outbound

This paper cites Assertllm: Generating and evaluating hardware verification assertions from design specifications via multi-llms,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Assertllm: Generating and evaluating hardware verification assertions from design specifications via multi-llms,

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:53.161183Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0cc11326-5618-48db-82dc-f52468efd028 · outbound

This paper cites Gpt4aigchip: Towards next-generation ai accelerator design automation via large language models,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Gpt4aigchip: Towards next-generation ai accelerator design automation via large language models,

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:57.646026Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation d4114799-3e06-49f9-8a5e-8a2a1aaf4597 · outbound

This paper cites Chateda: A large language model powered autonomous agent for eda,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Chateda: A large language model powered autonomous agent for eda,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:57.635822Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 0b26ba63-56e8-4b94-95e7-886d6f1cb97a · outbound

This paper cites (Security) Assertions by Large Language Models.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs (Security) Assertions by Large Language Models

Reference 19

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:53.331516Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation b346fadf-9b17-4209-b2ca-a16f4d358f63 · outbound

This paper cites Rtlfixer: Automatically fixing rtl syntax errors with large language model,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Rtlfixer: Automatically fixing rtl syntax errors with large language model,

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:53.422372Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 77b36558-44ef-4312-80e1-243e94660b8f · outbound

This paper cites HDLdebugger: Streamlining HDL debugging with Large Language Models.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs HDLdebugger: Streamlining HDL debugging with Large Language Models

Reference 21

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:53.469553Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3c5f401a-c160-47eb-b04e-921338f3b4f0 · outbound

This paper cites On the viability of using llms for sw/hw co-design: An example in designing cim dnn accelerators,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs On the viability of using llms for sw/hw co-design: An example in designing cim dnn accelerators,

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:57.619516Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation f5d9dae5-a761-42cf-800c-74d209fe6d33 · outbound

This paper cites Openllm-rtl: Open dataset and benchmark for llm-aided design rtl generation,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Openllm-rtl: Open dataset and benchmark for llm-aided design rtl generation,

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:57.608764Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 74cf41ff-4a09-42b7-8aae-c6711260d67c · outbound

This paper cites Benchmarking large language models for auto- mated verilog rtl code generation,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Benchmarking large language models for auto- mated verilog rtl code generation,

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:57.595255Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 2ef22331-e5e6-4600-8290-0bd3f09c9679 · outbound

This paper cites Verilogeval: Evaluating large language models for verilog code generation,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Verilogeval: Evaluating large language models for verilog code generation,

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:53.739533Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4914d012-6f91-45e8-bfad-ab0f0c13345e · outbound

This paper cites Rtllm: An open-source benchmark for design rtl generation with large language model,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Rtllm: An open-source benchmark for design rtl generation with large language model,

Reference 26

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:53.804528Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 70bde7e2-afaf-4939-b64b-2e0c5d52b1d5 · outbound

This paper cites Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation

Reference 27

Resolution: verified exact; local_arxiv, observed 2026-08-06T15:19:55.561303Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e3599c72-cd69-4338-945a-42a057a0a49a · outbound

This paper cites Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 28

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:53.956140Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 69825b9b-10e1-41a3-a31a-afc7b65cc0fb · outbound

This paper cites RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:54.045629Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 164bc178-8406-4244-9429-7df1ac1ac970 · outbound

This paper cites SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model

Reference 30

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:54.115981Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ff7979a1-c519-46e2-a392-2e931d17a6bb · outbound

This paper cites Opencores: Open source ip-cores,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Opencores: Open source ip-cores,

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:57.569393Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation c62f06c9-9c33-43ac-96fc-b9f66e5ea6d7 · outbound

This paper cites Design sdc mmc controller,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Design sdc mmc controller,

Reference 32

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:57.437337Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e43d6337-039e-41c9-8b86-a617daf1885c · outbound

This paper cites Hummingbirdv2 e203 core and soc,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Hummingbirdv2 e203 core and soc,

Reference 33

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:57.280192Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation dc751b16-581a-426d-ae31-beb79bd0e116 · outbound

This paper cites SWE-bench: Can language models resolve real- world github issues?.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs SWE-bench: Can language models resolve real- world github issues?

Reference 34

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:57.180563Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 44754cb2-12c0-431e-856d-d520d8fc0518 · outbound

This paper cites Swe-agent: Agent-computer interfaces enable automated soft- ware engineering,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Swe-agent: Agent-computer interfaces enable automated soft- ware engineering,

Reference 35

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:57.061380Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e3463531-c245-4b87-86d5-3012d1a36851 · outbound

This paper cites Yosys open synthesis suite,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Yosys open synthesis suite,

Reference 36

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:54.506417Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation e9ed99ff-8f02-4ea6-92fd-ee7288543b8b · outbound

This paper cites Nangate freepdk45 generic open cell library,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Nangate freepdk45 generic open cell library,

Reference 37

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:56.973350Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 68b5ae03-b93a-4182-8732-ca788ceeb595 · outbound

This paper cites Jasper formal verification platform,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Jasper formal verification platform,

Reference 38

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:56.720897Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 38d239eb-a80e-4096-99ed-272106e1f5b4 · outbound

This paper cites Rouge: A package for automatic evaluation of summaries,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Rouge: A package for automatic evaluation of summaries,

Reference 39

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:54.717596Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5771d6d3-c8ba-4519-9fbb-591465b88489 · outbound

This paper cites The Llama 3 Herd of Models.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs The Llama 3 Herd of Models

Reference 40

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:54.786546Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3f831038-4107-4e2e-b847-862962dda043 · outbound

This paper cites DeepSeek-V3 Technical Report.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs DeepSeek-V3 Technical Report

Reference 41

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:54.833135Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c8b5081e-dfd5-4581-bb95-209f331f682f · outbound

This paper cites DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning

Reference 42

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:54.912345Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 11d5ca7b-4e07-4288-a55b-97fa15e54d5a · outbound

This paper cites DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligence.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligence

Reference 43

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:54.984124Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 562fdfe4-ca48-4bd7-9bad-1b5e0fbccdd0 · outbound

This paper cites Code with codeqwen1.5,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Code with codeqwen1.5,

Reference 44

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:56.466583Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation e6a1d32f-c693-4ffd-9adb-0db668c8b1a0 · outbound

This paper cites Verilogcoder: Autonomous verilog coding agents with graph-based planning and abstract syntax tree (ast)- based waveform tracing tool,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Verilogcoder: Autonomous verilog coding agents with graph-based planning and abstract syntax tree (ast)- based waveform tracing tool,

Reference 45

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:56.245402Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 69bf2f45-e1a5-4818-9561-54b6a2899556 · outbound

This paper cites Llama 2: Open Foundation and Fine-Tuned Chat Models.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Llama 2: Open Foundation and Fine-Tuned Chat Models

Reference 46

Resolution: unresolved; no resolver link, observed 2026-08-06T15:19:55.232675Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation fd8bec0f-44b0-480b-a69f-23a536e1145e · outbound

This paper cites Origen: Enhancing rtl code generation with code-to-code augmentation and self-reflection,.

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs Origen: Enhancing rtl code generation with code-to-code augmentation and self-reflection,

Reference 47

Resolution: verified fuzzy; raw_fallback, observed 2026-08-06T15:19:56.062369Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Pith citing papers

Observation 3d060298-2863-4600-a6f4-54045634113f · inbound

InCoder-32B-Thinking: Industrial Code World Model for Thinking cites this paper.

InCoder-32B-Thinking: Industrial Code World Model for Thinking RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

Reference 18

Resolution: verified exact; arxiv_id, observed 2026-05-13T18:58:08.723913Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 5854c317-683e-48a4-ba1b-fe007e1d0b52 · inbound

From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation cites this paper.

From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

Reference 15

Resolution: verified exact; arxiv_id, observed 2026-05-11T06:46:50.008880Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation facd681e-8744-40e9-af29-076ab749e297 · inbound

HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs cites this paper.

HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

Reference 35

Resolution: verified exact; arxiv_id, observed 2026-05-12T10:36:29.758607Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 0e0e407f-a3e4-4ec5-8518-7015254148b5 · inbound

Agentic Agile-V: From Vibe Coding to Verified Engineering in Software and Hardware Development cites this paper.

Agentic Agile-V: From Vibe Coding to Verified Engineering in Software and Hardware Development RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

Reference 30

Resolution: verified exact; arxiv_id, observed 2026-05-21T06:54:01.160526Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.

Observation 7597c667-dc5c-47ac-8d42-2d3e5f4c3269 · inbound

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation cites this paper.

ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-02T07:12:17.009828Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a2a04a83-78e9-4ae1-b346-d4bd5c8021d8 · inbound

Can AI Agents Really Complete RTL-to-GDS? Lessons from Benchmarking Tool-Interactive EDA Workflows cites this paper.

Can AI Agents Really Complete RTL-to-GDS? Lessons from Benchmarking Tool-Interactive EDA Workflows RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-01T17:46:03.778892Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.