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CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

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arxiv 2409.12993 v2 pith:YY44VUGW submitted 2024-09-19 cs.AR cs.CL

CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Mingjie Liu , Yun-Da Tsai , Wenfei Zhou , Haoxing Ren This is my paper
classification cs.AR cs.CL
keywords codedatamodelsnon-textualrepresentationsverilogcorrect-by-constructionfine-tuned
verification ladder T0 review T1 audit T2 compute T3 formal T4 reserved
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Despite the significant progress made in code generation with large language models, challenges persist, especially with hardware description languages such as Verilog. This paper first presents an analysis of fine-tuned LLMs on Verilog coding, with synthetic data from prior methods. We identify two main issues: difficulties in handling non-textual representations (Karnaugh maps, state-transition diagrams and waveforms) and significant variability during training with models randomly making "minor" mistakes. To address these limitations, we enhance data curation by creating correct-by-construction data targeting non-textual representations. Additionally, we introduce an automated framework that generates error reports from various model checkpoints and injects these errors into open-source code to create targeted code repair data. Our fine-tuned Starcoder2-15B outperforms prior state-of-the-art results by 3.8%, 10.9%, 6.6% for pass@1 on VerilogEval-Machine, VerilogEval-Human, and RTLLM.

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Cited by 5 Pith papers

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  4. VeriPilot: An LLM-Powered Verilog Debugging Framework

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