TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog

Armin Abdollahi; Massoud Pedram; Mehdi Kamal; Negin Ashrafi

arxiv: 2604.23602 · v1 · submitted 2026-04-26 · 💻 cs.AR · cs.LG

TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog

Armin Abdollahi , Negin Ashrafi , Mehdi Kamal , Massoud Pedram This is my paper

Pith reviewed 2026-05-08 05:15 UTC · model grok-4.3

classification 💻 cs.AR cs.LG

keywords Verilog timing predictionretrieval-augmented LLMpre-synthesis estimationworst negative slacktotal negative slackRTL designhardware synthesisEDA acceleration

0 comments

The pith

A retrieval-augmented LLM predicts post-synthesis timing slacks directly from Verilog modules.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper introduces a two-stage method to estimate worst negative slack and total negative slack for hardware designs written in Verilog without executing synthesis tools. The first stage uses a fine-tuned LLM to generate path-level timing values that are reduced to compact structural features such as gate counts and critical-path depth. The second stage retrieves similar labeled examples and applies a learned adjustment vector inside an LLM regressor to produce the final slack predictions. If accurate across designs and manufacturing settings, this removes a major bottleneck in early RTL exploration by letting engineers test changes in minutes instead of hours.

Core claim

TimingLLM is a two-stage retrieval-augmented LLM pipeline that estimates worst negative slack and total negative slack directly from Verilog. Stage 1 fine-tunes an LLM to act as a compact post-synthesis timing oracle that outputs path-level arrival and required times, which are summarized into lightweight structural-timing cues. Stage 2 employs an LLM-based regressor that predicts the slacks and applies a learned diagonal steering vector, computed from the k nearest timing-labeled modules in a disjoint retrieval bank, at the last transformer block.

What carries the argument

The two-stage retrieval-augmented pipeline in which the first LLM extracts lightweight structural-timing cues and the second LLM regressor steers its output with a vector derived from nearest-neighbor retrieval.

If this is right

On VerilogEval the method attains R_WNS of 0.91 with 12 percent MAPE and R_TNS of 0.97 with 16 percent MAPE.
Runtime is 1.3 to 1.6 times faster than prior methods.
After initial training the model adapts to new technology libraries and PVT corners by refitting only the small regression head on 1000 labeled modules per setting while still outperforming baselines.
A new 60k-module Verilog corpus with synthesis reports is created and will be released to support further work.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

Designers could explore substantially more RTL variants within a fixed time budget because each timing query no longer requires a full synthesis run.
The same retrieval-plus-steering pattern may apply to other pre-synthesis predictions such as power or area if suitable cue extractors and labeled banks are built.
Success depends on maintaining a sufficiently diverse and up-to-date retrieval bank, which implies that organizations will need shared or curated libraries of synthesized modules.

Load-bearing premise

Lightweight structural cues extracted by the first-stage LLM together with retrieval from a bank of labeled modules contain enough information to predict timing slacks accurately for previously unseen Verilog modules and different technology nodes.

What would settle it

Evaluating the full pipeline on a set of Verilog modules synthesized under a new technology library and PVT corner without refitting the regression head and observing whether the correlation coefficients for WNS and TNS drop below 0.7.

Figures

Figures reproduced from arXiv: 2604.23602 by Armin Abdollahi, Massoud Pedram, Mehdi Kamal, Negin Ashrafi.

**Figure 1.** Figure 1: Dataset curation and stratified selection pipeline view at source ↗

**Figure 2.** Figure 2: Two-stage TimingLLM: fingerprint generation and retrieval-steered timing prediction. view at source ↗

**Figure 3.** Figure 3: Top-2 setup paths: STA vs. Stage-1 LLM agreement view at source ↗

**Figure 4.** Figure 4: Qualitative retrieval for feature-space steering view at source ↗

**Figure 5.** Figure 5: The details of employed dataset The distribution of synthesized gate counts across 60k-modules corpus exhibits a pronounced concentration in small-scale designs so 33% of modules contain between 1 and 10 gates, and 31% span 10–50 gates, together accounting for two-thirds of the dataset. Modules with moderate complexity (50–100 gates) comprise 14%, while designs with 100–200 gates and 200+ gates each repre… view at source ↗

read the original abstract

Early, tool-free prediction of post-synthesis timing remains a key obstacle to rapid RTL iteration. We introduce TimingLLM, a two-stage retrieval-augmented LLM pipeline that estimates worst negative slack (WNS) and total negative slack (TNS) directly from Verilog. Stage 1 is a fine-tuned LLM that acts as a compact post-synthesis timing oracle, producing path-level arrivals/required times that are summarized into lightweight structural-timing cues (e.g., bag-of-gates counts, critical-path depth, gate-type patterns). Stage 2 is an LLM-based regressor that predicts WNS/TNS and applies a learned diagonal steering vector at the last transformer block, computed from the k nearest timing-labeled modules in a disjoint retrieval bank. On VerilogEval, TimingLLM attains R_WNS = 0.91 (MAPE 12%) and R_TNS=0.97 (MAPE 16%) while running 1.3-1.6 times faster than prior methods. Training uses a new 60k-module Verilog corpus with synthesis reports, which we will release. After training once, TimingLLM can be adapted to new technology libraries and PVT corners by refitting only a small regression head on 1000 labeled modules per setting, consistently outperforming state-of-the-art baselines.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

TimingLLM shows a concrete two-stage LLM-plus-retrieval method for Verilog timing prediction that reports usable accuracy, but the cross-node adaptation story rests on an assumption that needs checking in the full text.

read the letter

The paper's main contribution is a two-stage pipeline where a fine-tuned LLM first turns Verilog into path summaries and lightweight structural cues like gate counts and critical-path depth, then a second stage uses k-nearest neighbors from a disjoint bank to compute a steering vector that adjusts the final WNS and TNS predictions. That retrieval step with the diagonal steering vector at the transformer block is the piece that has not shown up in earlier pre-synthesis timing work I have seen. They also plan to release the 60k-module corpus with synthesis reports, which would be useful on its own. The reported R values of 0.91 for WNS and 0.97 for TNS on VerilogEval, along with the speed-up over prior methods, are the kind of numbers that could matter for people who need quick feedback during RTL exploration. The adaptation claim, where you retrain only a small head on 1000 new modules for a different library or corner, is the part that makes the method sound practical rather than one-off. If the full evaluation confirms clean splits and no leakage between the retrieval bank and test modules, this setup could shorten some design loops. The soft spot is exactly the one the stress-test note flags. Structural cues alone do not observe cell delays, drive strengths, or wire RC, which are library- and corner-specific. If the first-stage LLM was trained on one node's reports, its summaries may carry biases that a small refit head cannot fully correct when the retrieval bank is also from the original node. The abstract gives no numbers on how the bank was constructed or whether the test modules truly sit outside the training distribution across nodes. Without those details the 12-16% MAPE figures look encouraging but not yet conclusive for the cross-technology use case. This work is for EDA researchers and tool builders who already follow ML-for-hardware papers. It engages the right prior art on timing prediction and retrieval-augmented models, and the method is described clearly enough to reproduce if the dataset arrives. I would send it to peer review because the task is real, the architecture is specific, and the quantitative claims are testable once the evaluation protocol is laid out.

Referee Report

2 major / 1 minor

Summary. The paper introduces TimingLLM, a two-stage retrieval-augmented LLM framework for pre-synthesis prediction of worst negative slack (WNS) and total negative slack (TNS) directly from Verilog. Stage 1 fine-tunes an LLM to act as a timing oracle that extracts and summarizes lightweight structural cues (bag-of-gates counts, critical-path depth, gate-type patterns). Stage 2 performs k-NN retrieval over a disjoint labeled bank and uses an LLM regressor with a learned diagonal steering vector to output WNS/TNS. On VerilogEval the method reports R_WNS=0.91 (MAPE 12%) and R_TNS=0.97 (MAPE 16%), runs 1.3-1.6x faster than prior work, and claims that after one-time training it can be adapted to new technology libraries/PVT corners by refitting only the regression head on 1000 labeled modules. A 60k-module Verilog corpus with synthesis reports will be released.

Significance. If the reported correlations hold under proper leakage controls and the cross-node adaptation claim is validated, the work could meaningfully accelerate RTL iteration by providing fast, tool-free timing estimates. The two-stage retrieval-augmented design and the planned dataset release are concrete strengths that would support follow-on research in ML-assisted EDA.

major comments (2)

Abstract: the central performance numbers (R_WNS=0.91, MAPE 12%; R_TNS=0.97, MAPE 16%) and the adaptability claim are presented without any information on train-test split ratios, retrieval-bank construction details, baseline re-implementations, or explicit checks for data leakage between the 60k training corpus and VerilogEval. These omissions directly affect the soundness of the quantitative support for the main claims.
Adaptation section (presumably §5 or §6): the assertion that refitting only the small regression head on 1000 new modules suffices for new technology libraries and PVT corners rests on the untested premise that Stage-1 structural cues remain sufficiently informative once cell delays, drive strengths, and wire RC change. No cross-node or cross-corner hold-out experiments are described that would confirm the cues transfer without retraining the LLM or updating the retrieval bank.

minor comments (1)

Abstract: the speed-up factor (1.3-1.6x) is stated without naming the prior methods or the measurement conditions (e.g., hardware, synthesis tool version), reducing clarity of the efficiency claim.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback, which helps clarify the presentation of our evaluation protocol and the scope of our adaptation claims. We address each major comment below and indicate planned revisions to the manuscript.

read point-by-point responses

Referee: Abstract: the central performance numbers (R_WNS=0.91, MAPE 12%; R_TNS=0.97, MAPE 16%) and the adaptability claim are presented without any information on train-test split ratios, retrieval-bank construction details, baseline re-implementations, or explicit checks for data leakage between the 60k training corpus and VerilogEval. These omissions directly affect the soundness of the quantitative support for the main claims.

Authors: We agree that the abstract omits these details due to space constraints. The full experimental protocol—including an 80/20 train-test split on the 60k-module corpus, construction of a disjoint retrieval bank from the training portion only, baseline re-implementations using identical splits, and explicit leakage-prevention steps (no overlap between retrieval bank and test modules)—is described in Sections 4 and 5. We will revise the abstract to include a concise statement summarizing the split ratios, disjoint bank construction, and leakage controls. revision: yes
Referee: Adaptation section (presumably §5 or §6): the assertion that refitting only the small regression head on 1000 new modules suffices for new technology libraries and PVT corners rests on the untested premise that Stage-1 structural cues remain sufficiently informative once cell delays, drive strengths, and wire RC change. No cross-node or cross-corner hold-out experiments are described that would confirm the cues transfer without retraining the LLM or updating the retrieval bank.

Authors: The Stage-1 cues (bag-of-gates counts, critical-path depth, gate-type patterns) are deliberately chosen as RTL-level structural descriptors that do not depend on absolute cell delays or wire RC. The retrieval bank and regression head are the only components refit per technology/PVT. We acknowledge that the current manuscript does not report explicit cross-node or cross-corner hold-out experiments validating cue transfer without LLM retraining. We will revise the adaptation section to explicitly state this design assumption, add a limitations paragraph, and include preliminary adaptation results on a second technology node if additional synthesis data can be obtained in time for the revision. revision: partial

Circularity Check

0 steps flagged

No circularity: predictions evaluated on held-out modules with disjoint retrieval bank

full rationale

The paper's pipeline extracts structural cues via a fine-tuned LLM (Stage 1) and uses k-NN retrieval from a disjoint labeled bank plus a regression head (Stage 2) to predict WNS/TNS. Reported metrics (R_WNS=0.91, R_TNS=0.97) are on held-out VerilogEval modules; adaptation to new libraries/PVT refits only the head on 1000 new modules. No derivation step reduces by construction to reuse of fitted quantities on the test set, no self-definitional loops, and no load-bearing self-citations. The chain is empirically grounded rather than tautological.

Axiom & Free-Parameter Ledger

3 free parameters · 2 axioms · 0 invented entities

The framework depends on a large number of data-fitted parameters inside the LLMs and regression head plus domain assumptions about what structural summaries preserve timing information; no new physical entities are introduced.

free parameters (3)

stage-1 LLM fine-tuning weights
The first LLM is fine-tuned on the 60k timing-labeled modules to produce path-level arrival and required times.
stage-2 regression head weights
The final regressor is trained to map summarized cues plus retrieval features to WNS and TNS.
diagonal steering vector
Learned from the k nearest modules in the disjoint retrieval bank and applied at the last transformer block.

axioms (2)

domain assumption Path-level timing estimates can be losslessly summarized into bag-of-gates counts, critical-path depth, and gate-type patterns while retaining predictive value for overall slack.
This premise justifies the compression step between stage 1 and stage 2.
domain assumption Modules retrieved by structural similarity from a pre-labeled bank supply useful guidance for timing prediction on new designs.
This underpins the retrieval-augmented component of stage 2.

pith-pipeline@v0.9.0 · 5556 in / 1714 out tokens · 85129 ms · 2026-05-08T05:15:04.812771+00:00 · methodology

discussion (0)

Reference graph

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