RTL-BenchLS supplies a large-scale formally verified benchmark and three novel tasks that expose low performance of frontier LLMs on realistic RTL reasoning and generation.
Origen: Enhancing rtl code generation with code-to-code augmentation and self-reflection
7 Pith papers cite this work. Polarity classification is still indexing.
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2026 7representative citing papers
TimingLLM uses a fine-tuned LLM to generate structural timing cues from Verilog followed by a retrieval-augmented regressor with a learned steering vector to predict WNS and TNS with R values of 0.91 and 0.97.
Verilog-Evolve uses executable feedback from simulation, synthesis, timing, and GEMM metrics to refine LLM-generated Verilog and evolves skills across tasks, improving functional success and downstream hardware quality on VerilogEval and mixed-precision GEMM benchmarks.
RTL-BenchMT is an agent-assisted framework for dynamically maintaining RTL generation benchmarks by fixing flaws and reducing overfitting in LLM-based EDA applications.
ROSUM-MCTS applies MCTS-inspired hierarchical candidate expansion and a composite reward balancing functional correctness, local content adequacy, and fluency to improve LLM summaries of VHDL and Verilog code, outperforming baselines on eval datasets.
VerilogCL applies contrastive learning with minimal-error data pairs and a proactive screening module to improve compilation success and functional correctness of 7B LLM-generated Verilog over open-source and commercial baselines on VerilogEval and RTLLM benchmarks.
HORIZON applies repository-level self-evolution to hardware design artifacts and reports 100% completion on ChipBench, RTLLM, Verilog-Eval, and nine CVDP categories using a hands-free agent loop.
citing papers explorer
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RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
RTL-BenchLS supplies a large-scale formally verified benchmark and three novel tasks that expose low performance of frontier LLMs on realistic RTL reasoning and generation.
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TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog
TimingLLM uses a fine-tuned LLM to generate structural timing cues from Verilog followed by a retrieval-augmented regressor with a learned steering vector to predict WNS and TNS with R values of 0.91 and 0.97.
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Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation
Verilog-Evolve uses executable feedback from simulation, synthesis, timing, and GEMM metrics to refine LLM-generated Verilog and evolves skills across tasks, improving functional success and downstream hardware quality on VerilogEval and mixed-precision GEMM benchmarks.
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RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision
RTL-BenchMT is an agent-assisted framework for dynamically maintaining RTL generation benchmarks by fixing flaws and reducing overfitting in LLM-based EDA applications.
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ROSUM-MCTS: Monte Carlo Tree Search-Inspired HDL Code Summarization with Structural Rewards
ROSUM-MCTS applies MCTS-inspired hierarchical candidate expansion and a composite reward balancing functional correctness, local content adequacy, and fluency to improve LLM summaries of VHDL and Verilog code, outperforming baselines on eval datasets.
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VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation
VerilogCL applies contrastive learning with minimal-error data pairs and a proactive screening module to improve compilation success and functional correctness of 7B LLM-generated Verilog over open-source and commercial baselines on VerilogEval and RTLLM benchmarks.
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Agentic Hardware Design as Repository-Level Code Evolution
HORIZON applies repository-level self-evolution to hardware design artifacts and reports 100% completion on ChipBench, RTLLM, Verilog-Eval, and nine CVDP categories using a hands-free agent loop.