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arxiv: 2605.22113 · v1 · pith:ESYJ77FJnew · submitted 2026-05-21 · 💻 cs.CR

QT-PUF: Quantum Tunneling Leakage Based PUF for Implantable IoMT Devices

Yueqi Ma , Vivek Mohan , Chip-Hong Chang , Emmanuel M. Drakakis This is my paper

Pith reviewed 2026-05-22 05:30 UTC · model grok-4.3

classification 💻 cs.CR
keywords physical unclonable functiongate tunneling leakageIoMTimplantable devicesCMOSlow powerPUFhardware security
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0 comments X

The pith

Gate-tunneling leakage variations in standard 65 nm CMOS generate unclonable digital responses suitable for ultralow-power implantable medical devices.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper presents QT-PUF, a physical unclonable function that turns process-induced differences in quantum gate leakage currents into unique digital bits for device authentication. It targets the security requirements of Internet of Medical Things implants by avoiding the power overhead and instability of conventional memory-based or oscillator-based PUFs. A sympathetic reader would care because successful deployment could let implanted sensors and monitors produce cryptographic material on demand while staying within the narrow voltage, temperature, and energy budgets of real medical hardware.

Core claim

QT-PUF exploits picoampere-level gate-tunneling leakage variations caused by manufacturing differences in 65 nm CMOS transistors and converts them into digital responses through a differential readout circuit that includes a pseudo-resistor current-to-voltage frontend. Simulations show this approach delivers an entropy of 0.9999998, a fractional Hamming distance of 0.5001, and an average power of 96.04 nW per bit at 1.2 V and 35°C, while keeping the bit error rate below 0.000163 across 1.0–1.3 V and 10–70°C.

What carries the argument

Differential readout circuit with pseudo-resistor I-to-V frontend that converts picoampere-level gate-tunneling leakage variations into stable digital responses under static bias.

Load-bearing premise

Picoampere-level gate-tunneling leakage variations from process differences in 65 nm CMOS can be turned into consistent digital outputs by the proposed readout circuit in actual fabricated chips.

What would settle it

Fabricating QT-PUF instances in 65 nm CMOS and directly measuring entropy, fractional Hamming distance, and bit error rate across 0.9–1.3 V and 0–100°C would test whether the simulated performance holds in silicon.

Figures

Figures reproduced from arXiv: 2605.22113 by Chip-Hong Chang, Emmanuel M. Drakakis, Vivek Mohan, Yueqi Ma.

Figure 1
Figure 1. Figure 1: Schematic of QT-PUF system architecture composed of: (a-1) cell selection logic (CS and RS are the column and row select signals) and (a-2) [PITH_FULL_IMAGE:figures/full_fig_p002_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Schematic illustrating the five gate leakage components in NMOS [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: (a) Distribution of differential leakage currents: the mean value is [PITH_FULL_IMAGE:figures/full_fig_p003_4.png] view at source ↗
Figure 5
Figure 5. Figure 5: PUF waveforms of 1500 samples obtained from simulation with [PITH_FULL_IMAGE:figures/full_fig_p003_5.png] view at source ↗
Figure 6
Figure 6. Figure 6: Logical speckle figure of measured PUF output from 20 arrays: [PITH_FULL_IMAGE:figures/full_fig_p003_6.png] view at source ↗
Figure 7
Figure 7. Figure 7: Measured BER of the proposed PUF under (a) temperature variation [PITH_FULL_IMAGE:figures/full_fig_p004_7.png] view at source ↗
read the original abstract

The Internet of Medical Things (IoMT) marks a shift toward decentralized healthcare, enabling continuous monitoring and personalized care through connected wearable and implantable devices. However, ensuring the trust and integrity of these devices themselves remains a major challenge, as physical compromise or counterfeiting can directly endanger patient safety, privacy, and data integrity. This work presents QT-PUF, a gate-tunneling-leakage-based physical unclonable function (PUF) that leverages quantum-mechanical gate leakage resulting from process-induced variations in standard CMOS devices. A differential readout circuit with a pseudo-resistor I-to-V frontend is proposed to convert the picoampere-level leakage variations into digital responses. Unlike existing PUFs such as those based on memory, ring oscillators, or arbiters, which are less suitable for ultralow-power IoMT devices (due to additional circuitry, power overhead, or poor stability), QT-PUF requires no external excitation or stabilization and operates under static bias. Simulation-based measurements for a $\mathbf{65}$~nm CMOS process demonstrate an entropy of $\mathbf{0.9999998}$, an FHD of $\mathbf{0.5001}$, and an average power (energy) consumption of $\mathbf{96.04}$~nW/bit ($\mathbf{19.21}$~fJ/bit, respectively) at $\mathbf{1.2\,V}$ and $\mathbf{35\,^{\circ}C}$ for the proposed PUF. It operates reliably across $\mathbf{0.9}\text{--}\mathbf{1.3}$~V and $\mathbf{0}\text{--}\mathbf{100\,^{\circ}C}$ with an average BER below $\mathbf{0.000163}$ across $\mathbf{1.0}\text{--}\mathbf{1.3}$~V and $\mathbf{10}\text{--}\mathbf{70\,^{\circ}C}$ within the operating conditions of typical implantable devices.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 2 minor

Summary. The paper proposes QT-PUF, a gate-tunneling-leakage-based PUF for implantable IoMT devices that exploits process-induced quantum-mechanical variations in standard 65 nm CMOS transistors. A differential readout circuit incorporating a pseudo-resistor I-to-V frontend is introduced to convert picoampere-level leakage currents into stable digital responses without external excitation. Simulation results are presented showing an entropy of 0.9999998, fractional Hamming distance of 0.5001, average power of 96.04 nW/bit (19.21 fJ/bit) at 1.2 V and 35°C, and BER below 0.000163 across 1.0–1.3 V and 10–70°C, with reliable operation over 0.9–1.3 V and 0–100°C.

Significance. If the simulation results translate to fabricated silicon, QT-PUF would represent a meaningful advance for ultralow-power hardware security in implantable medical devices by achieving high uniqueness and reliability with minimal power overhead and no additional stabilization circuitry. The reported energy efficiency and temperature/voltage tolerance are particularly relevant for battery-constrained IoMT applications. The simulation-only nature of the evaluation, however, substantially reduces the immediate significance of the claims.

major comments (2)
  1. [Abstract and Simulation Results] Abstract and all simulation sections: Every quantitative claim (entropy 0.9999998, FHD 0.5001, power 96.04 nW/bit, BER < 0.000163) is obtained exclusively from 65 nm CMOS simulations. No silicon measurements, tape-out details, or error analysis from fabricated devices are provided. This directly undermines the central assertion that picoampere-level gate-tunneling leakage variations can be stably mapped to reliable digital bits by the proposed differential pseudo-resistor frontend under real implantable-device conditions.
  2. [Proposed QT-PUF Circuit and Simulation Methodology] Circuit description and simulation setup: The I-to-V conversion and subsequent digital readout assume ideal oxide-thickness variation, subthreshold leakage models, and perfect pseudo-resistor linearity. Real 65 nm fabrication introduces additional mismatch mechanisms (oxide traps, line-edge roughness, packaging stress, and supply/temperature gradients) that are not modeled; these could alter the leakage distribution or add readout noise sufficient to degrade the reported BER and entropy once the circuit is realized in silicon.
minor comments (2)
  1. [Abstract] The abstract and introduction would benefit from an explicit statement of the simulation tool, transistor models (e.g., BSIM), and number of Monte-Carlo runs used to generate the reported statistics.
  2. [Figures] Figure captions and axis labels for leakage-current distributions and BER-vs-temperature plots should include the exact simulation conditions (voltage, temperature, number of instances) for reproducibility.

Simulated Author's Rebuttal

2 responses · 1 unresolved

We thank the referee for the detailed review and constructive comments on our manuscript. We address each major comment below, acknowledging the simulation-based evaluation while clarifying assumptions and limitations in the revised version.

read point-by-point responses

  1. Referee: [Abstract and Simulation Results] Abstract and all simulation sections: Every quantitative claim (entropy 0.9999998, FHD 0.5001, power 96.04 nW/bit, BER < 0.000163) is obtained exclusively from 65 nm CMOS simulations. No silicon measurements, tape-out details, or error analysis from fabricated devices are provided. This directly undermines the central assertion that picoampere-level gate-tunneling leakage variations can be stably mapped to reliable digital bits by the proposed differential pseudo-resistor frontend under real implantable-device conditions.

    Authors: We agree that all quantitative results are derived from simulations in a commercial 65 nm CMOS PDK. The manuscript presents a circuit-level proposal for exploiting gate-tunneling leakage as a PUF source, with performance evaluated via Monte Carlo analysis. We have revised the abstract, results sections, and conclusion to explicitly qualify all metrics as simulation-based and to moderate claims about real-device behavior. A new 'Limitations and Future Directions' subsection has been added that discusses the translation from simulation to silicon, including the absence of fabricated-device data at this stage. This addresses the concern without overstating the current evidence. revision: partial

  2. Referee: [Proposed QT-PUF Circuit and Simulation Methodology] Circuit description and simulation setup: The I-to-V conversion and subsequent digital readout assume ideal oxide-thickness variation, subthreshold leakage models, and perfect pseudo-resistor linearity. Real 65 nm fabrication introduces additional mismatch mechanisms (oxide traps, line-edge roughness, packaging stress, and supply/temperature gradients) that are not modeled; these could alter the leakage distribution or add readout noise sufficient to degrade the reported BER and entropy once the circuit is realized in silicon.

    Authors: The referee correctly notes that our simulations rely on the statistical models supplied in the 65 nm foundry PDK, which capture oxide-thickness variation and related tunneling effects. Additional real-world mechanisms such as oxide traps, extra line-edge roughness components, packaging stress, and certain gradient-induced noise are not explicitly included beyond the PDK statistics. In the revised manuscript we have expanded the 'Simulation Methodology' section to describe the exact models and corner cases used, and we have inserted a dedicated paragraph in the limitations discussion that enumerates these unmodeled effects and their possible influence on BER and entropy. This provides a more transparent account of the simulation assumptions. revision: partial

standing simulated objections not resolved
  • Absence of silicon measurements or fabricated-device validation, as the work is currently limited to simulation results.

Circularity Check

0 steps flagged

No circularity in derivation chain; results are direct simulation outputs

full rationale

The paper presents a circuit design for QT-PUF based on gate-tunneling leakage variations in 65 nm CMOS, with a differential readout circuit using pseudo-resistor I-to-V conversion. All reported metrics (entropy 0.9999998, FHD 0.5001, power 96.04 nW/bit, BER <0.000163) are explicitly stated as outputs from simulations under defined voltage and temperature conditions. No equations, first-principles derivations, or predictions appear that reduce by construction to fitted parameters, self-definitions, or self-citation chains. The central claims rest on simulation results rather than any load-bearing mathematical reduction or ansatz smuggling, rendering the presentation self-contained against external benchmarks.

Axiom & Free-Parameter Ledger

0 free parameters · 1 axioms · 0 invented entities

Abstract-only review limits visibility into parameters or assumptions; the core premise relies on domain knowledge of CMOS leakage behavior.

axioms (1)
  • domain assumption Process-induced variations produce measurable and usable differences in gate-tunneling leakage currents in standard CMOS transistors.
    This underpins the uniqueness and reliability of the PUF responses.

pith-pipeline@v0.9.0 · 5911 in / 1428 out tokens · 59206 ms · 2026-05-22T05:30:38.370618+00:00 · methodology

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