Wafer2Spike: Spiking Neural Network for Wafer Map Pattern Classification

Abhishek Mishra; Anup Das; Anush Lingamoorthy; Nagarajan Kandasamy; Suman Kumar

REVIEW 4 major objections 5 minor 10 references

Wafer2Spike: Spiking Neural Network for Wafer Map Pattern Classification

T0 review · 4 major / 5 minor · reviewed 2026-08-12 · deepseek-v4-flash

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Pith's one-line read A directly trained spiking neural network, Wafer2Spike, is reported to classify wafer map defect patterns with 98% average accuracy on the WM-811k benchmark, outperforming the deep neural network baselines it is compared with.

desk verdict Wafer2Spike is a clean transfer of established surrogate-gradient SNN training to wafer map defect classification with new per-class results, but the 98% headline and 22x energy savings are not yet supported as stated. read the letter →

arxiv 2411.19422 v1 pith:F2BOH5ZV submitted 2024-11-29 cs.NE

Abhishek Mishra , Suman Kumar , Anush Lingamoorthy , Anup Das , Nagarajan Kandasamy This is my paper · ORCID

classification cs.NE

keywords wafermapclassificationspikingneuralnetworksWM-811kdatasetdefectpatternleakyintegrate-and-fireneuronsurrogategradienttrainingdataaugmentationenergy-efficientinference

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper reports Wafer2Spike, a spiking neural network (SNN) architecture for classifying defect patterns on semiconductor wafer maps. The authors claim that, trained directly from labeled wafer maps in the WM-811k benchmark, Wafer2Spike reaches an average classification accuracy of 98%, higher than the CNN, SVM, and other neural baselines they compare against. They also claim it is more accurate on underrepresented defect classes, such as Scratch, thanks to a geometric data-augmentation procedure for minority classes. The point is to show that an SNN is not just an energy-efficient alternative to DNNs but can also beat them on this manufacturing-inspection task.

What carries the argument

The central object is the leaky integrate-and-fire (LIF) neuron with learnable current-decay and voltage-decay parameters, embedded in a convolutional spike encoder followed by spiking convolutional layers. The encoder converts static pixel intensities into timed spike trains, and the LIF dynamics propagate these spikes through space and time. Training is driven by a spatio-temporal backpropagation rule with a surrogate gradient, and minority-class examples are augmented by geometric transformations to address class imbalance.

What would settle it

Retrain every baseline on the exact same train/validation/test splits and the identical augmented training set used for Wafer2Spike, and compare per-class accuracy: if a baseline then matches or exceeds 98% on the same splits, the claimed superiority of the SNN would not be confirmed.

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Extended reading notes

Core claim

Wafer2Spike is a direct-training SNN that turns each 36x36 wafer map into spike trains via a trainable convolutional spike-encoding layer, then processes them through up to four spiking convolutional layers and a spiking fully-connected layer, ending in a non-spiking classifier. Its LIF neurons treat the synaptic-current decay and voltage-decay factors as learned parameters, and training uses spatio-temporal backpropagation with surrogate gradients. The reported result is 98% average accuracy on WM-811k, with the four-convolutional-layer variant (Wafer2Spike4C) surpassing the two- and three-layer versions and every baseline in most per-class comparisons. The paper also estimates inference energy from FLOPs and synaptic operations, reporting that the small variant is about 12.5x and 22x more energy-efficient than a CNN and a lightweight neural network baseline, respectively.

Load-bearing premise

The comparison with prior methods assumes that the random train/test splits and the geometric augmentation used for Wafer2Spike do not give it an advantage over the baselines, whose reported accuracies come from their own splits and preprocessing.

Editorial extensions

If this is right

A directly trained SNN can reach state-of-the-art accuracy on wafer map defect classification, not just approximate DNN accuracy.
The reported 98% average accuracy suggests the architecture and augmentation together handle class imbalance well, particularly for rare defect patterns.
The energy model indicates that Wafer2Spike's inference cost, measured in synaptic operations, can be up to roughly 22 times lower than a CNN baseline at comparable accuracy.
The learnable decay factors in LIF neurons are trainable parameters that help the spiking network adapt to the static image input, a method that could extend to other image classification domains.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The reported energy savings count only the network's inference operations, not the overhead of generating spike trains from the input or the energy cost of the encoding layer itself; including those could reduce the margin over baselines.
Because the paper does not fix identical split indices across methods, the accuracy gap versus prior work may partly reflect evaluation setup; a shared benchmark protocol would settle this.
The same trainable spike-encoding plus LIF recipe could be applied to other semiconductor inspection images, such as die-level defect maps, where rare classes are also the ones that matter.
The geometric augmentation for minority classes is described but not quantified separately; an ablation isolating augmentation from architecture would show how much of the 98% comes from each.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Wafer2Spike applies standard surrogate-gradient-trained spiking CNNs (following Wu et al.) to wafer map defect classification on WM-811k. What's new is the application, not the method: the paper reports per-class accuracies for rare patterns like Scratch and Near-Full, where several DNN baselines are weak, and it shows a sensible ablation over two, three, and four spiking convolutional layers. The code is released, which is a plus.

The soft spots are real and land on the central claims. Table I's comparison against [5]-[8] is uncontrolled: the footnote says samples are randomly selected per split, there is no evidence the same split indices were used for all methods, and Wafer2Spike's geometric augmentation is applied only to its own training data. The 98% figure is also the 8:2 split only; the 7:3 and 6:1:3 splits give 97%. No variance across runs is reported, which matters for rare classes with tiny sample counts. The abstract's "average accuracy of 98%" is therefore not established.

There's also a concrete red flag in Table I: the row reporting F1 scores for Wafer2Spike 4C lists values like 199%, 194%, and 155%. Those are impossible as percentages. I assume a formatting or typo problem (possibly missing decimal points), but it undermines confidence in the table's accuracy and needs fixing before review.

The energy comparison in Table II is a theoretical estimate, not a measurement, and it depends on unreported parameters: the simulation time step T and the firing rate gamma for each layer. The claimed 22x savings are for the smallest 2C model against DMC1, not for the 98% 4C model, which shows only 1.75x to 3x savings against the DNN baselines. So the efficiency headline oversells as well.

None of this is fatal to the paper's core idea. The SNN recipe is standard, the application is legitimate, and the rare-class improvements are plausible. But the evaluation needs shared splits, multiple runs with standard deviations, fully specified energy parameters, and corrected table entries. This is a fixable rigor gap, not a conceptual one.

A serious editor should send this to review. It is a short paper with a new benchmark result and released code; with revision it could be a solid empirical contribution. I would bring it to a reading group only if someone in the group works on SNN applications or wafer defect analysis. I would not cite it in my own work yet.

Referee Report

4 major / 5 minor

Summary. The paper introduces Wafer2Spike, a directly trained spiking neural network for classifying wafer map defect patterns in the WM-811k dataset. The architecture uses a convolutional spike encoding layer, up to four spiking convolutional layers, a spiking fully connected layer, and a non-spiking output layer, trained with surrogate-gradient spatio-temporal backpropagation. The authors report an average classification accuracy of 98% for the four-convolutional-layer configuration and claim that Wafer2Spike outperforms existing DNN- and ML-based methods on most defect classes while being up to 22x more energy-efficient than DNN baselines, based on a FLOP/SOP energy model.

Significance. If the performance claims are substantiated, the paper would make a useful contribution: it demonstrates that a directly trained SNN can reach state-of-the-art accuracy on a real industrial benchmark while offering potential energy advantages, and the authors have open-sourced the implementation. The energy model is transparent in form, and the architectural ablations (2C/3C/4C) are a reasonable design study. However, the central accuracy claim is currently not established because the comparison with baseline methods is uncontrolled, the reported numbers lack variance estimates, and the headline figure is the best-case split rather than a robust average. The energy-efficiency claim is also conditional on parameters that are not reported. These issues are correctable with additional experiments and reporting.

major comments (4)

[Section IV-B, Table I] The comparison with baselines [5]-[8] is uncontrolled. The footnote to Table I states that samples are randomly selected to populate each set, but there is no evidence that identical split indices were used for Wafer2Spike and for the baseline results taken from prior papers. Section IV-A further describes a geometric data-augmentation procedure for minority classes that is not reported for the baselines. Because the test sets and training data may differ, the observed accuracy gaps cannot be attributed to the model rather than the evaluation setup. Please report the exact split indices or, ideally, rerun the baselines under the same splits and augmentation protocol, and report accuracy averaged over multiple runs with standard deviations.
[Table I, 8:1:1 rows] The comparison mixes different performance metrics. For the 8:1:1 split, the footnote indicates that the numbers are recall (R) and F1 scores, and indeed the P2-Net row shows 'R99% R93% ...' while the Wafer2Spike rows show 'R98% R98% ...'. Yet the 'Avg. Accuracy' column is used for all rows as if it were accuracy. Claiming that Wafer2Spike 'outperforms' P2-Net on the basis of accuracy in one column and recall/F1 in others is not valid. All rows should be compared on the same metric, and the metric should be clearly defined.
[Abstract and Section IV-B] The abstract states that Wafer2Spike achieves an average classification accuracy of 98% on WM-811k, but Table I shows that Wafer2Spike4C achieves 98% only under the 8:2 split, while it achieves 97% under both the 7:3 and 6:1:3 splits. The headline number is therefore the best case, not an average over split protocols. Please either report the averaged accuracy over all split ratios or qualify the abstract to reflect which configuration and split yield 98%.
[Section IV-C, Eq. (SOPs)] The energy estimates in Table II depend on the simulation time steps T and the firing rate gamma via SOPs(L) = T * gamma * FLOPs(L), but T and gamma are not reported for any of the models. Without these values, the SOP counts and the resulting power numbers cannot be reproduced or verified. Additionally, the energy-saving factor of up to 22x follows directly from assuming 77 fJ per SOP versus 12.5 pJ per FLOP; the sensitivity of the conclusion to these per-operation constants should be discussed, and the theoretical nature of the estimate should be stated in the main text.

minor comments (5)

[Section III, Eq. (2)] The notation for the input volume IW and the kernel Wd_ci is not defined in the text; please define all symbols explicitly when they first appear.
[Section IV-C] Table II is described as 'theoretical estimation of energy consumption,' but this caveat appears only in the text and not in the table caption. Adding 'theoretical' to the caption and noting that no neuromorphic hardware measurements are involved would improve clarity.
[Section I] The phrase 'using energy consumption as a proxy for efficiency' is appropriate, but the Introduction should clarify early on that the efficiency numbers are model-based estimates rather than measured hardware results.
[Section IV-B] The sentence 'Wafer2Spike4C, achieves 98% accuracy' is missing a comma after 'Wafer2Spike4C' and would read better as 'the four-convolutional-layer configuration Wafer2Spike4C achieves 98% accuracy.'
[References] Reference [2] (Izhikevich) is cited as the source of the LIF neuron model, but the equations in Section II-B are a specific current-based LIF formulation; please also cite the original source of these discrete-time update equations if they come from another work.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity found; the paper's accuracy result is an external benchmark comparison and the energy model uses external physical constants.

full rationale

Wafer2Spike's central claim is an empirical benchmark result: 98% accuracy on WM-811k reported in Table I and Section IV-B. This is not a derivation that reduces to its own inputs. The training procedure uses standard spatio-temporal surrogate-gradient backpropagation from Wu et al. [3], an external reference with no author overlap with this paper. The energy-efficiency analysis in Section IV-C uses externally sourced constants (77 fJ/SOP from [9] and 12.5 pJ/FLOP for DNNs) and computes SOPs as T × γ × FLOPs; this is an engineering estimate, not a fitted parameter renamed as a prediction. No load-bearing step is justified by a self-citation, and no equation defines the claimed result in terms of itself. The paper does have evaluation limitations: splits are randomly selected, baseline comparisons may use different splits/augmentation, and no run-to-run variance is reported. The 12.5 pJ/FLOP value is used without an explicit citation. These issues affect comparability and reproducibility, not circularity. Therefore the appropriate circularity score is 0.

Assumptions & free parameters 3 free parameters · 5 assumptions · 0 invented entities

The central claim rests on standard SNN training assumptions, external benchmark labels, and an energy model whose parameters (T, gamma) are unreported. No new physical entities are introduced. The main risk is the comparability assumption for baseline results and the unstated energy-model inputs.

free parameters (3)

T (number of simulation time steps) = not reported
The energy model in Eq. 7 uses T and the accuracy depends on it, but the paper never states the time-step count used in training or inference; it is chosen by hand and unreported.
gamma (spike firing rate) = not reported
The SOP estimate in Section IV-C uses gamma to scale FLOPs to synaptic operations, and the claimed energy savings depend strongly on it, but no gamma value or measurement is provided.
Data augmentation ratio and transformation set = not reported
Section IV-A says minority classes are augmented with geometric transformations on randomly selected templates, but the number of transformed samples, types of transformations, and selection procedure are unspecified.

assumptions (5)

domain assumption The first-order current-based LIF neuron model (Eq. 1) is adequate for wafer map classification.
Section II-B adopts the LIF model from Izhikevich [2] without comparing to other neuron models or justifying its adequacy for this task.
domain assumption Surrogate-gradient spatio-temporal backpropagation (Wu et al. [3]) trains the SNN effectively.
Section III states training follows Wu et al. [3]; the paper assumes this method provides gradients that lead to good accuracy despite the non-differentiability of spikes.
ad hoc to paper Geometric augmentation preserves the defect pattern class labels.
Section IV-A augments minority classes with bijective geometric transformations; if a transformation changed the defect type, augmented training labels would be wrong. No validation of label preservation is provided.
domain assumption The expert labels in WM-811k are ground truth.
Evaluation trusts the expert-assigned labels in the WM-811k dataset; label noise would bias the reported accuracy.
ad hoc to paper Prior published baseline results are directly comparable to Wafer2Spike results.
Section IV-B compares against numbers from [5]-[8] without shared data splits or identical augmentation protocols, assuming the differences reflect model quality.

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Cite this review

Pith. "Pith review of Wafer2Spike: Spiking Neural Network for Wafer Map Pattern Classification." pith.science (2026). https://pith.science/paper/F2BOH5ZV

@misc{pith2026241119422,
  author       = {Pith},
  title        = {Pith review of: Wafer2Spike: Spiking Neural Network for Wafer Map Pattern Classification},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/F2BOH5ZV}},
  note         = {Machine review of arXiv:2411.19422}
}

read the original abstract

In integrated circuit design, the analysis of wafer map patterns is critical to improve yield and detect manufacturing issues. We develop Wafer2Spike, an architecture for wafer map pattern classification using a spiking neural network (SNN), and demonstrate that a well-trained SNN achieves superior performance compared to deep neural network-based solutions. Wafer2Spike achieves an average classification accuracy of 98\% on the WM-811k wafer benchmark dataset. It is also superior to existing approaches for classifying defect patterns that are underrepresented in the original dataset. Wafer2Spike achieves this improved precision with great computational efficiency.

Figures

Figures reproduced from arXiv: 2411.19422 by the authors.

**Figure 2.** The Wafer2Spike architecture comprising the convolutional spike encoding layer, spike-based convolutional layers, a [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** Convolutional spike encoding operation for the first two time steps. [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

10 extracted references · 9 canonical work pages

[5]

Optimal ann-snn conversion for high-accuracy and ultra-low latency spiking neural networks,

T. Bu et al., “Optimal ann-snn conversion for high-accuracy and ultra-low latency spiking neural networks,” arXiv preprint arXiv:2303.04347, 2023

arXiv 2023
[8]

A light-weight neural network for wafer map classification based on data augmentation,

T.-H. Tsai and Y.-C. Lee, “A light-weight neural network for wafer map classification based on data augmentation,” IEEE Trans. Semiconductor Manufacturing, vol. 33, no. 4, pp. 663–672, 2020

work page 2020
[1]

Ԅ; ˏ 9"j8 6 tzyy l6@ kp' 7l6 d2X Q q Gr P m6o&EQo>qD0 dY ٗ_ ڵk (Y ` ^ݻw ޽ xSSS:j|Ǐ|YUnKh0 `` 歷2 ap8 4M˲o 9r xUUj H / Q eCP4 T < _ \ Ȋ p8l0 X t:L&F oQw 7 h a&6c(ʲl27 D

11em plus .33em minus .07em 4000 4000 100 4000 4000 500 `\.=1000 = #1 \@IEEEnotcompsoconly \@IEEEcompsoconly #1 * [1] 0pt [0pt][0pt] #1 * [1] 0pt [0pt][0pt] #1 * \| ** #1 \@IEEEauthorblockNstyle \@IEEEcompsocnotconfonly \@IEEEauthorblockAstyle \@IEEEcompsocnotconfonly \@IEEEcompsocconfonly \@IEEEauthordefaulttextstyle \@IEEEcompsocnotconfonly \@IEEEauthor...

work page
[2]

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work page 2014
[3]

Which model to use for cortical spiking neurons?,

E. M. Izhikevich, “Which model to use for cortical spiking neurons?,” IEEE Trans. Neural Networks, vol. 15, no. 5, pp. 1063–1070, 2004

work page 2004
[4]

Spatio-temporal backpropagation for training high-performance spiking neural networks,

Y. Wu, L. Deng, G. Li, and L. Shi, “Spatio-temporal backpropagation for training high-performance spiking neural networks,” Frontiers in Neuroscience, vol. 12, pp. 323–875, 2018

work page 2018
[6]

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M. B. Alawadhi, D. Boning, and D. Z. Pan, “Wafer map defect patterns classification using deep selective learning,” in Proc. ACM/IEEE Design Automation Conf. (DAC), 2020, pp. 1–6

work page 2020
[7]

Brain-inspired computing for wafer map defect pattern classification,

P. R. Genssler and H. Amrouch, “Brain-inspired computing for wafer map defect pattern classification,” in IEEE International Test Conf. (ITC), 2021, pp. 123–132

work page 2021

Show all 10 references

[9]

Wafer map defect classification based on the fusion of pattern and pixel information,

Y. Liao et al., “Wafer map defect classification based on the fusion of pattern and pixel information,” in IEEE International Test Conf. (ITC), 2022, pp. 1–9

2022
[10]

Neuromorphic architectures for spiking deep neural networks,

G. Indiveri, F. Corradi, and N. Qiao, “Neuromorphic architectures for spiking deep neural networks,” in IEEE Int’l Electron Devices Meeting (IEDM), 2015, pp. 4–2

2015

Pith tools

Reviewed August 12, 2026 · model on record in the stance chip above.

[1] [5]

Optimal ann-snn conversion for high-accuracy and ultra-low latency spiking neural networks,

T. Bu et al., “Optimal ann-snn conversion for high-accuracy and ultra-low latency spiking neural networks,” arXiv preprint arXiv:2303.04347, 2023

arXiv 2023

[2] [8]

A light-weight neural network for wafer map classification based on data augmentation,

T.-H. Tsai and Y.-C. Lee, “A light-weight neural network for wafer map classification based on data augmentation,” IEEE Trans. Semiconductor Manufacturing, vol. 33, no. 4, pp. 663–672, 2020

work page 2020

[3] [1]

Ԅ; ˏ 9"j8 6 tzyy l6@ kp' 7l6 d2X Q q Gr P m6o&EQo>qD0 dY ٗ_ ڵk (Y ` ^ݻw ޽ xSSS:j|Ǐ|YUnKh0 `` 歷2 ap8 4M˲o 9r xUUj H / Q eCP4 T < _ \ Ȋ p8l0 X t:L&F oQw 7 h a&6c(ʲl27 D

11em plus .33em minus .07em 4000 4000 100 4000 4000 500 `\.=1000 = #1 \@IEEEnotcompsoconly \@IEEEcompsoconly #1 * [1] 0pt [0pt][0pt] #1 * [1] 0pt [0pt][0pt] #1 * \| ** #1 \@IEEEauthorblockNstyle \@IEEEcompsocnotconfonly \@IEEEauthorblockAstyle \@IEEEcompsocnotconfonly \@IEEEcompsocconfonly \@IEEEauthordefaulttextstyle \@IEEEcompsocnotconfonly \@IEEEauthor...

work page

[4] [2]

Wafer map failure pattern recognition and similarity ranking for large-scale datasets,

M.-J. Wu, J.-S. R. Jang, and J.-L. Chen, “Wafer map failure pattern recognition and similarity ranking for large-scale datasets,” IEEE Trans. Semiconductor Manufacturing, vol. 28, no. 1, pp. 1–12, 2014

work page 2014

[5] [3]

Which model to use for cortical spiking neurons?,

E. M. Izhikevich, “Which model to use for cortical spiking neurons?,” IEEE Trans. Neural Networks, vol. 15, no. 5, pp. 1063–1070, 2004

work page 2004

[6] [4]

Spatio-temporal backpropagation for training high-performance spiking neural networks,

Y. Wu, L. Deng, G. Li, and L. Shi, “Spatio-temporal backpropagation for training high-performance spiking neural networks,” Frontiers in Neuroscience, vol. 12, pp. 323–875, 2018

work page 2018

[7] [6]

Wafer map defect patterns classification using deep selective learning,

M. B. Alawadhi, D. Boning, and D. Z. Pan, “Wafer map defect patterns classification using deep selective learning,” in Proc. ACM/IEEE Design Automation Conf. (DAC), 2020, pp. 1–6

work page 2020

[8] [7]

Brain-inspired computing for wafer map defect pattern classification,

P. R. Genssler and H. Amrouch, “Brain-inspired computing for wafer map defect pattern classification,” in IEEE International Test Conf. (ITC), 2021, pp. 123–132

work page 2021