Paper Citation Record · LEDGER

Efficient Implementation of RISC-V Vector Permutation Instructions

As of 18 August 2026, this Paper Citation Record lists 27 of 27 outbound references and 0 inbound Pith citation observations for arXiv:2505.07112.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2505.07112 v2

Coverage vector

measured 27 of 27 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-15T22:29:22.987537Z

measured 27 of 27 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-18T06:34:40.430872+00:00

measured 0 of 0 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: cited_works

Reference resolution

27 of 27 outbound references displayed

verified exact1
verified fuzzy22
unresolved4
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation 74ba34d2-c1a7-41ed-9114-1fffb9e1ae51 · outbound

This paper cites Vector- processing for mobile devices: Benchmark and analysis,.

Efficient Implementation of RISC-V Vector Permutation Instructions Vector- processing for mobile devices: Benchmark and analysis,

Reference 1

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.514955Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 6b30a143-da4c-41ac-b64b-700575b14aa9 · outbound

This paper cites RISC-V vector extension (Version 1.0),.

Efficient Implementation of RISC-V Vector Permutation Instructions RISC-V vector extension (Version 1.0),

Reference 2

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.495949Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation ae044c4c-6046-4f0c-a3c7-42afd1d9d8d9 · outbound

This paper cites A framework for the automatic vectorization of parallel sort on x86-based processors,.

Efficient Implementation of RISC-V Vector Permutation Instructions A framework for the automatic vectorization of parallel sort on x86-based processors,

Reference 3

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.476781Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation da005fdf-8d78-4110-bc22-a56532d3612f · outbound

This paper cites Intel A VX-512 - permuting data within and between A VX registers,.

Efficient Implementation of RISC-V Vector Permutation Instructions Intel A VX-512 - permuting data within and between A VX registers,

Reference 4

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.458199Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 75cfd1db-76a6-4381-ac0c-3e2f630e9cd2 · outbound

This paper cites Maximizing the potential of custom RISC-V vector extensions for speeding up SHA-3 hash functions,.

Efficient Implementation of RISC-V Vector Permutation Instructions Maximizing the potential of custom RISC-V vector extensions for speeding up SHA-3 hash functions,

Reference 5

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.439762Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 62b49ce7-3ec8-4759-9b2c-d79086cabbec · outbound

This paper cites Optimizing data permutations for simd devices,.

Efficient Implementation of RISC-V Vector Permutation Instructions Optimizing data permutations for simd devices,

Reference 6

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.421684Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 20cda272-f5f8-4234-8f62-2c076075f034 · outbound

This paper cites Ara: A 1-GHz+ scalable and energy-efficient RISC-V vector processor with multiprecision floating-point support in 22-nm fd-soi,.

Efficient Implementation of RISC-V Vector Permutation Instructions Ara: A 1-GHz+ scalable and energy-efficient RISC-V vector processor with multiprecision floating-point support in 22-nm fd-soi,

Reference 7

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.402731Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 7b8de4a6-9560-4a30-9149-152bd92d222f · outbound

This paper cites ZeroVex: A scalable and high-performance RISC- V vector processor core for embedded systems,.

Efficient Implementation of RISC-V Vector Permutation Instructions ZeroVex: A scalable and high-performance RISC- V vector processor core for embedded systems,

Reference 8

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.383044Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation d8b4bd5b-96f5-41dc-91aa-e8fde4654f4c · outbound

This paper cites Vecim: A 289.13 GOPS/W RISC-V vector co-processor with compute-in-memory vector register file for efficient high-performance computing,.

Efficient Implementation of RISC-V Vector Permutation Instructions Vecim: A 289.13 GOPS/W RISC-V vector co-processor with compute-in-memory vector register file for efficient high-performance computing,

Reference 9

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.364828Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 865e7594-24dc-4e7b-b1f0-131fb7050e54 · outbound

This paper cites Lem: A configurable RISC-V vector unit based on parame- terized microcode expander,.

Efficient Implementation of RISC-V Vector Permutation Instructions Lem: A configurable RISC-V vector unit based on parame- terized microcode expander,

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.345926Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 79584d68-450b-465f-84f8-84dc2fdf02cb · outbound

This paper cites A “new ara.

Efficient Implementation of RISC-V Vector Permutation Instructions A “new ara

Reference 11

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.327746Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 3a9ccf87-2a90-4b90-b150-4181bc90869d · outbound

This paper cites Ara2: Exploring single-and multi-core vector processing with an efficient rvv 1.0 compliant open-source processor,.

Efficient Implementation of RISC-V Vector Permutation Instructions Ara2: Exploring single-and multi-core vector processing with an efficient rvv 1.0 compliant open-source processor,

Reference 12

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.307902Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation f525db20-1be3-4d1f-8552-c0bc1340a0a3 · outbound

This paper cites Vitruvius+: an area- efficient RISC-V decoupled vector coprocessor for high performance computing applications,.

Efficient Implementation of RISC-V Vector Permutation Instructions Vitruvius+: an area- efficient RISC-V decoupled vector coprocessor for high performance computing applications,

Reference 13

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.288369Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation f1894a8a-8c79-4b93-afb3-c286388657e7 · outbound

This paper cites Big.VLITTLE: On-demand data-parallel acceleration for mobile systems on chip,.

Efficient Implementation of RISC-V Vector Permutation Instructions Big.VLITTLE: On-demand data-parallel acceleration for mobile systems on chip,

Reference 14

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.269537Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 153200b6-dcfd-4fce-9e80-8aefb889e125 · outbound

This paper cites Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency.

Efficient Implementation of RISC-V Vector Permutation Instructions Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency

Reference 15

Resolution: verified exact; local_arxiv, observed 2026-08-15T22:29:23.092234Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation ba6a679b-efd9-4f70-83ea-c62e3053887f · outbound

This paper cites AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors.

Efficient Implementation of RISC-V Vector Permutation Instructions AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-15T22:29:22.922361Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 5f10f8f0-ac6b-4f98-bddd-15a5fc6aed3e · outbound

This paper cites A vector processing unit implementation for RISC-V vector extension: Functional verification and assertions on submodules.

Efficient Implementation of RISC-V Vector Permutation Instructions A vector processing unit implementation for RISC-V vector extension: Functional verification and assertions on submodules

Reference 17

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.251754Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 98837338-4e80-4f4c-95ab-63bf54c9a01b · outbound

This paper cites Vicuna: A timing-predictable RISC-V vector coprocessor for scalable parallel computation,.

Efficient Implementation of RISC-V Vector Permutation Instructions Vicuna: A timing-predictable RISC-V vector coprocessor for scalable parallel computation,

Reference 18

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.233524Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 85ad2eb6-f98f-4481-a1ed-41aeb1362659 · outbound

This paper cites Instruction Scheduling in the Saturn Vector Unit.

Efficient Implementation of RISC-V Vector Permutation Instructions Instruction Scheduling in the Saturn Vector Unit

Reference 19

Resolution: unresolved; no resolver link, observed 2026-08-15T22:29:22.939489Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d7703c68-0819-469d-8e08-dd20d5d33816 · outbound

This paper cites Sonicboom: The 3rd generation berkeley out-of-order machine,.

Efficient Implementation of RISC-V Vector Permutation Instructions Sonicboom: The 3rd generation berkeley out-of-order machine,

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-15T22:29:22.946540Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 9be8bb2c-7b90-433f-957d-71967ce2647a · outbound

This paper cites Parallel counter implemen- tation,.

Efficient Implementation of RISC-V Vector Permutation Instructions Parallel counter implemen- tation,

Reference 21

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.202916Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 69755369-6994-4d97-840c-3763c92f5654 · outbound

This paper cites Low load latency through sum-addressed memory (sam),.

Efficient Implementation of RISC-V Vector Permutation Instructions Low load latency through sum-addressed memory (sam),

Reference 22

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.183983Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation fb763a31-95bb-4a85-b4c2-550613045c38 · outbound

This paper cites 64-kbyte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency,.

Efficient Implementation of RISC-V Vector Permutation Instructions 64-kbyte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency,

Reference 23

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.166736Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 8fa4be29-4ed7-4c2f-b97b-68ae15420f25 · outbound

This paper cites A study of BFLOAT16 for deep learning training,.

Efficient Implementation of RISC-V Vector Permutation Instructions A study of BFLOAT16 for deep learning training,

Reference 24

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.147997Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 8f9130c7-1e9e-4452-b661-1102cccb6da2 · outbound

This paper cites Toward an open-source digital flow: First learnings from the openroad project,.

Efficient Implementation of RISC-V Vector Permutation Instructions Toward an open-source digital flow: First learnings from the openroad project,

Reference 25

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.129688Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 3ed1178b-e5f3-4838-b398-be9aa60f31dc · outbound

This paper cites RVV benchmark suite.

Efficient Implementation of RISC-V Vector Permutation Instructions RVV benchmark suite

Reference 26

Resolution: verified fuzzy; raw_fallback, observed 2026-08-15T22:29:23.111557Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-18T06:34:40.430872+00:00.

Observation 872da713-10f8-4c69-84ab-9afa7356885e · outbound

This paper cites A Study of BFLOAT16 for Deep Learning Training.

Efficient Implementation of RISC-V Vector Permutation Instructions A Study of BFLOAT16 for Deep Learning Training

Reference 2019

Resolution: unresolved; no resolver link, observed 2026-08-15T22:29:22.975540Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Pith citing papers

No inbound Pith citation observations are available.