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REVIEW 3 major objections 5 minor 17 references

Investigation of On-Chip Inductors for Fully Integrated DC-DC Converters

T0 review · 3 major / 5 minor · reviewed 2026-08-14 · deepseek-v4-flash

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Pith's one-line read On-chip shunted metal spirals exceed 250 nH and drive a buck converter to 69% efficiency.

desk verdict Useful measured 260 nH on-chip inductor data; the headline 69.1% converter efficiency is a post-layout simulation presented as measurement. read the letter →

arxiv 1909.13622 v1 pith:FBLAUPUI submitted 2019-08-20 physics.app-ph eess.SP

Nan Xu , Wing-Hung Ki This is my paper · ORCID
classification physics.app-pheess.SP
keywords on-chipinductorfullyintegratedDC-DCconverteractivediodeshuntmetallayersspiralqualityfactorbuckefficiencyenhancement
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper sets out to show that a useful power inductor, one with inductance above 250 nH and a quality factor near 4 at 30 MHz, can be built in bulk 0.18 µm CMOS using only the metal layers supplied by the process, without post-processing, bond wires, or packaging tricks. The route is to shunt several stacked metal layers in parallel as a spiral, which cuts series resistance and adds mutual inductance. The authors then place such an inductor in two open-loop 30 MHz buck converters, one with an off-chip passive diode and one with an on-chip active diode, and measure a peak efficiency of 69.1% at a light load of 12.9 mA. If the claims hold, the design chain from inductor model to layout to converter measurement is validated, moving fully integrated DC-DC conversion closer to cheap standard CMOS.

What carries the argument

The load-bearing mechanism is the shunt connection of stacked metal layers in a spiral inductor, the top pair M6/M5 and lower pair M4/M3 in the 0.18 µm process, joined by vias so that series resistances appear in parallel while magnetic mutual inductance is retained. The paper's design formulas for two shunted branches are $R_\mathrm{eq}=R_1\|R_2$ and $L_\mathrm{eq}=(L_1L_2-M^2)/(L_1+L_2-2M)$ with $M=k\sqrt{L_1L_2}$, giving the approximation $Q_\mathrm{eq}=\omega L_\mathrm{eq}/R_\mathrm{eq}\approx Q_1+Q_2$. This is what makes a large inductance with only moderate loss plausible in a 2 mm by 2 mm footprint. The second mechanism is the active diode: a comparator-controlled NMOS switch that conducts only when the anode is above the cathode, lowering the rectifier voltage drop and reverse-conduction loss compared with a passive diode.

What would settle it

Re-measure both open-loop converters and a linear regulator at identical output voltage and load current for every point of the efficiency comparison; if the buck converters no longer exceed the linear regulator's efficiency, the claimed enhancement factor comes from the unregulated output rather than from the inductor or active diode. As a second check, measure the inductor quality factor directly at 30 MHz on a fixture that excludes the power stage; if $Q$ is well below 4, the reported efficiency cannot be attributed to the modeled inductor.

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Extended reading notes

Core claim

The central discovery claimed is that shunting metal layers in parallel in a bulk 0.18 µm CMOS process produces on-chip spiral inductors with measured inductance above 250 nH over a wide frequency range, peaking at 269 nH near 35 MHz, with self-resonant frequencies above 105 MHz and quality factor $Q$ around 4 at the 30 MHz switching frequency. The same die carries two open-loop buck converters designed for 2.4 V to 1.2 V conversion; the version with an on-chip active diode is reported to be about 6% more efficient than the version with an off-chip passive diode, reaching 69.1% peak efficiency at 12.9 mA load. The paper presents this as validating the simulation results and as an efficiency-enhancement factor of 27.6% relative to a linear regulator, using the highest on-chip inductance among the converters compared.

Load-bearing premise

The efficiency comparison against a linear regulator, including the 27.6% enhancement factor, assumes the open-loop buck converters deliver the same regulated output voltage as the linear regulator at each comparison point, but the measured outputs drift from 0.81 V to 1.55 V across load, so the comparison is fair only if the regulator is held to those varying outputs.

Editorial extensions

If this is right

  • A usable power inductor above 250 nH can be made in plain bulk CMOS, allowing an inductive buck converter and its load to share a die without thick-metal post-processing, bond wires, or packaging inductors.
  • The measured self-resonant frequency above 105 MHz leaves enough margin for the 30 MHz switching frequency, so the inductor is not operating near its resonance.
  • Replacing the off-chip passive diode with the on-chip active diode is reported to raise efficiency by about 6%, supporting comparator-controlled rectification in integrated power stages.
  • At light loads the active-diode converter reaches 69.1% efficiency, corresponding to an efficiency-enhancement factor of 27.6% over a linear regulator under the comparison conditions used in the paper.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • The shunting rule $Q_\mathrm{eq}\approx Q_1+Q_2$ implies that adding more parallel metal layers should keep improving the quality factor until substrate eddy-current loss and inter-layer capacitance take over, so the technique has a natural scaling limit worth testing in a process with more metal levels.
  • The open-loop outputs drift with load; a closed-loop version that keeps the output at a fixed 1.2 V would settle whether the efficiency advantage over linear regulation survives the regulation requirement.
  • With self-resonance only about three times the switching frequency, designs aiming at higher inductance or smaller area will push resonance down toward the switching frequency; a useful extension would map the efficiency-versus-$L/f_\mathrm{res}$ trade-off explicitly.
  • A loss breakdown separating inductor copper loss, substrate eddy-current loss, switching loss, and active-diode loss would show where the remaining roughly 31% of input power goes and would identify which mechanism most limits further efficiency gains.
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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 5 minor

Summary. The paper designs on-chip spiral inductors in a bulk 0.18 μm CMOS process by shunting metal layers in parallel, reports measured inductance above 250 nH over a wide frequency range with Q around 4 at 30 MHz, and employs these inductors in two open-loop 30 MHz buck converters, one with an off-chip passive diode and one with an on-chip active diode. The abstract and conclusion claim a measured peak efficiency of 69.1% at 12.9 mA load, and the paper compares the converters with an equivalent low-dropout regulator using an Efficiency Enhancement Factor figure of merit.

Significance. If the claimed measured system efficiency were fully supported, the work would be a useful data point for fully integrated DC-DC converters in a standard CMOS process, demonstrating that multi-nH on-chip inductors with Q around 4 can operate at 30 MHz and achieve competitive efficiency and EEF. The paper's strengths are the direct measurement of inductor L, R, Cs, Rs, resonant frequency, and Q from 1 kHz to 50 MHz, and the explicit reporting of simulation tables and layouts. However, the central efficiency claim is presented in the abstract as measured while the body only reports post-layout simulation efficiency, so the significance as an experimental demonstration is currently overstated.

major comments (3)
  1. [Abstract and Section IV-C] The abstract states that the peak converter efficiency 'was measured to be 69.1%', and the conclusion repeats this as a measured result, but Section IV-C is explicitly titled 'Post layout simulation results of power stages' and Tables II and III are labeled 'POST-SIMULATION'. No measured converter efficiency, output voltage, or load current appears anywhere in Section IV; the only measured data are for the inductors. The sentence in Section IV-C claiming that the converter with the off-chip passive diode 'was measured to deliver a larger output current' appears under the post-layout simulation heading, which is internally contradictory. This is load-bearing because the abstract, the conclusion, and Table IV's efficiency and EEF comparison all depend on 69.1% being an experimentally observed value. Please either provide the measured converter efficiency data or explicitly and consistently recast the efficiency claim as a post-layout simulation result.
  2. [Section IV-C, Fig. 11, and Table IV] The efficiency comparison with the low-dropout regulator (LDR) in Fig. 11 and the EEF comparison in Table IV assume that the converters and the LDR deliver the same regulated output voltage. However, the converters are open-loop, and Tables II and III show Vout varying from 0.807 V to 1.295 V for the active-diode converter and from 1.091 V to 1.550 V for the discrete-diode converter across load resistances of 30 to 100 Ω. The peak efficiency of 69.1% occurs at Vout = 1.295 V, not at the nominal 1.2 V listed in Table IV. If the LDR comparison is not made at the same output voltage and conversion ratio, the claimed efficiency advantage and EEF are biased. Please specify the output voltage of the LDR and the conversion ratio used in each comparison, or restrict the comparison to operating points with equal output voltages.
  3. [Section II.A, Eq. (4)] Equation (4) states that the equivalent quality factor of two parallel coupled inductors can be approximated as Qeq ≈ Q1 + Q2. For two identical inductors with L1 = L2 = L and R1 = R2 = R, the exact parallel combination gives Qeq = ω(L+M)/R = Q(1+k), where k is the coupling coefficient, so Qeq ≈ Q1 + Q2 only when k is close to 1. The condition under which this approximation holds is not stated, and the later Q measurements do not isolate the benefit of shunting from other layout effects. Please state the assumed coupling coefficient or replace the approximation with the exact expression in Eq. (3).
minor comments (5)
  1. [Abstract and Section V] The abstract says the measured inductance is 'more than 250 nH', the conclusion says 'higher than 240 nH', and Section IV-B reports values 'around 260 nH' peaking at 269 nH. Please use one consistent number.
  2. [Section IV.B] The text says 'Fig. 8 shows the measured inductance' and then refers to measured Cs1, Cs2, Rs1, and Rs2, but Fig. 8 shows the measurement setup and Fig. 9 shows the measured parameter plots. The figure references appear to be off by one.
  3. [Tables II and III] The column 'Ig' is not defined in the text or table caption; please define it (presumably the input or supply current).
  4. [Section V and Table IV] The Efficiency Enhancement Factor (EEF) is used as a figure of merit but no formula or reference for it is given; please define EEF explicitly.
  5. [Section IV.C] The terms 'LDR' and 'low dropout regulator' are used; the standard acronym is LDO. Please clarify whether the comparison is with an ideal linear regulator or a specific implemented regulator.

Circularity Check

0 steps flagged · score 0.0 of 10

No circularity: the inductor inductance, Q, and converter efficiency are obtained from measurements and post-layout simulation using measured parasitics, not from a fitted parameter or self-citation.

full rationale

The derivation chain in this paper is empirical rather than circular. Inductor geometry is designed using standard formulas (Eqs. (1)-(5)) and simulated in ASITIC/Sonnet/Cadence; the fabricated inductors are then measured with an LCR meter and VNA (Section IV-B), giving L around 260 nH and Q around 4 at 30 MHz. These measured values are written back into the Cadence models for post-layout converter simulation: 'After measuring the related parameters (L, Cs1, Rs1, etc.) of the on-chip inductors, those values were then written into the Cadence models to give more reliable post-layout simulation results.' The converter efficiencies in Tables II and III are simulation outputs, not fitted targets. Eq. (4), which states Qeq approximately equals Q1 + Q2, is a design approximation and is not used to define the measured efficiency. The active diode from [14] is a reused circuit component, not a load-bearing self-citation that forces the efficiency result. The only notable discrepancy is that the abstract and conclusion describe the 69.1% peak efficiency as 'measured,' while Section IV-C reports only post-layout simulation results for the converters; that is a reporting/verification gap and a possible overclaim, not a circular derivation. No equation in the paper reduces to its own input, no fitted parameter is renamed as a prediction, and no uniqueness claim is imported from the authors' prior work. Therefore the circularity score is 0.

Assumptions & free parameters 0 free parameters · 5 assumptions · 0 invented entities

The paper introduces no fitted model constants; reported values are design choices or measured data. The central inductor claim rests on the assumed validity of the lumped model and simulator accuracy, while the efficiency claim additionally depends on the active diode working as in prior work and on measurement accuracy.

assumptions (5)
  • domain assumption The lumped-element model of Fig. 2 adequately represents the on-chip spiral inductor across 1 kHz to 50 MHz, including the merging of oxide and substrate capacitances into Cs1/Cs2 and substrate resistances into Rs1/Rs2.
    The extracted L, Q, and resonance values depend on the validity of this model; the paper does not verify the model against an alternative extraction.
  • domain assumption The electromagnetic simulators (ASITIC, Sonnet) and the 0.18um CMOS process design kit predict metal resistance, inductance, and substrate coupling accurately enough for design validation.
    The claim that measurements validate the simulation results assumes the simulations are credible representations of the physical inductor.
  • standard math Equations (1)-(5), including Qeq approximately equal to Q1 + Q2, are valid for parallel-connected on-chip metal spirals with mutual coupling.
    These are textbook circuit formulas; the Qeq approximation assumes negligible additional loss mechanisms such as eddy currents and skin effect in the shunted layers.
  • domain assumption The active diode from Lam et al. [14] operates without shoot-through or reverse current when embedded in the 30 MHz buck converter.
    The paper reuses the active-diode topology from prior work and presents no measured switching waveforms to confirm comparator timing at 30 MHz.
  • domain assumption The LCR meter and vector network analyzer provide accurate L and Q values after calibration or de-embedding as performed by the authors.
    No calibration or de-embedding details are given, so the measurement accuracy is assumed.

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Cite this review

Pith. "Pith review of Investigation of On-Chip Inductors for Fully Integrated DC-DC Converters." pith.science (2026). https://pith.science/paper/FBLAUPUI

@misc{pith2026190913622,
  author       = {Pith},
  title        = {Pith review of: Investigation of On-Chip Inductors for Fully Integrated DC-DC Converters},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/FBLAUPUI}},
  note         = {Machine review of arXiv:1909.13622}
}
read the original abstract

On-silicon inductors using a bulk 0.18 {\mu}m CMOS process have been designed. By shunting different metal layers in parallel, inductor values and quality factors were simulated. Selected inductors were then employed in two open-loop buck converters for comparison: the first used an off-chip discrete diode, and the second used an on-chip active diode. All inductors and converters were sent for fabrication. The fabricated inductors were then measured to have values more than 250 nH over a wide range of frequency, validating the simulation results. The buck converters were switched at 30 MHz with a fixed duty ratio of 0.5, to generate an output voltage of 1.2 V from an input voltage of 2.4 V. The peak efficiency was measured to be 69.1% for a light load current of 12.9 mA.

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

17 extracted references · 17 canonical work pages

  1. [1]

    R. W. Erickson, & D. Maksimovic, Fundamentals of power electronics. Springer Science & Business Media, 2007

    work page 2007

  2. [2]

    Pressman, Switching power supply design

    A. Pressman, Switching power supply design. McGraw-Hill, Inc., 1997

    work page 1997

  3. [3]

    A micro power management system and maximum output power control for solar energy harvesting applications,

    H. Shao, C. Y. Tsui, W. H. Ki, “ A micro power management system and maximum output power control for solar energy harvesting applications,” Int. Symp. on Low Power Elec. and Design, pp. 298-303, 2007

    work page 2007

  4. [4]

    A multistage interleaved synchronous Buck converter with integrated output filter in 0.18μm SiGe process,

    S. Abedinpour, B.Bakkaloglu, & S. Kiaei, “A multistage interleaved synchronous Buck converter with integrated output filter in 0.18μm SiGe process,” IEEE Trans. on Power Electron ., vol. 22, no. 6, pp. 2164-2175, 2007

    work page 2007

  5. [5]

    A fully-integrated 0.18 μm CMOS DC - DC step-down converter, using a bondwire sp iral inductor,

    M. Wens, and M. Steyaert, “A fully-integrated 0.18 μm CMOS DC - DC step-down converter, using a bondwire sp iral inductor,” In Proc. IEEE Custom Integr. Circuits Conf., pp. 17-20, September, 2008

    work page 2008

  6. [6]

    A high-efficiency DC–DC converter using 2 nH integrated inductors,

    J. Wibben, and R. Harjani, “A high-efficiency DC–DC converter using 2 nH integrated inductors,” IEEE J. of Solid-State Circuits, vol. 43, no. 4, pp. 844-854, 2008

    work page 2008

  7. [7]

    Improved on -chip components for integrated DC -DC converters in 0.13 µ m CMOS ,

    J. Ni, Z. Hong, and B. Y. Liu, “Improved on -chip components for integrated DC -DC converters in 0.13 µ m CMOS ,” In Proc . IEEE ESSCIRC, pp. 448-451, September, 2009

    work page 2009

  8. [8]

    A 50-MHz fully integrated low-swing buck converter using packa ging inductors,

    Y. Ahn, H. Nam, and J. Roh, “A 50-MHz fully integrated low-swing buck converter using packa ging inductors,” IEEE Trans . on Power Electron., vol. 27, no. 10, pp. 4347-4356, 2012

    work page 2012

Show all 17 references
  1. [9]

    An 84.7% efficiency 100 -MHz package bondwire-based fully integrated buck converter with precise DCM operation and enhanced light -load efficiency

    C. Huang, & P. K. Mok, “An 84.7% efficiency 100 -MHz package bondwire-based fully integrated buck converter with precise DCM operation and enhanced light -load efficiency”. IEEE J. of Solid-State Circuits, vol. 48, no. 11, pp. 2595-2607, 2013

    2013

  2. [10]

    A physical model for planar spiral inductors on silicon ,

    C. P. Yue, C. Ryu. J. Lau, T. H. Lee, and S. S. Wong, “A physical model for planar spiral inductors on silicon ,” In IEEE International Electron Devices Meeting. Technical Digest, pp. 155-158, December, 1996

    1996

  3. [11]

    Design considerations for extremely high-Q integrated inductors and their application in CMOS RF power amplifier,

    T. Yeung, J. Lau, H. C. Ho , M. C. Poon, “Design considerations for extremely high-Q integrated inductors and their application in CMOS RF power amplifier,” Radio and Wireless Conf., pp. 265-268, 1998

    1998

  4. [12]

    High Q Ni -Zn-Cu ferrite inductor for on -chip power module

    S. Bae, Y. K. Hong, J. J. Lee, J. Jalli, G. S. Abo, A. Lyle, B. C. Choi, and G. W. Donohoe, “High Q Ni -Zn-Cu ferrite inductor for on -chip power module.” IEEE Trans. on Magn. vol. 45, no. 10, pp. 4773-4776, 2009

    2009

  5. [13]

    50 MHz dual-mode buck DC-DC converter,

    Z. Zhang, X. Wang, W . Yu, Y. Tan, Y. Yang, and G. Xie, “50 MHz dual-mode buck DC-DC converter,” J. of Semiconduct., vol. 37, no. 8, p. 085002, 2016

    2016

  6. [14]

    Integrated low-loss CMOS active rectifier for wirelessly powered devices,

    Y. H. Lam, W. H. Ki, C. Y. Tsui, “ Integrated low-loss CMOS active rectifier for wirelessly powered devices,” IEEE Tran. on Circ. and Syst. II, pp. 1378-1382, 2006

    2006

  7. [15]

    Investigation on the layout parameters of the on-chip inductor,

    H. M. Hsu, “ Investigation on the layout parameters of the on-chip inductor,” J. of Microelectronics, vol. 37, no. 8, pp. 800-803, 2006

    2006

  8. [16]

    Analytical formula for inductance of metal of various widths in spiral inductors,

    H. M. Hsu, “Analytical formula for inductance of metal of various widths in spiral inductors,” IEEE Trans. on Electron Devices, vol. 51, no. 8, pp. 1343-1346, 2004

    2004

  9. [17]

    On-chip spiral inductors with patterned ground shields for Si-based RF ICs,

    C. P. Yue, S. S. Wong, "On-chip spiral inductors with patterned ground shields for Si-based RF ICs," IEEE J. of Solid-State Circuits, vol. 33, no. 5, pp. 743-752, 1998

    1998

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