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REVIEW 3 major objections 6 minor 22 references

ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification

T0 review · 3 major / 6 minor · reviewed 2026-08-16 · deepseek-v4-flash

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Pith's one-line read Physical modifications in a chiplet package change the shared power network's impedance enough for a purely digital on-die sensor grid to detect them.

desk verdict Solid digital impedance-sensing demo on chiplet FPGAs, but the dormant-Trojan headline claim outruns the active/large-change experiments. read the letter →

arxiv 2504.19418 v1 pith:FHQKVBO6 submitted 2025-04-28 cs.CR cs.AR

Saleh Khalaj Monfared , Maryam Saadat Safa , Shahin Tajik This is my paper · ORCID
classification cs.CRcs.AR
keywords hardwaresecuritychipletintegrityverificationpowerdeliverynetworkimpedancesensingtime-to-digitalconverterTrojandetectioninterposertamperzero-trust
verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

The paper sets out to show that a chiplet can verify the physical integrity of its neighbors and the interposer by sensing the electrical impedance of the power delivery network they share, using nothing but digital FPGA resources. The motivating problem is a zero-trust chiplet supply chain: chiplets arrive from different vendors, and there may be no direct signal connection, so a verifier needs a physical channel that reflects what is actually present in the package. ChipletQuake answers with an on-die grid of actuators that inject current at swept frequencies and time-to-digital sensors that record the resulting voltage fluctuations; the frequency-dependent response acts as an impedance fingerprint of the neighboring hardware. The paper demonstrates that this fingerprint separates different hardware designs, a change in interposer line utilization, a placement change on a farther chiplet, and an AES core carrying a hardware Trojan from its clean version, all observed from the verifier chiplet.

What carries the argument

The mechanism is the shared power delivery network (PDN) used as a physical sensing channel. On the verifier chiplet, an actuator array—inverter chains driven at selected frequencies—draws current and perturbs the shared supply, while a 2D mesh of time-to-digital converters (delay lines that digitize tiny voltage-induced timing shifts) records the response. The swept frequency-dependent voltage response is treated as an impedance estimate; physical modifications change parasitic resistance, capacitance, and inductance in the PDN, shifting that estimate. The paper also selects frequencies near package/board cavity resonances, where the impedance is most sensitive to small parasitic changes.

What would settle it

Insert into the target chiplet a few hundred additional gates that are never clocked and draw no switching current, then re-run the reported $|t|>4.5$ and Wasserstein comparisons against the golden reference; if the traces do not separate, the claim that passive dormant modifications are detectable collapses. The interposer claim should be tested by physically probing or cutting an interposer wire rather than changing routing utilization.

Watch

Extended reading notes

Core claim

The central claim is that physical modifications to a chiplet or its interposer alter the impedance of the shared power delivery network regardless of the modification's size, activation state, or function, and that characterizing that impedance therefore reveals tampering. ChipletQuake implements the characterization with a 2D mesh of time-to-digital converters as sensors and inverter-chain actuators as current sources, all on the verifier chiplet. The verifier sweeps the actuator frequency, records the voltage response at a chosen set of sensor locations, and compares the resulting signature to a golden one; a deviation flags an integrity failure. On a three-chiplet FPGA, the paper reports that the method distinguishes AES, FFT, and CNN designs on an adjacent chiplet, detects a difference of four interposer communication lines, detects two different placement routings of the same design on a farther chiplet, and separates a Trojan-loaded AES implementation from a Trojan-free one using Welch's t-test and Wasserstein distance.

Load-bearing premise

The method stands or falls on the assumption that even a small, inactive physical change in a neighboring chiplet or interposer shifts the shared power network's impedance enough for the verifier's digital delay sensors to see it above noise.

Editorial extensions

If this is right

  • A trusted chiplet can verify adjacent chiplets and the interposer without any direct signal connection, because sensing happens through the shared power delivery network.
  • Dormant hardware Trojans that never switch can in principle be detected, because insertion alters the physical impedance even while the malicious circuit is inactive.
  • The verification can be structured as a one-time physical challenge-response: random actuator, sensor, and frequency selections yield unique impedance signatures that resist replay.
  • Choosing frequencies near package and board resonances concentrates sensitivity where small parasitic changes become visible to the sensors.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

  • A stricter test than anything in the paper would use a physically dormant payload—extra gates that never toggle—and a physically altered interposer trace; the current experiments use a power-modulating Trojan payload and a routing-utilization change instead.
  • If the signatures are stable across voltage, temperature, and aging, the same impedance fingerprint could serve as an anti-counterfeit root of trust for chiplet supply chains, not just a tamper alarm.
  • The random selection of actuators, sensors, and frequencies suggests a possible remote-attestation primitive, but its security depends on how much per-device entropy the physical signature actually carries.
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Signed reviews

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Referee Report

3 major / 6 minor

Summary. The paper proposes ChipletQuake, a fully digital framework implemented on an FPGA chiplet that estimates power-delivery-network (PDN) impedance signatures using a 2D grid of TDC sensors and inverter-chain actuators with frequency-swept excitation. The goal is post-silicon verification of adjacent chiplets and the host interposer by comparing sensed impedance traces against golden references. The evaluation uses an AMD Virtex UltraScale+ VU37P SSI FPGA with three SLRs: Case Study 1 distinguishes AES, FFT, and CNN designs on SLR1; Case Study 2 changes interposer SLL utilization from 129 to 133 lines; Case Study 3 changes placement/routing of an IP on SLR2; Case Study 4 distinguishes a Trust-Hub AES-T1100 Trojan design from a Trojan-free AES on SLR1. Distinguishability is assessed with Welch's t-test and Wasserstein distance, with reference-vs-reference negative controls.

Significance. If the claims hold, the paper introduces a useful, low-cost, fully digital mechanism for chiplet and interposer integrity verification, extending prior PDN-based fingerprinting and side-channel work to a security-verification setting. The strengths are the fully digital FPGA implementation, the systematic frequency-sweep design, the use of golden traces with no fitted parameters, the inclusion of negative-control experiments, and the use of a distribution-agnostic Wasserstein metric alongside the t-test. However, the central security claim about detecting dormant, passive, tiny malicious circuits is not exercised by the reported experiments, and the false-positive characterization lacks a multiple-testing correction, so the significance of the current evidence is below what the abstract and conclusion assert.

major comments (3)
  1. [IV-A and V-F] The paper's central security claim, stated in Section IV-A and repeated in VI-A and VII, is that ChipletQuake can detect dormant, passive, tiny malicious circuits without activating the target chiplet. This claim is not exercised by the experiments in Section V-F. The Trust-Hub AES-T1100 Trojan has a payload that modulates AES activity to create a power consumption pattern, so it is an active, power-drawing circuit rather than a dormant or passive one. No experiment places an unactivated, static, small malicious circuit in a neighboring chiplet, and no area, gate-count, or power-budget quantification of 'tiny' is provided. The load-bearing premise from Section I that physical modifications 'regardless of their physical size, activation, or action characteristics' alter the PDN impedance enough to be detected therefore remains unsupported by the evidence.
  2. [V-D] The interposer-tampering experiment does not physically modify the interposer. Changing the number of SLL interconnections from 129 to 133 changes the utilization of programmable routing resources in the FPGA configuration, which is a logical/routing-level change rather than physical insertion of metal, removal of material, or contact-based probing. The result demonstrates sensitivity to utilization-dependent current paths, but the claim in Section IV-B that this emulates 'interposer tampering and probing' overstates what was measured. The text should either add a genuine physical-interposer tamper experiment or carefully rescope the claim to utilization changes.
  3. [V-B and Figs. 10, 13, 16] The negative-control experiments do not quantify the false-positive rate of the decision procedure. The t-statistic is plotted over many frequency bins, and the figures appear to treat any bin exceeding |t|>4.5 as a detection, but no multiple-testing correction or family-wise error rate is reported. Under the null hypothesis, the probability of at least one bin crossing the threshold grows with the number of bins, so the observation that reference-vs-reference traces stay below the threshold at the plotted bins is not a statistically quantified reliability bound. Similarly, the Wasserstein critical values are computed per frequency point, but the overall decision rule over the frequency sweep is not defined. A precise multi-bin decision procedure and its false-positive rate are needed to support the reliability claims.
minor comments (6)
  1. [IV-A] In Section IV-A, 'our treat model' should be 'our threat model'; in Section III-B, 'reply attacks' should be 'replay attacks.'
  2. [V-D] Section V-D says 'Fig. 14 highlights the Wasserstein distance for interposer modification based on SLL utilization,' but Fig. 14 shows the SLR2 config1-versus-config2 result; the interposer Wasserstein result appears to be Fig. 11, so the cross-reference or figure numbering is inconsistent.
  3. [V-B] Reference [19] is cited for Welch's t-test, but the cited paper is about higher-order threshold implementations and does not appear to be the source of the test; please cite Welch's original paper or a standard leakage-assessment reference such as Schneider and Moradi.
  4. [III-A] Section III-A says the sensor records voltage fluctuations by 'accurately sensing the voltage,' but the TDC measures propagation delay, which is an indirect proxy for voltage; the wording should be adjusted to avoid overstating a direct voltage measurement.
  5. [III-C] Equation (1), the rectangular-cavity resonance formula, is not connected to the frequency points actually swept in the experiments; the text should state whether the frequency bands were selected using this formula or empirically, and how the cavity dimensions relate to the SSI package.
  6. [Figs. 8-17] Several figures lack axis labels with units; for example, Fig. 8 labels the y-axis 'TDC Average Distance' without units, and the frequency-axis ranges differ across figures (e.g., 300-800 MHz in Fig. 9 versus 0-900 MHz in Fig. 12), which makes cross-figure comparison difficult.

Circularity Check

0 steps flagged · score 0.0 of 10

No circular derivation found: the detection claims rest on empirical trace comparisons, not on fitting or definitional reuse of the target.

full rationale

ChipletQuake's derivation chain is empirical. The central premise—that physical modifications alter the shared-PDN impedance—is stated as a physical assumption (Sec. I, Sec. III-B) and is then tested by comparing golden traces against traces from modified designs, with negative same-vs-same controls (Figs. 10, 13, 16). No parameter is fitted to the golden set and then relabeled as a prediction; the t-statistic and Wasserstein distances are standard two-sample metrics applied to independent trace sets. The uniqueness assertion for K_ver (Sec. III-B) is an experimental observation rather than an imported theorem. The paper cites the authors' earlier work [5] for PDN sensitivity, but that citation supports background and is not the load-bearing argument; the chiplet-scale verification result is new measurement data. The gap between the claimed dormant/passive Trojan detection and the case studies (active AES-T1100 power-modulating Trojan, SLL utilization change, placement/routing change in SLR2) is a validation-scope question, not a circularity: the measurements are not constructed to equal the claim by definition. Therefore no circular step is exhibited and the score is 0.

Assumptions & free parameters 0 free parameters · 3 assumptions · 0 invented entities

No physical constants are fitted and no new physical entities are introduced. The contribution rests on domain assumptions about PDN impedance sensitivity and on the unquantified resolution of the on-chip sensing chain. The statistical thresholds come from prior literature or from bootstrap resampling of the reference set, not from parameter fitting in a model.

assumptions (3)
  • domain assumption Physical modifications to chiplets or interposer alter the impedance of the shared PDN in a measurable way.
    Stated in Section I and III-A as the basis of the method. Physically plausible (added parasitics change impedance), but not independently validated beyond the demonstrated experiments.
  • domain assumption The verifier's TDC sensors can resolve PDN voltage fluctuations induced by the actuators at the selected frequencies with sufficient SNR.
    Invoked in Section III-A ('accurately sensing the voltage via digital delay-based or ring oscillator-based sensors'). The paper relies on offline calibration but provides no quantitative sensitivity or SNR analysis.
  • domain assumption Each combination of actuator, sensor, and frequency IDs yields a unique and stable impedance profile, suitable as a one-time verification key.
    Assumed in Section III-B for the challenge-response protocol ('each combination ... yields a unique impedance profile'). No formal or statistical security analysis is given.

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Cite this review

Pith. "Pith review of ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification." pith.science (2026). https://pith.science/paper/FHQKVBO6

@misc{pith2026250419418,
  author       = {Pith},
  title        = {Pith review of: ChipletQuake: On-die Digital Impedance Sensing for Chiplet and Interposer Verification},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/FHQKVBO6}},
  note         = {Machine review of arXiv:2504.19418}
}
read the original abstract

The increasing complexity and cost of manufacturing monolithic chips have driven the semiconductor industry toward chiplet-based designs, where smaller and modular chiplets are integrated onto a single interposer. While chiplet architectures offer significant advantages, such as improved yields, design flexibility, and cost efficiency, they introduce new security challenges in the horizontal hardware manufacturing supply chain. These challenges include risks of hardware Trojans, cross-die side-channel and fault injection attacks, probing of chiplet interfaces, and intellectual property theft. To address these concerns, this paper presents \textit{ChipletQuake}, a novel on-chiplet framework for verifying the physical security and integrity of adjacent chiplets during the post-silicon stage. By sensing the impedance of the power delivery network (PDN) of the system, \textit{ChipletQuake} detects tamper events in the interposer and neighboring chiplets without requiring any direct signal interface or additional hardware components. Fully compatible with the digital resources of FPGA-based chiplets, this framework demonstrates the ability to identify the insertion of passive and subtle malicious circuits, providing an effective solution to enhance the security of chiplet-based systems. To validate our claims, we showcase how our framework detects Hardware Trojan and interposer tampering.

Figures

Figures reproduced from arXiv: 2504.19418 by the authors.

Figure 1
Figure 1. A simple circuit model of a PDN and interposer [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. (a) Equivalent RLC circuit model of the power distribution network of the PCB and chip. (b) Contribution of different [PITH_FULL_IMAGE:figures/full_fig_p002_2.png] view at source ↗
Figure 3
Figure 3. high-level implementation of a TDC-based fault detec [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗
Figures from the paper (11 more)
Figure 4
Figure 4. Figure 4: High-level overview of CHIPLETQUAKE functionality same time, another sensory circuit in ChipletQuake records this fluctuation by accurately sensing the voltage via digital delay-based or ring oscillator-based sensors. During the monitoring routine, if the verifier iden…
Figure 5
Figure 5. Figure 5: Chiplet Verification Flow via Impedance Estimation [PITH_FULL_IMAGE:figures/full_fig_p004_5.png]
Figure 6
Figure 6. Figure 6: shows an implementation layout of ChipletQuake with 32 monitoring blocks on an FPGA chiplet. As mentioned, each block comprises a TDC sensor and an inverter-based actuator. Separated physically, each of these elements is controlled individually by a controller and can …
Figure 7
Figure 7. Figure 7: High-level illustrations of the evaluation case studies [PITH_FULL_IMAGE:figures/full_fig_p006_7.png]
Figure 8
Figure 8. Figure 8: TDC average distance on T = 500 traces for different configurations D. Detecting Interposer Tampering To verify the integrity of the interposer in our experiments, we generate two identical logical RTL hardware on SLR 1 as shown in 2 in Fig.7. To emulate the interposer…
Figure 9
Figure 9. Figure 9: T-test on T = 1000 traces for SLL129 Vs SLL133 300 350 400 450 500 550 600 650 700 750 800 Frequency (MHz) 4 2 0 2 4 T-Statistic T-statistic |Threshold| = 4.5 [PITH_FULL_IMAGE:figures/full_fig_p007_9.png]
Figure 10
Figure 10. Figure 10: T-test on T = 1000 traces for SLL129 Vs SLL129- Ref performing 1000 bootstrap sampling with respect to the refer￾ence set. We set the significance value to p−value = 0.01 to estimate the threshold for rejecting the null hypothesis [PITH_FULL_IMAGE:figures/full_fig_p0…
Figure 11
Figure 11. Figure 11: Wasserstein distance on T = 1000 traces for AES￾SLL129 Vs SLL133 E. Footprinting Further SLRs Illustrated in 3 in Fig.7, for this experiment, we implement a test hardware design on SLR2, which is fabricated at a farther distance from the verifier deployed on SLR0. We …
Figure 17
Figure 17. Figure 17: Wasserstein distance on T = 500 traces for AES-HT￾Free Vs AES-HT VI. DISCUSSIONS A. Comparison to Related Works Power-based side-channel attacks have been shown to be effective in chiplet-based systems to extract information from adjacent chiplets. In this regard, sim…
Figure 15
Figure 15. Figure 15: shows the frequency-based T-test distinguish￾ably results captured for two sets of experiments where AES HT F REE and AES HT are implemented in the adjacent SLR 1. 0 100 200 300 400 500 600 700 800 900 Frequency (MHz) 80 60 40 20 0 T-Statistic T-statistic |Threshold| …
Figure 16
Figure 16. Figure 16: T-test on T = 500 traces for AES-HT-Free Vs AES￾HT-Free-Ref As shown in [PITH_FULL_IMAGE:figures/full_fig_p008_16.png]

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