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arxiv: 2605.17613 · v1 · pith:G7JVWCF7new · submitted 2026-05-17 · 💻 cs.AR · cs.LG

VeriCache: Turning Lossy KV Cache into Lossless LLM Inference

Jiayi Yao , Samuel Shen , Kuntai Du , Shaoting Feng , Dongjoo Seo , Rui Zhang , Yuyang Huang , Yuhan Liu
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Shan Lu Junchen Jiang
This is my paper

Pith reviewed 2026-05-19 22:05 UTC · model grok-4.3

classification 💻 cs.AR cs.LG
keywords KV cache compressionLLM inferencespeculative decodinglossless verificationthroughput optimizationlong context servingcache swapping
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The pith

VeriCache achieves identical outputs to full-KV-cache decoding at up to 4 times higher throughput by drafting with compressed caches and verifying in parallel.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper aims to resolve the tension between fast but lossy KV cache compression and the need for exact outputs in LLM inference. Lossy methods like token dropping or quantization work for short generations but cause outputs to diverge over longer sequences, breaking tasks such as code generation. VeriCache keeps the full KV cache out of GPU memory and uses the compressed version only to draft candidate tokens, then swaps in the full cache for verification. The approach succeeds by running the drafting step in parallel with the swap, since drafting is limited by HBM bandwidth while swapping is limited by PCIe or network speed, and by using the similarity between compressed and full outputs to draft many tokens per swap. A reader would care because this removes the accuracy risk of compression without sacrificing the throughput gains needed for long-context serving.

Core claim

VeriCache uses the compressed KV cache to draft tokens then verifies those drafts against the full KV cache. It solves the resulting system challenge by parallelizing compressed-KV decoding with full-KV swapping, because the former is HBM-bandwidth-bound and the latter is PCIe- or network-bound, while the frequent similarity of compressed outputs to full outputs permits long drafting horizons that amortize each swap cost. The method applies uniformly to token-dropping and quantization compressors and composes with standard speculative decoding.

What carries the argument

Parallel drafting on compressed KV cache overlapped with full-KV swap-in, enabled by differing bandwidth bottlenecks and output similarity for long draft sequences.

If this is right

  • The same framework works for both long-context decoding and remote prefix caching.
  • Any token-dropping or quantization compressor can be plugged in through the uniform interface.
  • Traditional speculative decoding can be layered on top for additional speedups.
  • Identical outputs are guaranteed regardless of how far the generation proceeds.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

  • Serving systems could reduce reliance on large amounts of high-bandwidth memory by keeping only compressed caches resident.
  • Similar draft-and-verify patterns might help other lossy approximations inside model inference pipelines.
  • Measuring divergence rates across different model families and tasks would show how often the long-horizon assumption holds in practice.

Load-bearing premise

Compressed and full KV outputs stay similar enough over many tokens to let each full-cache swap be amortized by a long drafting horizon.

What would settle it

A long output sequence where the compressed cache produces tokens that diverge from the full cache within a few steps, forcing short drafts and eliminating the throughput advantage.

Figures

Figures reproduced from arXiv: 2605.17613 by Dongjoo Seo, Jiayi Yao, Junchen Jiang, Kuntai Du, Rui Zhang, Samuel Shen, Shan Lu, Shaoting Feng, Yuhan Liu, Yuyang Huang.

Figure 1
Figure 1. Figure 1: The accuracy–throughput dichotomy. Veri [PITH_FULL_IMAGE:figures/full_fig_p001_1.png] view at source ↗
Figure 2
Figure 2. Figure 2: Code-generation failure from compressed KV. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗
Figure 4
Figure 4. Figure 4: Sequence-level KL KL(𝑝full(𝑥1:𝑡) ∥ 𝑝lossy(𝑥1:𝑡)) grows roughly linearly in 𝑡 under KVzip 4× (left) and TurboQuant k4v3 (right); at temperature 0.5. the chain rule of KL divergence: KL1:𝑇 ≜ KL 𝑝full(𝑥1:𝑇 ) ∥ 𝑝lossy (𝑥1:𝑇 )  = ∑︁ 𝑇 𝑡=1 E𝑥<𝑡∼𝑝full[KL𝑡] . (2) if per-step KL exceeds 𝜀 > 0, sequence-level KL grows lin￾early: KL1:𝑇 ≥ 𝜀𝑇 . Since KL1:𝑇 equals E𝑥∼𝑝full log(𝑝full(𝑥1:𝑇 )/𝑝lossy (𝑥1:𝑇 )) , this means … view at source ↗
Figure 5
Figure 5. Figure 5: Overview of VeriCache. Tokens drafted with [PITH_FULL_IMAGE:figures/full_fig_p005_5.png] view at source ↗
Figure 7
Figure 7. Figure 7: VeriCache’s two settings: long-context decod [PITH_FULL_IMAGE:figures/full_fig_p006_7.png] view at source ↗
Figure 8
Figure 8. Figure 8: Acceptance rate (left) and ideal speedup (right) [PITH_FULL_IMAGE:figures/full_fig_p007_8.png] view at source ↗
Figure 9
Figure 9. Figure 9: Acceptance length vs. draft length, comparing [PITH_FULL_IMAGE:figures/full_fig_p007_9.png] view at source ↗
Figure 10
Figure 10. Figure 10: Composing VeriCache with Eagle. (Left) Ac [PITH_FULL_IMAGE:figures/full_fig_p008_10.png] view at source ↗
Figure 11
Figure 11. Figure 11: Sustained decoding throughput on long [PITH_FULL_IMAGE:figures/full_fig_p009_11.png] view at source ↗
Figure 12
Figure 12. Figure 12: End-to-end request latency vs. request rate on Pipeline 1 (top) and Pipeline 2 (bottom). [PITH_FULL_IMAGE:figures/full_fig_p010_12.png] view at source ↗
Figure 13
Figure 13. Figure 13: VeriCache’s speedup over Full KV: Pipeline 1, varying KV-cache budget and HBM/interconnect ratio [PITH_FULL_IMAGE:figures/full_fig_p011_13.png] view at source ↗
Figure 14
Figure 14. Figure 14: Quality (negative KL-divergence) vs. throughput on Pipeline 1 (top) and Pipeline 2 (bottom). [PITH_FULL_IMAGE:figures/full_fig_p011_14.png] view at source ↗
Figure 15
Figure 15. Figure 15: Additional token-dropping and quantization [PITH_FULL_IMAGE:figures/full_fig_p011_15.png] view at source ↗
Figure 16
Figure 16. Figure 16: Quality vs. throughput: function-call accuracy (top), defense success rate (bottom). [PITH_FULL_IMAGE:figures/full_fig_p012_16.png] view at source ↗
Figure 17
Figure 17. Figure 17: Quality vs. throughput on Pipeline 1 long [PITH_FULL_IMAGE:figures/full_fig_p012_17.png] view at source ↗
read the original abstract

The large size of the KV cache has become a major bottleneck for serving LLMs with increasing context lengths. In response, many KV cache compression methods, such as token dropping and quantization, have been proposed. However, almost all of these methods are inherently lossy-despite minimal accuracy degradation for short outputs, their outputs increasingly diverge from full-KV-cache outputs as more tokens are decoded, which leads to catastrophic failures in code generation and tool calling. We present VeriCache, the first inference framework that ensures the same output as full-KV-cache decoding but largely preserves the high decoding throughput of a range of KV cache compression algorithms. VeriCache uses the compressed KV cache to draft tokens, then verifies them against the full KV cache. While it may seem like just speculative decoding, VeriCache requires addressing a key system challenge to work-keeping the full KV cache out of GPU memory and minimizing the overhead of swapping it in for verification. The insight is two-fold: (1) compressed-KV decoding can be parallelized with full-KV swap, because one is HBM-bandwidth-bound and the other is PCIe/network-bound, and (2) the compressed KV cache often produces output similar to the full KV cache, allowing a long drafting horizon to amortize each full-KV swap. VeriCache applies to both long-context decoding and remote prefix caching, supports a broad family of token-dropping and quantization methods through a uniform compressor interface, and composes with traditional speculative decoding. Experimental results show that VeriCache achieves up to 4X higher throughput than full-KV inference while producing identical outputs.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Referee Report

2 major / 1 minor

Summary. The manuscript presents VeriCache, an inference framework that converts lossy KV cache compression methods into lossless LLM decoding. It uses the compressed KV cache to draft tokens via speculative-style decoding and verifies the drafts against the full KV cache to guarantee identical outputs. The key system insight is that compressed-KV decoding (HBM-bandwidth bound) can be overlapped with full-KV cache swapping (PCIe/network bound), and that output similarity often permits sufficiently long drafting horizons to amortize swap costs. The approach supports long-context decoding, remote prefix caching, a uniform interface for token-dropping and quantization compressors, and composition with conventional speculative decoding. Experiments are reported to deliver up to 4X throughput versus full-KV inference while producing identical outputs.

Significance. If the performance and correctness claims are substantiated, VeriCache would offer a practical way to retain the memory and bandwidth benefits of aggressive KV compression without sacrificing output fidelity, which is especially relevant for long-context serving and distributed prefix caching. The uniform compressor interface and explicit composition with existing speculative decoding are concrete engineering contributions that could be adopted broadly. The bandwidth-overlap insight is a systems-level strength that may generalize beyond the specific setting.

major comments (2)
  1. [Abstract] Abstract: the central performance claim ('up to 4X higher throughput ... while producing identical outputs') rests on the assumption that compressed-KV drafts remain sufficiently similar to full-KV outputs for long horizons, yet the abstract itself notes that lossy methods cause outputs to 'increasingly diverge' and produce 'catastrophic failures' in code generation and tool calling. No quantitative acceptance-rate or horizon-length data are supplied for these divergence-prone regimes, which directly determines whether swap amortization can occur and whether the 4X figure is achievable.
  2. [Experimental results] Experimental results (as summarized in the abstract): the reported throughput gains lack any description of the models, workloads, hardware configuration, measurement methodology, or drafting-horizon statistics. Without these details it is impossible to evaluate whether the parallelization insight actually hides the full-KV swap latency under realistic conditions.
minor comments (1)
  1. [Design] The description of the uniform compressor interface could be expanded with a short pseudocode or API sketch to clarify how new compression methods are integrated.

Simulated Author's Rebuttal

2 responses · 0 unresolved

We thank the referee for the constructive feedback and positive assessment of VeriCache's potential impact. We address each major comment point by point below and have revised the manuscript to provide the requested details and clarifications.

read point-by-point responses

  1. Referee: [Abstract] Abstract: the central performance claim ('up to 4X higher throughput ... while producing identical outputs') rests on the assumption that compressed-KV drafts remain sufficiently similar to full-KV outputs for long horizons, yet the abstract itself notes that lossy methods cause outputs to 'increasingly diverge' and produce 'catastrophic failures' in code generation and tool calling. No quantitative acceptance-rate or horizon-length data are supplied for these divergence-prone regimes, which directly determines whether swap amortization can occur and whether the 4X figure is achievable.

    Authors: We agree that the abstract correctly identifies the divergence problem as motivation for the work. VeriCache guarantees identical outputs via verification regardless of similarity; however, throughput gains depend on sufficiently long drafting horizons to amortize swaps. The full manuscript reports acceptance rates and horizon statistics across workloads, including code generation and tool calling. In the revision we will add a dedicated table and accompanying text in Section 5 that explicitly quantifies average acceptance rates and drafting horizons for these divergence-prone tasks under the evaluated compressors, allowing readers to assess amortization directly. revision: yes

  2. Referee: [Experimental results] Experimental results (as summarized in the abstract): the reported throughput gains lack any description of the models, workloads, hardware configuration, measurement methodology, or drafting-horizon statistics. Without these details it is impossible to evaluate whether the parallelization insight actually hides the full-KV swap latency under realistic conditions.

    Authors: We acknowledge that the abstract's condensed summary omits these details. The full manuscript contains Section 5 with descriptions of models (Llama-2-7B/13B, Mistral-7B), workloads (long-context QA, code generation, tool calling), hardware (A100/H100 GPUs with PCIe/NVLink), methodology (end-to-end tokens/s, per-phase latency breakdowns), and drafting-horizon/acceptance statistics. In the revision we will expand Section 5 with additional tables and a new subsection on bandwidth-overlap measurements to make all parameters and statistics explicit and reproducible. revision: yes

Circularity Check

0 steps flagged

No circularity; claims rest on independent systems observations and experiments

full rationale

The paper describes a speculative-decoding-style framework that uses compressed KV for drafting and full KV for verification to guarantee identical outputs. Throughput gains are attributed to measured bandwidth differences (HBM-bound drafting overlapping PCIe-bound swaps) and empirical output similarity allowing amortization; these are external observations about hardware constraints and workload behavior, not self-definitions, fitted parameters presented as predictions, or results that reduce to the paper's own inputs by construction. No equations, uniqueness theorems, or self-citation chains appear in the provided text that would force the central claims.

Axiom & Free-Parameter Ledger

0 free parameters · 2 axioms · 0 invented entities

The central claim rests on domain assumptions about hardware bandwidth asymmetry and similarity of compressed versus full KV outputs; no free parameters or invented entities are introduced in the abstract.

axioms (2)
  • domain assumption Compressed KV cache produces output similar enough to full KV cache to support a long drafting horizon that amortizes full-KV swaps.
    This similarity assumption is required for the amortization argument in the abstract.
  • domain assumption Compressed-KV decoding is HBM-bandwidth-bound while full-KV swap is PCIe/network-bound, enabling effective overlap.
    This hardware assumption underpins the parallelization insight.

pith-pipeline@v0.9.0 · 5851 in / 1361 out tokens · 54999 ms · 2026-05-19T22:05:21.069105+00:00 · methodology

discussion (0)

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