Paper Citation Record · LEDGER

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning

As of 14 August 2026, this Paper Citation Record lists 37 of 37 outbound references and 2 inbound Pith citation observations for arXiv:2508.18462.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2508.18462 v1

Coverage vector

measured 37 of 37 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links, observed 2026-08-05T16:28:25.425437Z

measured 39 of 39 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-14T06:32:32.682623+00:00

measured 2 of 2 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-01T15:14:11.345252Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-05-13T21:38:18.790309Z

Reference resolution

37 of 37 outbound references displayed

verified exact1
verified fuzzy2
unresolved34
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

Observation b0b1dd94-2e62-477c-bc94-03474012e978 · outbound

This paper cites an unresolved cited work.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Unresolved cited work

Reference 1

Resolution: unresolved; raw_fallback, observed 2026-08-05T16:28:29.407492Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation ce8656ce-43b9-4f44-a176-3df3460c700f · outbound

This paper cites Scaling Laws for Neural Language Models.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Scaling Laws for Neural Language Models

Reference 2

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:22.011326Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0337f627-0707-4234-85b3-46bd78ed66b8 · outbound

This paper cites OpenCoder: The Open Cookbook for Top-Tier Code Large Language Models.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning OpenCoder: The Open Cookbook for Top-Tier Code Large Language Models

Reference 3

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:22.084503Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation ca31f762-ff0e-490c-a23a-0188dab51d15 · outbound

This paper cites Qwen2.5-Coder Technical Report.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Qwen2.5-Coder Technical Report

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:22.330173Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d05d32d1-33cb-4021-a3df-57fa32b5e964 · outbound

This paper cites DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligence.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligence

Reference 7

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:22.392151Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 8651e4f0-f01d-461b-8a53-65ae1c5a4864 · outbound

This paper cites Evaluating Large Language Models Trained on Code.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Evaluating Large Language Models Trained on Code

Reference 8

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:22.480856Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 92cf5aaa-833c-42c5-aa0b-26d4b99bfbb3 · outbound

This paper cites Reinforcement Learning from Automatic Feedback for High-Quality Unit Test Generation.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Reinforcement Learning from Automatic Feedback for High-Quality Unit Test Generation

Reference 9

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:22.554445Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0bf9aecc-0b43-4989-bd69-584a283099e7 · outbound

This paper cites Zheng, G.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Zheng, G

Reference 10

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T16:28:29.202146Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation ada31771-3cfb-470f-a593-8ea29a27ba3b · outbound

This paper cites an unresolved cited work.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Unresolved cited work

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:22.691168Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 00a45bff-a91a-4c97-902e-8a87f1a12d9b · outbound

This paper cites an unresolved cited work.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Unresolved cited work

Reference 12

Resolution: unresolved; raw_fallback, observed 2026-08-05T16:28:29.049389Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation e491920e-dcf3-44ee-852b-ca422f9268e4 · outbound

This paper cites an unresolved cited work.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Unresolved cited work

Reference 13

Resolution: unresolved; raw_fallback, observed 2026-08-05T16:28:28.806241Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation c30c8371-5e17-4705-a149-a12752f6063d · outbound

This paper cites an unresolved cited work.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Unresolved cited work

Reference 14

Resolution: unresolved; raw_fallback, observed 2026-08-05T16:28:28.533275Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation ea83a352-454f-448a-810f-8d2cc060d73a · outbound

This paper cites RLEF: Grounding Code LLMs in Execution Feedback with Reinforcement Learning.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning RLEF: Grounding Code LLMs in Execution Feedback with Reinforcement Learning

Reference 15

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:23.056538Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 0cde8a5e-ce47-45e2-8df7-822e2965564e · outbound

This paper cites REINFORCE++: Stabilizing Critic-Free Policy Optimization with Global Advantage Normalization.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning REINFORCE++: Stabilizing Critic-Free Policy Optimization with Global Advantage Normalization

Reference 16

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:23.142291Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation c1889f3e-ef72-4548-ba4c-6d72c1dcc3cf · outbound

This paper cites Nadimi, G.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Nadimi, G

Reference 17

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:23.283937Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 3e3c838c-6bd3-4b49-98a3-123f96906d39 · outbound

This paper cites an unresolved cited work.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Unresolved cited work

Reference 18

Resolution: unresolved; raw_fallback, observed 2026-08-05T16:28:28.410554Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation f81278ce-87d3-4e72-8deb-4cc18a8bb516 · outbound

This paper cites CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Reference 19

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:23.394069Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 90e026dc-a184-4fba-91a6-8254070bdacb · outbound

This paper cites HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers

Reference 20

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:23.466779Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d0f859d1-452e-4595-b8f6-a38ca7c3b2d1 · outbound

This paper cites an unresolved cited work.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Unresolved cited work

Reference 21

Resolution: unresolved; raw_fallback, observed 2026-08-05T16:28:28.225470Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 7bf63cef-2a6b-462f-baf3-5fe81a863774 · outbound

This paper cites ACECode: A Reinforcement Learning Framework for Aligning Code Efficiency and Correctness in Code Language Models.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning ACECode: A Reinforcement Learning Framework for Aligning Code Efficiency and Correctness in Code Language Models

Reference 22

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:23.667324Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation feb9cb6d-254c-4435-bb56-fb5b6f0b3753 · outbound

This paper cites o1-Coder: an o1 Replication for Coding.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning o1-Coder: an o1 Replication for Coding

Reference 23

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:23.800435Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 39cfd819-272d-4632-81b6-c14fb3c770df · outbound

This paper cites DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning

Reference 24

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:23.922141Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 4e608cb5-419b-4951-aab7-d892bb9938a0 · outbound

This paper cites an unresolved cited work.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Unresolved cited work

Reference 25

Resolution: unresolved; raw_fallback, observed 2026-08-05T16:28:28.098646Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 475105f1-9590-4e5f-9d77-1958a31d5d2e · outbound

This paper cites DeepSeekMath: Pushing the Limits of Mathematical Reasoning in Open Language Models.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning DeepSeekMath: Pushing the Limits of Mathematical Reasoning in Open Language Models

Reference 26

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:24.125394Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation f82f7251-46e0-41d7-9d66-00789839178d · outbound

This paper cites an unresolved cited work.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Unresolved cited work

Reference 27

Resolution: unresolved; raw_fallback, observed 2026-08-05T16:28:27.852419Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 5fc0b55a-aca2-4299-9980-cd5a2d4f90cf · outbound

This paper cites an unresolved cited work.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Unresolved cited work

Reference 28

Resolution: unresolved; raw_fallback, observed 2026-08-05T16:28:27.534476Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 09dc13c3-c7ea-4364-bdf8-502aeafa3a8e · outbound

This paper cites Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation

Reference 29

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:24.367469Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation a74a5bf7-a0dd-4cc3-b120-5d3a66f8d7c3 · outbound

This paper cites an unresolved cited work.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Unresolved cited work

Reference 30

Resolution: unresolved; raw_fallback, observed 2026-08-05T16:28:27.139256Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 892a309e-02ba-4dd4-aea2-c9b5976a8fcf · outbound

This paper cites Zhang, Y.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Zhang, Y

Reference 31

Resolution: verified fuzzy; raw_fallback, observed 2026-08-05T16:28:26.844108Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation f6dc1164-875f-48ca-a793-08ebc49ea0a5 · outbound

This paper cites LlamaFactory: Unified Efficient Fine-Tuning of 100+ Language Models.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning LlamaFactory: Unified Efficient Fine-Tuning of 100+ Language Models

Reference 32

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:24.726902Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation cb3afca8-1dd9-4d81-9918-12f65db4bb6d · outbound

This paper cites OpenRLHF: An Easy-to-use, Scalable and High-performance RLHF Framework.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning OpenRLHF: An Easy-to-use, Scalable and High-performance RLHF Framework

Reference 33

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:24.805658Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 954cfc98-b21b-401b-ba92-f5c7e113d066 · outbound

This paper cites StarCoder: may the source be with you!.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning StarCoder: may the source be with you!

Reference 34

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:24.928836Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 66de2aae-3a1c-4afa-9a9d-92cffd650c8b · outbound

This paper cites Code Llama: Open Foundation Models for Code.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Code Llama: Open Foundation Models for Code

Reference 35

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:24.988529Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6b006717-fcd9-4e1f-a184-e2b3d461966e · outbound

This paper cites Qwen Technical Report.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Qwen Technical Report

Reference 36

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:25.076248Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 66784273-8fd1-4643-8000-716b39dad172 · outbound

This paper cites ChipNeMo: Domain-Adapted LLMs for Chip Design.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning ChipNeMo: Domain-Adapted LLMs for Chip Design

Reference 37

Resolution: unresolved; no resolver link, observed 2026-08-05T16:28:25.147288Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 70376b72-9478-4bd3-9e7c-281dce07532d · outbound

This paper cites Thakur, B.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Thakur, B

Reference 38

Resolution: verified exact; raw_fallback, observed 2026-08-05T16:28:25.852746Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 7f227235-c5d5-4df6-a2d7-9423e24631d1 · outbound

This paper cites an unresolved cited work.

VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning Unresolved cited work

Reference 39

Resolution: unresolved; raw_fallback, observed 2026-08-05T16:28:26.603736Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Pith citing papers

Observation 4d427995-b5cf-431d-a3f8-f2b2b38207dc · inbound

TestDecision: Sequential Test Suite Generation via Greedy Optimization and Reinforcement Learning cites this paper.

TestDecision: Sequential Test Suite Generation via Greedy Optimization and Reinforcement Learning VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning

Reference 54

Resolution: verified exact; arxiv_id, observed 2026-05-13T21:38:18.791535Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-14T06:32:32.682623+00:00.

Observation 174ff88f-b81f-44d3-ae42-5af09ba88d10 · inbound

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs cites this paper.

A Progressive Approach to Synthesizable RTL Design Generation Using LLMs VERIRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning

Reference 25

Resolution: unresolved; no resolver link, observed 2026-08-01T15:14:11.345252Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.