Paper Citation Record · LEDGER

VeriGen: A Large Language Model for Verilog Code Generation

As of 15 August 2026, this Paper Citation Record lists 0 of 0 outbound references and 12 inbound Pith citation observations for arXiv:2308.00708.

A citation records a reference. It does not transfer a finding from one paper to another.

pith.paper-citation-record.v1
2308.00708 v1

Coverage vector

measured 0 of 0 reference resolution

Typed states for the displayed outbound observations.

Source: paper_references, paper_reference_links

measured 12 of 12 standing notices

One-hop event checks from named stored sources.

Source: scholarly_work_events, retraction_status_cache, observed 2026-08-15T06:32:42.880941+00:00

measured 12 of 12 inbound itemization

Pith citing papers itemized under the disclosed page cap.

Source: paper_references, paper_reference_links, observed 2026-08-12T13:27:04.792249Z

measured 0 of 1 external citation measurements

A source-named dated measurement, never combined with another source.

Source: arxiv_reference, observed 2026-07-01T18:45:58.323304Z

Reference resolution

0 of 0 outbound references displayed

verified exact0
verified fuzzy0
unresolved0
parse uncertain0
malformed identifier0
metadata mismatch0

External citation measurements

No source-named external measurement is stored.

Outbound references

No outbound reference observations are available for this paper version.

Pith citing papers

Observation c7438387-f811-450c-aceb-2221d9541330 · inbound

UVLLM: An Automated Universal RTL Verification Framework using LLMs cites this paper.

UVLLM: An Automated Universal RTL Verification Framework using LLMs VeriGen: A Large Language Model for Verilog Code Generation

Reference 11

Resolution: unresolved; no resolver link, observed 2026-08-12T13:27:04.792249Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 6d45cf80-f53d-4258-b6a2-216737f0f3f4 · inbound

From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification cites this paper.

From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification VeriGen: A Large Language Model for Verilog Code Generation

Reference 24

Resolution: verified exact; arxiv_id, observed 2026-05-22T18:01:54.476323Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 3147073d-4cd0-4371-9964-e11877bc1919 · inbound

BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis cites this paper.

BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis VeriGen: A Large Language Model for Verilog Code Generation

Reference 10

Resolution: unresolved; no resolver link, observed 2026-08-07T04:31:18.492402Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation d1e3f49e-500a-4b91-84d8-4cc636301a15 · inbound

Mitigating hallucinations and omissions in LLMs for invertible problems: An application to hardware logic design automation cites this paper.

Mitigating hallucinations and omissions in LLMs for invertible problems: An application to hardware logic design automation VeriGen: A Large Language Model for Verilog Code Generation

Reference 31

Resolution: verified exact; arxiv_id, observed 2026-05-17T05:29:05.078923Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation b25841ac-8891-44c2-89fa-e9247f80e399 · inbound

VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation cites this paper.

VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation VeriGen: A Large Language Model for Verilog Code Generation

Reference 17

Resolution: verified exact; arxiv_id, observed 2026-05-16T07:47:32.966395Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 29ded5f3-da40-4553-924f-54625fd7dae3 · inbound

InCoder-32B-Thinking: Industrial Code World Model for Thinking cites this paper.

InCoder-32B-Thinking: Industrial Code World Model for Thinking VeriGen: A Large Language Model for Verilog Code Generation

Reference 36

Resolution: metadata mismatch; arxiv_id, observed 2026-05-13T18:58:08.655064Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation dc62332d-ed56-4ce7-ad1f-f5e808e9a849 · inbound

Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design cites this paper.

Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design VeriGen: A Large Language Model for Verilog Code Generation

Reference 30

Resolution: verified exact; arxiv_id, observed 2026-05-11T00:25:50.588995Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation aea19ce1-6a48-413a-b802-94f45df72eb2 · inbound

ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration cites this paper.

ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration VeriGen: A Large Language Model for Verilog Code Generation

Reference 4

Resolution: verified exact; arxiv_id, observed 2026-05-11T13:36:08.344254Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation c0c9747f-9e72-4777-bbd9-de1fc2f26e35 · inbound

From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation cites this paper.

From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation VeriGen: A Large Language Model for Verilog Code Generation

Reference 13

Resolution: verified exact; arxiv_id, observed 2026-05-11T20:41:11.818781Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 59dbfcdc-f35a-467b-a530-fed84cfca5b4 · inbound

Agentic Hardware Design as Repository-Level Code Evolution cites this paper.

Agentic Hardware Design as Repository-Level Code Evolution VeriGen: A Large Language Model for Verilog Code Generation

Reference 10

Resolution: metadata mismatch; arxiv_id, observed 2026-07-01T18:45:58.325077Z

Source-reported events for the cited work

No event found in the named queried sources as of 2026-08-15T06:32:42.880941+00:00.

Observation 3d4a764e-0cbc-49a2-b254-45781b7201f0 · inbound

Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair cites this paper.

Open-Source LLM-Driven Formal Verification: A Multi-Agent Pipeline for RTL Repair VeriGen: A Large Language Model for Verilog Code Generation

Reference 6

Resolution: unresolved; no resolver link, observed 2026-08-03T01:29:16.160698Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.

Observation 197c9d52-276a-48e8-bdc6-c23203c00cc3 · inbound

AtumAI: A Principled Framework for Agentic Generation of Datacenter Control-Plane Policies cites this paper.

AtumAI: A Principled Framework for Agentic Generation of Datacenter Control-Plane Policies VeriGen: A Large Language Model for Verilog Code Generation

Reference 49

Resolution: unresolved; no resolver link, observed 2026-08-04T04:39:20.645175Z

Source-reported events for the cited work

Unavailable: canonical work link unavailable.