Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing

Boxun Xu; Chen He; Peng Li; Rebecca Chen; Yuxuan Yin

REVIEW 3 major objections 5 minor 19 references

Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing

T0 review · 3 major / 5 minor · reviewed 2026-08-05 · deepseek-v4-flash

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Pith's one-line read Transfer learning pins 5nm chips' minimum voltage to a 3.89 mV error.

desk verdict Useful industrial result, but the central transfer-learning claim lacks a direct control and the numbers have no error bars; worth refereeing, needs revision. read the letter →

arxiv 2509.00035 v1 pith:HZ4R5AGN submitted 2025-08-21 cs.LG cs.AI

Yuxuan Yin , Rebecca Chen , Boxun Xu , Chen He , Peng Li This is my paper · ORCID

classification cs.LGcs.AI

keywords Vminpredictiontransferlearningsiliconodometerprocessvariationsemiconductormanufacturingminimumoperatingvoltageneuralnetwork5nmtechnology

verification ladder T0 review T1 audit T2 compute T3 formal

The pith

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The reading

This paper tries to show that minimum operating voltage (Vmin) of advanced 5nm chips can be predicted accurately even when only a few hundred chips are available for training. The key move is to pretrain a neural network on abundant data from the mature 16nm node, then fine-tune only the shallow layers on the scarce 5nm data. Adding input features from on-chip silicon odometer sensors, which capture localized process variation, further improves accuracy. If correct, the approach would let chipmakers screen and bin parts early in a new node's life without waiting for large datasets or expensive direct Vmin tests.

What carries the argument

The central object is a feedforward network with three stacked modules: a feature fusion layer that maps manually grouped feature families (e.g., threshold voltage, leakage, silicon odometer readings) into a fixed number of hidden features via learnable linear projections; an embedding layer that projects the fused features of different node-specific sizes into a common 32-dimensional space; and hidden layers that are transferred. During transfer, the hidden layers are copied from the 16nm model and frozen, leaving only the fusion, embedding, and output layers to be trained on the 5nm data. The silicon odometer is a pair of ring oscillators whose beat frequency conventionally measures aging;

What would settle it

Retrain the target model on the same 25% of 5nm data but with the middle layers randomly initialized and frozen (no 16nm pretraining), keeping all other settings identical; if the test RMSE stays near 3.89 mV, the transferred representation is not doing the work, whereas a substantially larger error would confirm the pretrained layers are essential.

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Extended reading notes

Core claim

The paper claims that a transfer learning network—pretrained on 5,239 16nm automotive dies and fine-tuned on just 25% of 415 5nm dies—predicts the average Vmin with a test RMSE of 3.89 mV. This beats a neural network trained from scratch on the same 5nm data (5.81 mV), as well as linear regression (7.09 mV), XGBoost (5.39 mV), and CatBoost (4.59 mV). An ablation shows that adding 124 silicon odometer features lowers RMSE from 11.57 mV to 7.09 mV for a linear model and from 4.66 mV to 3.89 mV for the transferred network, indicating that the odometer data carries information about process variation that POSt and parametric features do not. The paper interprets these results as evidence that le

Load-bearing premise

The frozen middle layers learned on 16nm data must still be useful for 5nm; if the process change makes those layers encode 16nm-only patterns, transfer learning adds nothing and the 3.89 mV result would be due to the fine-tuned shallow layers alone.

Editorial extensions

If this is right

Pretraining on a mature node may provide a generalizable representation of how process variation maps to Vmin, so the same recipe could be reused for future node pairs (for example, 5nm to 3nm) with minimal new data.
Silicon odometer data, currently deployed for reliability and aging tracking, can be repurposed at manufacturing time as a cheap, high-resolution surrogate for direct Vmin testing.
Freezing the transferred hidden layers turns the target training problem into a shallow, low-parameter regression, which is why the model can fine-tune on only a few hundred dies without overfitting.
Jointly predicting all Vmin patterns in one multi-task output layer appears to stabilize training and reduce overfitting on small target datasets, a departure from single-pattern model training.
If the approach generalizes, production testing of automotive chips at advanced nodes could shift from expensive structural Vmin tests to prediction based on low-cost sensor and parametric measurements.

Reading between the lines

Editorial extensions of the paper, not claims the author makes directly.

The 3.89 mV result is consistent with the hypothesis that the 16nm-to-5nm process shift preserves the qualitative shape of the variation-to-Vmin mapping, leaving only a feature-distribution shift; a direct probe would be to repeat the experiment with frozen layers initialized randomly—if the error stays near 3.89 mV, the improvement comes from the shallow fine-tuning, not the transferred represent
Silicon odometer placement density is likely a tunable design knob; feature-attribution or sensitivity analysis on the trained model could identify which odometer locations matter most, guiding sensor floorplanning for future nodes.
The same multi-output transfer setup could be extended to predict other per-chip performance metrics such as Fmax or leakage, using the same odometer inputs, without needing a new architecture.
If transfer learning proves portable across nodes, the semiconductor industry could shrink the time between first silicon and volume production by relying on legacy-data-driven models during early ramps, when test data is scarcest.

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Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, and a circularity audit.

Desk Editor's Note

read the letter

Honest take: this is a solid engineering paper with a clear practical problem—predicting Vmin at a 5nm node with very little data—and it reports a plausible solution: pretrain on 16nm data, freeze hidden layers, add silicon odometer features. The industrial dataset (5,239 16nm dies, 415 5nm dies) is real and the odometer ablation (Fig. 5) shows consistent gains. The feature-grouping and alignment approach is sensible, and the authors are candid that this is an extension of their own prior work rather than a radically new idea.

The main soft spot is the one the stress-test flags: the transferred network freezes all hidden layers and trains only the fusion, embedding, and output layers, so it has far fewer trainable parameters than the from-scratch network (5.81 mV). Without a control that uses the same frozen architecture but random initialization, the 3.89 mV result could just be implicit regularization, not knowledge transferred from 16nm. That control is missing. This is a load-bearing flaw in the causal claim, though not in the practical result—if a random-initialized frozen net gives the same accuracy, the method still works but the explanation is wrong.

Second, all RMSEs are single numbers from one random split. No error bars, no repeats, no statistical tests. For a paper whose headline is "significantly improves," that's weak. The target definition also shifts: Section V-B says "average Vmin across all patterns and temperatures," but the network has multiple outputs (o(b) and o(t)). That needs clarification. Hyperparameters are also odd—100k epochs, batch size 32—and there's no discussion of convergence or overfitting checks. Data and code are not released, which is expected for industrial data but limits reproducibility.

On the positive side, the paper is clearly written, the baseline comparisons are reasonable, and the ablation for silicon odometer features is the right kind of evidence. The citation pattern is fine; the authors cite their own prior work because it is directly relevant.

Verdict: conditional. The paper deserves peer review because the problem matters and the method is plausible, but the authors need to add the random-initialized frozen control, run repeated splits with confidence intervals, clarify the target definition, and ideally release anonymized data or code. I would not cite it in my own work yet, but would bring it to a reading group to discuss the control issue.

Referee Report

3 major / 5 minor

Summary. The paper proposes a transfer learning framework for predicting minimum operating voltage (Vmin) in advanced semiconductor nodes. A neural network is pretrained on 5,239 16nm dies using POSt and parametric test features; the hidden layers are then copied to a 5nm model and frozen, while the feature fusion, embedding, and output layers are fine-tuned on only 415 5nm dies. The 5nm model additionally receives silicon odometer features, which are available only at the 5nm node. Experiments report a test RMSE of 3.89 mV for the transferred network on 5nm, compared with 5.81 mV for a from-scratch neural network and 4.59 mV for CatBoost. An ablation study (Fig. 5) shows that adding silicon odometer features improves both a linear model and the transferred network.

Significance. If the results hold, this is a practically relevant contribution to semiconductor test and performance modeling: it addresses the real problem of scarce labeled data at advanced technology nodes and introduces silicon odometer sensing as a useful input modality. The use of real industrial 16nm and 5nm datasets is a strength, as is the multi-pattern output formulation and the explicit ablation of the odometer features. However, the current evidence is not yet sufficient to support the central claim that the improvement comes from cross-node knowledge transfer rather than from architectural regularization or baseline unfairness.

major comments (3)

[V-C; Eq. (10)-(11)] The reported 3.89 mV for the transferred model is produced by freezing hidden layers initialized from 16nm pretraining. The only deep-network comparator is a from-scratch network trained end-to-end (5.81 mV), which has many more trainable parameters and no freezing. This confounds the effect of knowledge transfer with the effect of freezing as an implicit regularizer. Please add a control that uses the same fine-tuning protocol (freeze hidden layers, train only fusion/embedding/output) but with randomly initialized hidden layers. If this control matches or beats 3.89 mV, the paper's title claim that legacy 16nm data provide measurable benefit is unsupported. This control is essential and should be run over multiple random seeds.
[V-A, V-B, V-C; Tables II-III] Every RMSE in Tables II and III is a single number from one random 75/25 split, with no repeated splits, no error bars, and no confidence intervals. On a 5nm dataset of only 415 dies, with 25% used for training, the gap between the best model (3.89 mV) and CatBoost (4.59 mV) is small relative to typical split-to-split variability. Please report mean ± std over at least 5–10 random splits, or bootstrap confidence intervals, for all models and ablations. Without this, the claim of 'best performance' is not statistically supported.
[V-A; Table III] Baseline comparability is a concern. Linear regression, XGBoost, and CatBoost are given only three CFS-selected features, while the neural networks receive all features through the fusion layer. The claimed superiority over traditional ML baselines may therefore reflect feature-set size rather than the proposed architecture or transfer learning. Please report baselines trained on all features (or on the same fused feature representation) to make the comparison fair.

minor comments (5)

[Title] The title contains a typo: 'V oltage' should be 'Voltage'.
[IV-C] The notation 'memb-dimensional' is unclear; define the embedding dimension explicitly, e.g., m_emb.
[V-A] The training protocol states 100k epochs with no early stopping or validation-based stopping criterion. Please clarify how overfitting is avoided, especially on the small 5nm training set.
[V-B/V-C] In Section V-B the prediction target is stated as 'average Vmin across all patterns and temperatures'; Section V-C does not repeat this. Please clarify whether Table III reports RMSE on the same averaged target or on all individual patterns.
[Table I] For the 5nm row, the grouped POSt feature counts 12, 7, 18 sum to 37; the text calls them '37 grouped POSt features.' Consider adding the total in the table for readability.

Circularity Check

0 steps flagged · score 2.0 of 10

No significant circularity: central results are held-out empirical evaluations; self-citations are non-load-bearing.

full rationale

The paper's central claim, stated in Section V-C and Table III, is that the transferred neural network achieves a held-out test RMSE of 3.89 mV on the 5nm dataset using only 25% of the 5nm data for training. This is a genuine out-of-sample prediction, not a quantity constructed from its own inputs. The silicon odometer contribution is tested by an ablation study (Fig. 5) comparing POSt-only vs. POSt+siliconOdo inputs on held-out data, so it is empirically grounded rather than definitionally forced. No equation in the paper defines Vmin in terms of the model's own outputs, and no fitted parameter is renamed as a prediction: Eq. (1) is a standard regression formulation, and Eq. (10)-(11) define a hard-constraint fine-tuning objective (θ_hidden = θ_base_hidden), which is a training-strategy choice, not a reduction of the target to its inputs. The authors cite their own prior works ([4], [10], [15], [11]) for baseline construction (CFS feature selection, 'Following [4], [10], [15]', Section V-A), for background on Vmin modeling, and for the problem setup; these citations are standard self-referencing for continuity and do not carry the central premise that transfer learning works — that premise is tested empirically against external baselines (XGBoost, CatBoost, linear regression, from-scratch neural network). The most substantive concern is experimental rather than circular: the transferred model freezes hidden layers, drastically reducing the number of trainable parameters relative to the from-scratch network, and no control with randomly initialized frozen hidden layers is reported, so part of the gain could be attributed to implicit regularization rather than knowledge transfer from 16nm. This is a missing baseline that affects the strength of the mechanism claim, but it is not a by-construction equivalence between input and output. The reviewer-rule check finds no passage asserting an unresolved limitation or omitted proof that would indicate circularity; the paper is self-contained against external benchmarks, and the derivation chain is empirical with held-out evaluation. Accordingly, the paper exhibits no significant circularity, with only minor non-load-bearing self-citations.

Assumptions & free parameters 6 free parameters · 5 assumptions · 0 invented entities

No new physical entities are introduced; silicon odometers are prior art (refs [7]-[9]). The central claim is empirical, so free parameters are the hand-chosen hyperparameters of the neural network, and axioms are the domain assumptions about transferability and sensor validity.

free parameters (6)

k (fusion hidden features per functional group) = 2
Hand-chosen in Section V-A; controls information compression in the feature fusion layer and affects model capacity and transferability.
embedding dimension = 32
Hand-chosen hyperparameter for the embedding layer that maps fused features into a shared space.
hidden layer sizes = 64, 16, 64
Hand-chosen architecture for the three fully connected hidden layers.
learning rate = 1e-3
Adam optimizer learning rate selected by the authors.
batch size = 32
Training batch size chosen for both base and target models.
training epochs = 100k
Fixed training duration with no described early stopping or validation-based model selection.

assumptions (5)

domain assumption A representation learned on 16nm POSt features transfers to 5nm POSt features even when hidden layers are frozen.
Invoked in Section IV-D (Eq. 10-11) when freezing hidden layers; if false, transfer learning cannot work.
domain assumption At T0, the stressed and reference ring oscillators of a silicon odometer run at identical frequencies, so odometer frequency is a valid process-variation monitor.
Stated in Section III-B; this is the basis for using silicon odometer outputs as input features for Vmin prediction.
domain assumption The measured Vmin labels and POSt/odometer features are accurate and consistent across the two technology nodes despite different test flows and temperatures.
Implicit in Section V-A; differences in test settings are acknowledged but assumed not to break comparability.
standard math MSE loss and standard supervised learning assumptions hold for the Vmin regression problem.
Equations (2) and (5) define the objective; assumes i.i.d. noise and reliable labels.
ad hoc to paper Feature grouping based on domain expertise is meaningful and aligns features across technology nodes.
Section IV-B groups features into functional types manually; the groupings are not derived from data and could affect transfer.

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Cite this review

Pith. "Pith review of Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing." pith.science (2026). https://pith.science/paper/HZ4R5AGN

@misc{pith2026250900035,
  author       = {Pith},
  title        = {Pith review of: Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing},
  year         = {2026},
  howpublished = {\url{https://pith.science/paper/HZ4R5AGN}},
  note         = {Machine review of arXiv:2509.00035}
}

abstract

Accurate prediction of chip performance is critical for ensuring energy efficiency and reliability in semiconductor manufacturing. However, developing minimum operating voltage ($V_{min}$) prediction models at advanced technology nodes is challenging due to limited training data and the complex relationship between process variations and $V_{min}$. To address these issues, we propose a novel transfer learning framework that leverages abundant legacy data from the 16nm technology node to enable accurate $V_{min}$ prediction at the advanced 5nm node. A key innovation of our approach is the integration of input features derived from on-chip silicon odometer sensor data, which provide fine-grained characterization of localized process variations -- an essential factor at the 5nm node -- resulting in significantly improved prediction accuracy.

Figures

Figures reproduced from arXiv: 2509.00035 by the authors.

**Figure 2.** High level diagram of a silicon odometer [9]. [PITH_FULL_IMAGE:figures/full_fig_p003_2.png] view at source ↗

**Figure 3.** Illustration of POSt and silicon odometer placement: [PITH_FULL_IMAGE:figures/full_fig_p003_3.png] view at source ↗

Figures from the paper (2 more)

**Figure 4.** Figure 4: Proposed transfer learning framework for [PITH_FULL_IMAGE:figures/full_fig_p004_4.png]

**Figure 5.** Figure 5: The effectiveness of silicon odometer features. [PITH_FULL_IMAGE:figures/full_fig_p008_5.png]

Discussion (0). Continue with ORCID to comment.

Reference graph

Works this paper leans on

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Available: https://doi.org/10.1145/3649329.3657338

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Pith tools

Reviewed August 5, 2026 · model on record in the stance chip above.

[1] [1]

Wafer level stress: Enabling zero defect quality for automotive microcontrollers without package burn-in,

C. He and Y . Yu, “Wafer level stress: Enabling zero defect quality for automotive microcontrollers without package burn-in,” in 2020 IEEE International Test Conference (ITC) , 2020, pp. 1–10

work page 2020

[2] [2]

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T. Chen and C. Guestrin, “Xgboost: A scalable tree boosting system,” in Proceedings of the 22nd acm sigkdd international conference on knowledge discovery and data mining , 2016, pp. 785–794

2016

[3] [3]

Catboost: unbiased boosting with categorical features,

L. Prokhorenkova, G. Gusev, A. V orobev, A. V . Dorogush, and A. Gulin, “Catboost: unbiased boosting with categorical features,” in Advances in neural information processing systems , vol. 31, 2018

work page 2018

[4] [4]

Domain-specific machine learning based minimum operating voltage prediction using on-chip monitor data,

Y . Yin, R. Chen, C. He, and P. Li, “Domain-specific machine learning based minimum operating voltage prediction using on-chip monitor data,” in 2023 IEEE International Test Conference (ITC) , 2023, pp. 99–104

work page 2023

[5] [5]

Deep Lattice Networks and Partial Monotonic Functions,

S. You, D. Ding, K. Canini, J. Pfeifer, and M. Gupta, “Deep Lattice Networks and Partial Monotonic Functions,” in Advances in Neural Information Processing Systems , vol. 30, 2017

work page 2017

[6] [6]

Lattice regression,

E. Garcia and M. Gupta, “Lattice regression,” Advances in Neural Information Processing Systems , vol. 22, 2009

work page 2009

[7] [7]

Silicon odometer: An on- chip reliability monitor for measuring frequency degradation of digital circuits,

T.-H. Kim, R. Persaud, and C. H. Kim, “Silicon odometer: An on- chip reliability monitor for measuring frequency degradation of digital circuits,” IEEE Journal of Solid-State Circuits , vol. 43, no. 4, pp. 874– 880, 2008

work page 2008

[8] [8]

An all-in-one silicon odometer for separately monitoring hci, bti, and tddb,

J. Keane, X. Wang, D. Persaud, and C. H. Kim, “An all-in-one silicon odometer for separately monitoring hci, bti, and tddb,” IEEE Journal of Solid-State Circuits, vol. 45, no. 4, pp. 817–829, 2010

work page 2010